commit 6e0177dfbffdd2b140cfab8f8720604b5b9cbf7b Author: lw-everestlinux Date: Wed Oct 5 12:03:03 2022 -0400 Initial commit diff --git a/COPYRIGHT b/COPYRIGHT new file mode 100644 index 0000000..5ec5e0b --- /dev/null +++ b/COPYRIGHT @@ -0,0 +1,16 @@ +Copyright Notes +=============== + +The musl-cross-make build tools and documentation are licensed under +the MIT/Expat license as found in the `LICENSE` file. + +Note that this license does not cover the patches (`patches/`) or +resulting binary artifacts. + +Each patch (`patches/`) is distributed under the terms of the license +of the upstream project to which it is applied. + +Similarly, any resulting binary artifacts produced using this build +tooling retain the original licensing from the upstream projects. The +authors of musl-cross-make do not make any additional copyright claims +to these artifacts. diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..793e474 --- /dev/null +++ b/LICENSE @@ -0,0 +1,19 @@ +Copyright (c) 2015-2020 Rich Felker, et al. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..09f8c2d --- /dev/null +++ b/Makefile @@ -0,0 +1,189 @@ + +SOURCES = sources + +CONFIG_SUB_REV = 3d5db9ebe860 +BINUTILS_VER = 2.33.1 +GCC_VER = 9.4.0 +MUSL_VER = 1.2.3 +GMP_VER = 6.1.2 +MPC_VER = 1.1.0 +MPFR_VER = 4.0.2 +LINUX_VER = headers-4.19.88-1 + +GNU_SITE = https://ftpmirror.gnu.org/gnu +GCC_SITE = $(GNU_SITE)/gcc +BINUTILS_SITE = $(GNU_SITE)/binutils +GMP_SITE = $(GNU_SITE)/gmp +MPC_SITE = $(GNU_SITE)/mpc +MPFR_SITE = $(GNU_SITE)/mpfr +ISL_SITE = http://isl.gforge.inria.fr/ + +MUSL_SITE = https://musl.libc.org/releases +MUSL_REPO = git://git.musl-libc.org/musl + +LINUX_SITE = https://cdn.kernel.org/pub/linux/kernel +LINUX_HEADERS_SITE = http://ftp.barfooze.de/pub/sabotage/tarballs/ + +DL_CMD = wget -c -O +SHA1_CMD = sha1sum -c + +COWPATCH = $(CURDIR)/cowpatch.sh + +HOST = $(if $(NATIVE),$(TARGET)) +BUILD_DIR = build/$(if $(HOST),$(HOST),local)/$(TARGET) +OUTPUT = $(CURDIR)/output$(if $(HOST),-$(HOST)) + +REL_TOP = ../../.. + +-include config.mak + +SRC_DIRS = gcc-$(GCC_VER) binutils-$(BINUTILS_VER) musl-$(MUSL_VER) \ + $(if $(GMP_VER),gmp-$(GMP_VER)) \ + $(if $(MPC_VER),mpc-$(MPC_VER)) \ + $(if $(MPFR_VER),mpfr-$(MPFR_VER)) \ + $(if $(ISL_VER),isl-$(ISL_VER)) \ + $(if $(LINUX_VER),linux-$(LINUX_VER)) + +all: + +clean: + rm -rf gcc-* binutils-* musl-* gmp-* mpc-* mpfr-* isl-* build build-* linux-* + +distclean: clean + rm -rf sources + + +# Rules for downloading and verifying sources. Treat an external SOURCES path as +# immutable and do not try to download anything into it. + +ifeq ($(SOURCES),sources) + +$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/gmp*)): SITE = $(GMP_SITE) +$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/mpc*)): SITE = $(MPC_SITE) +$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/mpfr*)): SITE = $(MPFR_SITE) +$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/isl*)): SITE = $(ISL_SITE) +$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/binutils*)): SITE = $(BINUTILS_SITE) +$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/gcc*)): SITE = $(GCC_SITE)/$(basename $(basename $(notdir $@))) +$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/musl*)): SITE = $(MUSL_SITE) +$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-5*)): SITE = $(LINUX_SITE)/v5.x +$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-4*)): SITE = $(LINUX_SITE)/v4.x +$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-3*)): SITE = $(LINUX_SITE)/v3.x +$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-2.6*)): SITE = $(LINUX_SITE)/v2.6 +$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-headers-*)): SITE = $(LINUX_HEADERS_SITE) + +$(SOURCES): + mkdir -p $@ + +$(SOURCES)/config.sub: | $(SOURCES) + mkdir -p $@.tmp + cd $@.tmp && $(DL_CMD) $(notdir $@) "http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=$(CONFIG_SUB_REV)" + cd $@.tmp && touch $(notdir $@) + cd $@.tmp && $(SHA1_CMD) $(CURDIR)/hashes/$(notdir $@).$(CONFIG_SUB_REV).sha1 + mv $@.tmp/$(notdir $@) $@ + rm -rf $@.tmp + +$(SOURCES)/%: hashes/%.sha1 | $(SOURCES) + mkdir -p $@.tmp + cd $@.tmp && $(DL_CMD) $(notdir $@) $(SITE)/$(notdir $@) + cd $@.tmp && touch $(notdir $@) + cd $@.tmp && $(SHA1_CMD) $(CURDIR)/hashes/$(notdir $@).sha1 + mv $@.tmp/$(notdir $@) $@ + rm -rf $@.tmp + +endif + + +# Rules for extracting and patching sources, or checking them out from git. + +musl-git-%: + rm -rf $@.tmp + git clone -b $(patsubst musl-git-%,%,$@) $(MUSL_REPO) $@.tmp + cd $@.tmp && git fsck + mv $@.tmp $@ + +%.orig: $(SOURCES)/%.tar.gz + case "$@" in */*) exit 1 ;; esac + rm -rf $@.tmp + mkdir $@.tmp + ( cd $@.tmp && tar zxvf - ) < $< + rm -rf $@ + touch $@.tmp/$(patsubst %.orig,%,$@) + mv $@.tmp/$(patsubst %.orig,%,$@) $@ + rm -rf $@.tmp + +%.orig: $(SOURCES)/%.tar.bz2 + case "$@" in */*) exit 1 ;; esac + rm -rf $@.tmp + mkdir $@.tmp + ( cd $@.tmp && tar jxvf - ) < $< + rm -rf $@ + touch $@.tmp/$(patsubst %.orig,%,$@) + mv $@.tmp/$(patsubst %.orig,%,$@) $@ + rm -rf $@.tmp + +%.orig: $(SOURCES)/%.tar.xz + case "$@" in */*) exit 1 ;; esac + rm -rf $@.tmp + mkdir $@.tmp + ( cd $@.tmp && tar Jxvf - ) < $< + rm -rf $@ + touch $@.tmp/$(patsubst %.orig,%,$@) + mv $@.tmp/$(patsubst %.orig,%,$@) $@ + rm -rf $@.tmp + +%: %.orig | $(SOURCES)/config.sub + case "$@" in */*) exit 1 ;; esac + rm -rf $@.tmp + mkdir $@.tmp + ( cd $@.tmp && $(COWPATCH) -I ../$< ) + test ! -d patches/$@ || cat patches/$@/* | ( cd $@.tmp && $(COWPATCH) -p1 ) + if test -f $$@ '%s\n' \ + "TARGET = $(TARGET)" \ + "HOST = $(HOST)" \ + "MUSL_SRCDIR = $(REL_TOP)/musl-$(MUSL_VER)" \ + "GCC_SRCDIR = $(REL_TOP)/gcc-$(GCC_VER)" \ + "BINUTILS_SRCDIR = $(REL_TOP)/binutils-$(BINUTILS_VER)" \ + $(if $(GMP_VER),"GMP_SRCDIR = $(REL_TOP)/gmp-$(GMP_VER)") \ + $(if $(MPC_VER),"MPC_SRCDIR = $(REL_TOP)/mpc-$(MPC_VER)") \ + $(if $(MPFR_VER),"MPFR_SRCDIR = $(REL_TOP)/mpfr-$(MPFR_VER)") \ + $(if $(ISL_VER),"ISL_SRCDIR = $(REL_TOP)/isl-$(ISL_VER)") \ + $(if $(LINUX_VER),"LINUX_SRCDIR = $(REL_TOP)/linux-$(LINUX_VER)") \ + "-include $(REL_TOP)/config.mak" + +all: | $(SRC_DIRS) $(BUILD_DIR) $(BUILD_DIR)/Makefile $(BUILD_DIR)/config.mak + cd $(BUILD_DIR) && $(MAKE) $@ + +install: | $(SRC_DIRS) $(BUILD_DIR) $(BUILD_DIR)/Makefile $(BUILD_DIR)/config.mak + cd $(BUILD_DIR) && $(MAKE) OUTPUT=$(OUTPUT) $@ + +endif + +.SECONDARY: diff --git a/README.md b/README.md new file mode 100644 index 0000000..2c346df --- /dev/null +++ b/README.md @@ -0,0 +1,170 @@ +musl-cross-make +=============== + +This is the second generation of musl-cross-make, a fast, simple, +but advanced makefile-based approach for producing musl-targeting +cross compilers. Features include: + +- Single-stage GCC build, used to build both musl libc and its own + shared target libs depending on libc. + +- No hard-coded absolute paths; resulting cross compilers can be + copied/moved anywhere. + +- Ability to build multiple cross compilers for different targets + using a single set of patched source trees. + +- Nothing is installed until running `make install`, and the + installation location can be chosen at install time. + +- Automatic download of source packages, including GCC prerequisites + (GMP, MPC, MPFR), using https and checking hashes. + +- Automatic patching with canonical musl support patches and patches + which provide bug fixes and features musl depends on for some arch + targets. + + +Usage +----- + +The build system can be configured by providing a `config.mak` file in +the top-level directory. The only mandatory variable is `TARGET`, which +should contain a gcc target tuple (such as `i486-linux-musl`), but many +more options are available. See the provided `config.mak.dist` and +`presets/*` for examples. + +To compile, run `make`. To install to `$(OUTPUT)`, run `make install`. + +The default value for `$(OUTPUT)` is output; after installing here you +can move the cross compiler toolchain to another location as desired. + + + +Supported `TARGET`s +------------------- + +The following is a non-exhaustive list of `$(TARGET)` tuples that are +believed to work: + +- `aarch64[_be]-linux-musl` +- `arm[eb]-linux-musleabi[hf]` +- `i*86-linux-musl` +- `microblaze[el]-linux-musl` +- `mips-linux-musl` +- `mips[el]-linux-musl[sf]` +- `mips64[el]-linux-musl[n32][sf]` +- `powerpc-linux-musl[sf]` +- `powerpc64[le]-linux-musl` +- `riscv64-linux-musl` +- `s390x-linux-musl` +- `sh*[eb]-linux-musl[fdpic][sf]` +- `x86_64-linux-musl[x32]` + + + +How it works +------------ + +The current musl-cross-make is factored into two layers: + +1. The top-level Makefile which is responsible for downloading, + verifying, extracting, and patching sources, and for setting up a + build directory, and + +2. Litecross, the cross compiler build system, which is itself a + Makefile symlinked into the build directory. + +Most of the real magic takes place in litecross. It begins by setting +up symlinks to all the source trees provided to it by the caller, then +builds a combined `src_toolchain` directory of symlinks that combines +the contents of the top-level gcc and binutils source trees and +symlinks to gmp, mpc, and mpfr. One configured invocation them +configures all the GNU toolchain components together in a manner that +does not require any of them to be installed in order for the others +to use them. + +Rather than building the whole toolchain tree at once, though, +litecross starts by building just the gcc directory and its +prerequisites, to get an `xgcc` that can be used to configure musl. It +then configures musl, installs musl's headers to a staging "build +sysroot", and builds `libgcc.a` using those headers. At this point it +has all the prerequisites to build musl `libc.a` and `libc.so`, which the +rest of the gcc target-libs depend on; once they are built, the full +toolchain `make all` can proceed. + +Litecross does not actually depend on the musl-cross-make top-level +build system; it can be used with any pre-extracted, properly patched +set of source trees. + + +Project scope and goals +----------------------- + +The primary goals of this project are to: + +- Provide canonical musl support patches for GCC and binutils. + +- Serve as a canonical example of how GCC should be built to target + musl. + +- Streamline the production of musl-targeting cross compilers so that + musl users can easily produce musl-linked applications or bootstrap + new systems using musl. + +- Assist musl and toolchain developers in development and testing. + +While the patches applied to GCC and binutils are all intended not to +break non-musl configurations, musl-cross-make itself is specific to +musl. Changes to add support for exotic target variants outside of +what upstream musl supports are probably out-of-scope unless they are +non-invasive. Changes to fix issues building musl-cross-make to run on +non-Linux systems are well within scope as long as they are clean. + +Most importantly, this is a side project to benefit musl and its +users. It's not intended to be something high-maintenance or to divert +development effort away from musl itself. + + +Patches included +---------------- + +In addition to canonical musl support patches for GCC, +musl-cross-make's patch set provides: + +- Static-linked PIE support +- Addition of `--enable-default-pie` +- Fixes for SH-specific bugs and bitrot in GCC +- Support for J2 Core CPU target in GCC & binutils +- SH/FDPIC ABI support + +Most of these patches are integrated in gcc trunk/binutils master. +They should also be usable with Gregor's original musl-cross or other +build systems, if desired. + +Some functionality (SH/FDPIC, and support for J2 specific features) is +presently only available with gcc 5.2.0 and later, and binutils 2.25.1 +and later. + +License +------- + +The musl-cross-make build tools and documentation are licensed under +the MIT/Expat license as found in the `LICENSE` file. + +Note that this license does not cover the patches (`patches/`) or +resulting binary artifacts. + +Each patch (`patches/`) is distributed under the terms of the license +of the upstream project to which it is applied. + +Similarly, any resulting binary artifacts produced using this build +tooling retain the original licensing from the upstream projects. The +authors of musl-cross-make do not make any additional copyright claims +to these artifacts. + +### Contribution + +Unless you explicitly state otherwise, any contribution submitted for +inclusion in musl-cross-make by you shall be licensed as above without +any additional terms or conditions. diff --git a/config.mak b/config.mak new file mode 100644 index 0000000..d33f789 --- /dev/null +++ b/config.mak @@ -0,0 +1,89 @@ +# +# config.mak.dist - sample musl-cross-make configuration +# +# Copy to config.mak and edit as desired. +# + +# There is no default TARGET; you must select one here or on the make +# command line. Some examples: + +# TARGET = i486-linux-musl +# TARGET = x86_64-linux-musl +# TARGET = arm-linux-musleabi +# TARGET = arm-linux-musleabihf +# TARGET = sh2eb-linux-muslfdpic +TARGET = ${EVEREST_TARGET} +# ... + +# By default, cross compilers are installed to ./output under the top-level +# musl-cross-make directory and can later be moved wherever you want them. +# To install directly to a specific location, set it here. Multiple targets +# can safely be installed in the same location. Some examples: + +# OUTPUT = /opt/cross +# OUTPUT = /usr/local +OUTPUT = ${EVEREST}/cross-tools/${EVEREST_TARGET} + +# By default, latest supported release versions of musl and the toolchain +# components are used. You can override those here, but the version selected +# must be supported (under hashes/ and patches/) to work. For musl, you +# can use "git-refname" (e.g. git-master) instead of a release. Setting a +# blank version for gmp, mpc, mpfr and isl will suppress download and +# in-tree build of these libraries and instead depend on pre-installed +# libraries when available (isl is optional and not set by default). +# Setting a blank version for linux will suppress installation of kernel +# headers, which are not needed unless compiling programs that use them. + +# BINUTILS_VER = 2.25.1 +# GCC_VER = 5.2.0 +# MUSL_VER = git-master +# GMP_VER = +# MPC_VER = +# MPFR_VER = +# ISL_VER = +# LINUX_VER = + +# By default source archives are downloaded with wget. curl is also an option. + +# DL_CMD = wget -c -O +# DL_CMD = curl -C - -L -o + +# Check sha-1 hashes of downloaded source archives. On gnu systems this is +# usually done with sha1sum. + +# SHA1_CMD = sha1sum -c +# SHA1_CMD = sha1 -c +# SHA1_CMD = shasum -a 1 -c + +# Something like the following can be used to produce a static-linked +# toolchain that's deployable to any system with matching arch, using +# an existing musl-targeted cross compiler. This only works if the +# system you build on can natively (or via binfmt_misc and qemu) run +# binaries produced by the existing toolchain (in this example, i486). + +# COMMON_CONFIG += CC="i486-linux-musl-gcc -static --static" CXX="i486-linux-musl-g++ -static --static" + +# Recommended options for smaller build for deploying binaries: + +# COMMON_CONFIG += CFLAGS="-g0 -Os" CXXFLAGS="-g0 -Os" LDFLAGS="-s" + +# Options you can add for faster/simpler build at the expense of features: + +# COMMON_CONFIG += --disable-nls +# GCC_CONFIG += --disable-libquadmath --disable-decimal-float +# GCC_CONFIG += --disable-libitm +# GCC_CONFIG += --disable-fixed-point +# GCC_CONFIG += --disable-lto + +# By default C and C++ are the only languages enabled, and these are +# the only ones tested and known to be supported. You can uncomment the +# following and add other languages if you want to try getting them to +# work too. + +# GCC_CONFIG += --enable-languages=c,c++ + +# You can keep the local build path out of your toolchain binaries and +# target libraries with the following, but then gdb needs to be told +# where to look for source files. + +# COMMON_CONFIG += --with-debug-prefix-map=$(CURDIR)= diff --git a/cowpatch.sh b/cowpatch.sh new file mode 100755 index 0000000..c79c9d9 --- /dev/null +++ b/cowpatch.sh @@ -0,0 +1,103 @@ +#!/bin/sh +# +# cowpatch.sh, by Rich Felker +# +# Permission to use, copy, modify, and/or distribute this software for +# any purpose with or without fee is hereby granted. +# +# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL +# WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE +# AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL +# DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA +# OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER +# TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +# PERFORMANCE OF THIS SOFTWARE. +# +# Take the above disclaimer seriously! This is an experimental tool +# still and does not yet take precautions against malformed/malicious +# patch files like patch(1) does. It may act out-of-tree and clobber +# stuff you didn't intend for it to clobber. +# + +set -e + +echo () { printf "%s\n" "$*" ; } + +cow () { +test -h "$1" || return 0 +if test -d "$1" ; then +case "$1" in +*/*) set -- "${1%/*}/" "${1##*/}" ;; +*) set -- "" "$1" ;; +esac +mkdir "$1$2.tmp.$$" +mv "$1$2" "$1.$2.orig" +mv "$1$2.tmp.$$" "$1$2" +( cd "$1$2" && ln -s ../".$2.orig"/* . ) +else +cp "$1" "$1.tmp.$$" +mv "$1.tmp.$$" "$1" +fi +} + +cowp () { +while test "$1" ; do +case "$1" in +*/*) set -- "${1#*/}" "$2${2:+/}${1%%/*}" ;; +*) set -- "" "$2${2:+/}$1" ;; +esac +cow "$2" +done +} + +cowpatch () { + +plev=0 +OPTIND=1 +while getopts ":p:i:RNE" opt ; do +test "$opt" = p && plev="$OPTARG" +done + +while IFS= read -r l ; do +case "$l" in ++++*) +IFS=" " read -r junk pfile junk <dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-bfin.c b/bfd/elf32-bfin.c +index 49ef360..8346d57 100644 +--- a/bfd/elf32-bfin.c ++++ b/bfd/elf32-bfin.c +@@ -4257,7 +4257,7 @@ elf32_bfinfdpic_size_dynamic_sections (bfd *output_bfd, + if (htab->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-cr16.c b/bfd/elf32-cr16.c +index 5d8ffbc..497630e 100644 +--- a/bfd/elf32-cr16.c ++++ b/bfd/elf32-cr16.c +@@ -2464,7 +2464,7 @@ _bfd_cr16_elf_size_dynamic_sections (bfd * output_bfd, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + #if 0 + s = bfd_get_linker_section (dynobj, ".interp"); +diff --git a/bfd/elf32-cris.c b/bfd/elf32-cris.c +index 3031173..5b40524 100644 +--- a/bfd/elf32-cris.c ++++ b/bfd/elf32-cris.c +@@ -3764,7 +3764,7 @@ elf_cris_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-frv.c b/bfd/elf32-frv.c +index b55a7ab..ef72c23 100644 +--- a/bfd/elf32-frv.c ++++ b/bfd/elf32-frv.c +@@ -5444,7 +5444,7 @@ elf32_frvfdpic_size_dynamic_sections (bfd *output_bfd, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-hppa.c b/bfd/elf32-hppa.c +index 41bf5c5..62c7cf6 100644 +--- a/bfd/elf32-hppa.c ++++ b/bfd/elf32-hppa.c +@@ -2215,7 +2215,7 @@ elf32_hppa_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (htab->etab.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + sec = bfd_get_linker_section (dynobj, ".interp"); + if (sec == NULL) +diff --git a/bfd/elf32-i370.c b/bfd/elf32-i370.c +index 7fba4d1..458f694 100644 +--- a/bfd/elf32-i370.c ++++ b/bfd/elf32-i370.c +@@ -594,7 +594,7 @@ i370_elf_size_dynamic_sections (bfd *output_bfd, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-i386.c b/bfd/elf32-i386.c +index 7642d0f..b0844c8 100644 +--- a/bfd/elf32-i386.c ++++ b/bfd/elf32-i386.c +@@ -2834,7 +2834,7 @@ elf_i386_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info) + if (htab->elf.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + if (s == NULL) +diff --git a/bfd/elf32-lm32.c b/bfd/elf32-lm32.c +index 23f6e5e..0805e3c 100644 +--- a/bfd/elf32-lm32.c ++++ b/bfd/elf32-lm32.c +@@ -2141,7 +2141,7 @@ lm32_elf_size_dynamic_sections (bfd *output_bfd, + if (htab->root.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-m32r.c b/bfd/elf32-m32r.c +index 155d079..a2e3c7c 100644 +--- a/bfd/elf32-m32r.c ++++ b/bfd/elf32-m32r.c +@@ -2170,7 +2170,7 @@ m32r_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (htab->root.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-m68k.c b/bfd/elf32-m68k.c +index 10d2fcb..489f3f1 100644 +--- a/bfd/elf32-m68k.c ++++ b/bfd/elf32-m68k.c +@@ -3257,7 +3257,7 @@ elf_m68k_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-metag.c b/bfd/elf32-metag.c +index 9c54a71..755c431 100644 +--- a/bfd/elf32-metag.c ++++ b/bfd/elf32-metag.c +@@ -2848,7 +2848,7 @@ elf_metag_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (htab->etab.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + if (s == NULL) +diff --git a/bfd/elf32-nios2.c b/bfd/elf32-nios2.c +index fd70007..2a2b3a6 100644 +--- a/bfd/elf32-nios2.c ++++ b/bfd/elf32-nios2.c +@@ -5849,7 +5849,7 @@ nios2_elf32_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-or1k.c b/bfd/elf32-or1k.c +index d4f92b7..a1eba09 100644 +--- a/bfd/elf32-or1k.c ++++ b/bfd/elf32-or1k.c +@@ -2447,7 +2447,7 @@ or1k_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (htab->root.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_section_by_name (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-ppc.c b/bfd/elf32-ppc.c +index 8415f1e..5597051 100644 +--- a/bfd/elf32-ppc.c ++++ b/bfd/elf32-ppc.c +@@ -6191,7 +6191,7 @@ ppc_elf_size_dynamic_sections (bfd *output_bfd, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (htab->elf.dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-s390.c b/bfd/elf32-s390.c +index de37ca4..a1e628c 100644 +--- a/bfd/elf32-s390.c ++++ b/bfd/elf32-s390.c +@@ -2039,7 +2039,7 @@ elf_s390_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (htab->elf.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + if (s == NULL) +diff --git a/bfd/elf32-sh.c b/bfd/elf32-sh.c +index 012ee4e..a51453f 100644 +--- a/bfd/elf32-sh.c ++++ b/bfd/elf32-sh.c +@@ -3349,7 +3349,7 @@ sh_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (htab->root.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-tic6x.c b/bfd/elf32-tic6x.c +index b6640ea..380ab8d 100644 +--- a/bfd/elf32-tic6x.c ++++ b/bfd/elf32-tic6x.c +@@ -3300,7 +3300,7 @@ elf32_tic6x_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info) + if (htab->elf.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + if (s == NULL) +diff --git a/bfd/elf32-tilepro.c b/bfd/elf32-tilepro.c +index cb3f896..d55be2d 100644 +--- a/bfd/elf32-tilepro.c ++++ b/bfd/elf32-tilepro.c +@@ -2463,7 +2463,7 @@ tilepro_elf_size_dynamic_sections (bfd *output_bfd, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-vax.c b/bfd/elf32-vax.c +index 6089e8c..893ea8d 100644 +--- a/bfd/elf32-vax.c ++++ b/bfd/elf32-vax.c +@@ -1124,7 +1124,7 @@ elf_vax_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info) + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-xtensa.c b/bfd/elf32-xtensa.c +index 73538cd..37ea5da 100644 +--- a/bfd/elf32-xtensa.c ++++ b/bfd/elf32-xtensa.c +@@ -1637,7 +1637,7 @@ elf_xtensa_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + && htab->sgotloc != NULL); + + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + if (s == NULL) +diff --git a/bfd/elf64-alpha.c b/bfd/elf64-alpha.c +index f67b0af..1973cd0 100644 +--- a/bfd/elf64-alpha.c ++++ b/bfd/elf64-alpha.c +@@ -2877,7 +2877,7 @@ elf64_alpha_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf64-hppa.c b/bfd/elf64-hppa.c +index 6f40b88..3b628b4 100644 +--- a/bfd/elf64-hppa.c ++++ b/bfd/elf64-hppa.c +@@ -1558,7 +1558,7 @@ elf64_hppa_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info) + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + sec = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (sec != NULL); +diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c +index 8cff990..851845f 100644 +--- a/bfd/elf64-ppc.c ++++ b/bfd/elf64-ppc.c +@@ -9748,7 +9748,7 @@ ppc64_elf_size_dynamic_sections (bfd *output_bfd, + if (htab->elf.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + if (s == NULL) +diff --git a/bfd/elf64-s390.c b/bfd/elf64-s390.c +index 2e505f3..406bb66 100644 +--- a/bfd/elf64-s390.c ++++ b/bfd/elf64-s390.c +@@ -1989,7 +1989,7 @@ elf_s390_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (htab->elf.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + if (s == NULL) +diff --git a/bfd/elf64-sh64.c b/bfd/elf64-sh64.c +index e460895..d920598 100644 +--- a/bfd/elf64-sh64.c ++++ b/bfd/elf64-sh64.c +@@ -3404,7 +3404,7 @@ sh64_elf64_size_dynamic_sections (bfd *output_bfd, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf64-x86-64.c b/bfd/elf64-x86-64.c +index f15d33e..870aadf 100644 +--- a/bfd/elf64-x86-64.c ++++ b/bfd/elf64-x86-64.c +@@ -3181,7 +3181,7 @@ elf_x86_64_size_dynamic_sections (bfd *output_bfd, + if (htab->elf.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + if (s == NULL) +diff --git a/bfd/elflink.c b/bfd/elflink.c +index 7f04271..5b3438d 100644 +--- a/bfd/elflink.c ++++ b/bfd/elflink.c +@@ -246,7 +246,7 @@ _bfd_elf_link_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info) + + /* A dynamically linked executable has a .interp section, but a + shared library does not. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_make_section_anyway_with_flags (abfd, ".interp", + flags | SEC_READONLY); +@@ -5763,7 +5763,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd, + bfd_boolean all_defined; + + *sinterpptr = bfd_get_linker_section (dynobj, ".interp"); +- BFD_ASSERT (*sinterpptr != NULL || !info->executable); ++ BFD_ASSERT (*sinterpptr != NULL || !info->executable || info->nointerp); + + if (soname != NULL) + { +diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c +index beedb70..599f9cf 100644 +--- a/bfd/elfnn-aarch64.c ++++ b/bfd/elfnn-aarch64.c +@@ -7674,7 +7674,7 @@ elfNN_aarch64_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + + if (htab->root.dynamic_sections_created) + { +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + if (s == NULL) +diff --git a/bfd/elfnn-ia64.c b/bfd/elfnn-ia64.c +index c45fa28..3b304d5 100644 +--- a/bfd/elfnn-ia64.c ++++ b/bfd/elfnn-ia64.c +@@ -2992,7 +2992,7 @@ elfNN_ia64_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + + /* Set the contents of the .interp section to the interpreter. */ + if (ia64_info->root.dynamic_sections_created +- && info->executable) ++ && info->executable && !info->nointerp) + { + sec = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (sec != NULL); +diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c +index be1e59a..329dec3 100644 +--- a/bfd/elfxx-mips.c ++++ b/bfd/elfxx-mips.c +@@ -9579,7 +9579,7 @@ _bfd_mips_elf_size_dynamic_sections (bfd *output_bfd, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elfxx-sparc.c b/bfd/elfxx-sparc.c +index 9bb71a9..db0d4f1 100644 +--- a/bfd/elfxx-sparc.c ++++ b/bfd/elfxx-sparc.c +@@ -2559,7 +2559,7 @@ _bfd_sparc_elf_size_dynamic_sections (bfd *output_bfd, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elfxx-tilegx.c b/bfd/elfxx-tilegx.c +index 59a2f7e..6f7485a 100644 +--- a/bfd/elfxx-tilegx.c ++++ b/bfd/elfxx-tilegx.c +@@ -2724,7 +2724,7 @@ tilegx_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/include/bfdlink.h b/include/bfdlink.h +index 797a465..cf533dd 100644 +--- a/include/bfdlink.h ++++ b/include/bfdlink.h +@@ -433,6 +433,9 @@ struct bfd_link_info + /* TRUE if BND prefix in PLT entries is always generated. */ + unsigned int bndplt: 1; + ++ /* TRUE if generation of .interp/PT_INTERP should be suppressed. */ ++ unsigned int nointerp: 1; ++ + /* Char that may appear as the first char of a symbol, but should be + skipped (like symbol_leading_char) when looking up symbols in + wrap_hash. Used by PowerPC Linux for 'dot' symbols. */ +diff --git a/ld/ld.texinfo b/ld/ld.texinfo +index cf3b586..1e5e5cf 100644 +--- a/ld/ld.texinfo ++++ b/ld/ld.texinfo +@@ -1426,6 +1426,13 @@ generating dynamically linked ELF executables. The default dynamic + linker is normally correct; don't use this unless you know what you are + doing. + ++@kindex --no-dynamic-linker ++@item --no-dynamic-linker ++When producing an executable file, omit the request for a dynamic ++linker to be used at load-time. This is only meaningful for ELF ++executables that contain dynamic relocations, and usually requires ++entry point code that is capable of processing these relocations. ++ + @kindex --fatal-warnings + @kindex --no-fatal-warnings + @item --fatal-warnings +diff --git a/ld/ldlex.h b/ld/ldlex.h +index 59bd14f..8b57f84 100644 +--- a/ld/ldlex.h ++++ b/ld/ldlex.h +@@ -33,6 +33,7 @@ enum option_values + OPTION_DEFSYM, + OPTION_DEMANGLE, + OPTION_DYNAMIC_LINKER, ++ OPTION_NO_DYNAMIC_LINKER, + OPTION_SYSROOT, + OPTION_EB, + OPTION_EL, +diff --git a/ld/lexsup.c b/ld/lexsup.c +index 777d6e2..1b992f7 100644 +--- a/ld/lexsup.c ++++ b/ld/lexsup.c +@@ -138,6 +138,9 @@ static const struct ld_option ld_options[] = + { {"dynamic-linker", required_argument, NULL, OPTION_DYNAMIC_LINKER}, + 'I', N_("PROGRAM"), N_("Set PROGRAM as the dynamic linker to use"), + TWO_DASHES }, ++ { {"no-dynamic-linker", no_argument, NULL, OPTION_NO_DYNAMIC_LINKER}, ++ '\0', NULL, N_("Produce an executable with no program interpreter header"), ++ TWO_DASHES }, + { {"library", required_argument, NULL, 'l'}, + 'l', N_("LIBNAME"), N_("Search for library LIBNAME"), TWO_DASHES }, + { {"library-path", required_argument, NULL, 'L'}, +@@ -762,6 +765,10 @@ parse_args (unsigned argc, char **argv) + case 'I': /* Used on Solaris. */ + case OPTION_DYNAMIC_LINKER: + command_line.interpreter = optarg; ++ link_info.nointerp = 0; ++ break; ++ case OPTION_NO_DYNAMIC_LINKER: ++ link_info.nointerp = 1; + break; + case OPTION_SYSROOT: + /* Already handled in ldmain.c. */ diff --git a/patches/binutils-2.25.1/0002-cas.diff b/patches/binutils-2.25.1/0002-cas.diff new file mode 100644 index 0000000..3db1743 --- /dev/null +++ b/patches/binutils-2.25.1/0002-cas.diff @@ -0,0 +1,640 @@ +diff --git a/bfd/archures.c b/bfd/archures.c +index 51068b9..c67d76b 100644 +--- a/bfd/archures.c ++++ b/bfd/archures.c +@@ -294,10 +294,12 @@ DESCRIPTION + .#define bfd_mach_sh_dsp 0x2d + .#define bfd_mach_sh2a 0x2a + .#define bfd_mach_sh2a_nofpu 0x2b ++.#define bfd_mach_shj2 0x2c + .#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1 + .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + .#define bfd_mach_sh2a_or_sh4 0x2a3 + .#define bfd_mach_sh2a_or_sh3e 0x2a4 ++.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 + .#define bfd_mach_sh2e 0x2e + .#define bfd_mach_sh3 0x30 + .#define bfd_mach_sh3_nommu 0x31 +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index ca0cafd..99e92c6 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -2109,10 +2109,12 @@ enum bfd_architecture + #define bfd_mach_sh_dsp 0x2d + #define bfd_mach_sh2a 0x2a + #define bfd_mach_sh2a_nofpu 0x2b ++#define bfd_mach_shj2 0x2c + #define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1 + #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + #define bfd_mach_sh2a_or_sh4 0x2a3 + #define bfd_mach_sh2a_or_sh3e 0x2a4 ++#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 + #define bfd_mach_sh2e 0x2e + #define bfd_mach_sh3 0x30 + #define bfd_mach_sh3_nommu 0x31 +diff --git a/bfd/cpu-sh.c b/bfd/cpu-sh.c +index d516d66..66d21a5 100644 +--- a/bfd/cpu-sh.c ++++ b/bfd/cpu-sh.c +@@ -44,7 +44,9 @@ + #define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17 + #define SH2A_OR_SH4_NEXT arch_info_struct + 18 + #define SH2A_OR_SH3E_NEXT arch_info_struct + 19 +-#define SH64_NEXT NULL ++#define SH64_NEXT arch_info_struct + 20 ++#define SHJ2_NEXT arch_info_struct + 21 ++#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT NULL + + static const bfd_arch_info_type arch_info_struct[] = + { +@@ -348,6 +350,36 @@ static const bfd_arch_info_type arch_info_struct[] = + bfd_arch_default_fill, + SH64_NEXT + }, ++ { ++ 32, /* 32 bits in a word. */ ++ 32, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_sh, ++ bfd_mach_shj2, ++ "sh", /* Architecture name. . */ ++ "j2", /* Machine name. */ ++ 1, ++ FALSE, /* Not the default. */ ++ bfd_default_compatible, ++ bfd_default_scan, ++ bfd_arch_default_fill, ++ SHJ2_NEXT ++ }, ++ { ++ 32, /* 32 bits in a word. */ ++ 32, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_sh, ++ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, ++ "sh", /* Architecture name. . */ ++ "sh2a-or-sh3e-or-j2", /* Machine name. */ ++ 1, ++ FALSE, /* Not the default. */ ++ bfd_default_compatible, ++ bfd_default_scan, ++ bfd_arch_default_fill, ++ SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT ++ }, + }; + + const bfd_arch_info_type bfd_sh_arch = +@@ -398,6 +430,8 @@ static struct { unsigned long bfd_mach, arch, arch_up; } bfd_to_arch_table[] = + { bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up }, + { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up }, + { bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up }, ++ { bfd_mach_shj2, arch_shj2, arch_shj2_up }, ++ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up }, + { 0, 0, 0 } /* Terminator. */ + }; + +diff --git a/binutils/readelf.c b/binutils/readelf.c +index a31db52..5ec21b0 100644 +--- a/binutils/readelf.c ++++ b/binutils/readelf.c +@@ -3217,6 +3217,8 @@ get_machine_flags (unsigned e_flags, unsigned e_machine) + case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break; + case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break; + case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break; ++ case EF_SHJ2: strcat (buf, ", j2"); break; ++ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break; + default: strcat (buf, _(", unknown ISA")); break; + } + +diff --git a/gas/config/tc-sh.c b/gas/config/tc-sh.c +index 125f073..37f6fb0 100644 +--- a/gas/config/tc-sh.c ++++ b/gas/config/tc-sh.c +@@ -1648,6 +1648,8 @@ get_operands (sh_opcode_info *info, char *args, sh_operand_info *operand) + ptr++; + } + get_operand (&ptr, operand + 2); ++ if (strcmp (info->name,"cas") == 0) ++ operand[2].type = A_IND_0; + } + else + { +@@ -2187,7 +2189,10 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands) + goto fail; + reg_m = 4; + break; +- ++ case A_IND_0: ++ if (user->reg != 0) ++ goto fail; ++ break; + default: + printf (_("unhandled %d\n"), arg); + goto fail; +diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s +index cc29889..a3e18b5 100644 +--- a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s ++++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s +@@ -12,7 +12,5 @@ + sh2a_nofpu_or_sh3_nommu: + ! Instructions introduced into sh2a-nofpu-or-sh3-nommu +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + + ! Instructions inherited from ancestors: sh sh2 + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} +diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s +index c702845..812aa76 100644 +--- a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s ++++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s +@@ -12,7 +12,7 @@ + sh2a_nofpu_or_sh4_nommu_nofpu: + ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -119,8 +119,8 @@ sh2a_nofpu_or_sh4_nommu_nofpu: + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu.s +index 6f4a17e..5b38643 100644 +--- a/gas/testsuite/gas/sh/arch/sh2a-nofpu.s ++++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu.s +@@ -64,7 +64,7 @@ sh2a_nofpu: + movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(,), */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} + movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(,), */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -171,8 +171,8 @@ sh2a_nofpu: + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff --git a/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s b/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s +index 25c8ae1..69d3536 100644 +--- a/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s ++++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s +@@ -13,7 +13,7 @@ sh2a_or_sh3e: + ! Instructions introduced into sh2a-or-sh3e + fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -124,8 +124,8 @@ sh2a_or_sh3e: + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff --git a/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s b/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s +index d3300ca..c697268 100644 +--- a/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s ++++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s +@@ -39,7 +39,7 @@ sh2a_or_sh4: + fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub ,*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} + ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc ,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -150,8 +150,8 @@ sh2a_or_sh4: + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff --git a/gas/testsuite/gas/sh/arch/sh2a.s b/gas/testsuite/gas/sh/arch/sh2a.s +index 370dbd4..0d9f3b0 100644 +--- a/gas/testsuite/gas/sh/arch/sh2a.s ++++ b/gas/testsuite/gas/sh/arch/sh2a.s +@@ -16,7 +16,7 @@ sh2a: + fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s ,@(,) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32} + fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(,), */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -140,8 +140,8 @@ sh2a: + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff --git a/gas/testsuite/gas/sh/arch/sh3-dsp.s b/gas/testsuite/gas/sh/arch/sh3-dsp.s +index acc26be..cfd4dfe 100644 +--- a/gas/testsuite/gas/sh/arch/sh3-dsp.s ++++ b/gas/testsuite/gas/sh/arch/sh3-dsp.s +@@ -12,7 +12,7 @@ + sh3_dsp: + ! Instructions introduced into sh3-dsp + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -152,8 +152,8 @@ sh3_dsp: + setrc #4 ;!/* 10000010i8*1.... setrc # */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff --git a/gas/testsuite/gas/sh/arch/sh3-nommu.s b/gas/testsuite/gas/sh/arch/sh3-nommu.s +index 3e8ff02..dacaae1 100644 +--- a/gas/testsuite/gas/sh/arch/sh3-nommu.s ++++ b/gas/testsuite/gas/sh/arch/sh3-nommu.s +@@ -26,7 +26,7 @@ sh3_nommu: + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@- */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@- */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -133,8 +133,8 @@ sh3_nommu: + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff --git a/gas/testsuite/gas/sh/arch/sh3.s b/gas/testsuite/gas/sh/arch/sh3.s +index 97ab939..aa70fc3 100644 +--- a/gas/testsuite/gas/sh/arch/sh3.s ++++ b/gas/testsuite/gas/sh/arch/sh3.s +@@ -13,7 +13,7 @@ sh3: + ! Instructions introduced into sh3 + ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -128,8 +128,8 @@ sh3: + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff --git a/gas/testsuite/gas/sh/arch/sh3e.s b/gas/testsuite/gas/sh/arch/sh3e.s +index f5c8ab9..215e5ec 100644 +--- a/gas/testsuite/gas/sh/arch/sh3e.s ++++ b/gas/testsuite/gas/sh/arch/sh3e.s +@@ -12,7 +12,7 @@ + sh3e: + ! Instructions introduced into sh3e + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -132,8 +132,8 @@ sh3e: + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff --git a/gas/testsuite/gas/sh/arch/sh4-nofpu.s b/gas/testsuite/gas/sh/arch/sh4-nofpu.s +index 32b58f9..1fef035 100644 +--- a/gas/testsuite/gas/sh/arch/sh4-nofpu.s ++++ b/gas/testsuite/gas/sh/arch/sh4-nofpu.s +@@ -12,7 +12,7 @@ + sh4_nofpu: + ! Instructions introduced into sh4-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -136,8 +136,8 @@ sh4_nofpu: + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff --git a/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s b/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s +index 61f0bc6..65d11c5 100644 +--- a/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s ++++ b/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s +@@ -24,7 +24,7 @@ sh4_nommu_nofpu: + stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@- */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@- */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -139,8 +139,8 @@ sh4_nommu_nofpu: + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff --git a/gas/testsuite/gas/sh/arch/sh4.s b/gas/testsuite/gas/sh/arch/sh4.s +index af135ce..dc199cb 100644 +--- a/gas/testsuite/gas/sh/arch/sh4.s ++++ b/gas/testsuite/gas/sh/arch/sh4.s +@@ -17,7 +17,7 @@ sh4: + fsrra fr1 ;!/* 1111nnnn01111101 fsrra */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up} + ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -145,8 +145,8 @@ sh4: + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff --git a/gas/testsuite/gas/sh/arch/sh4a-nofpu.s b/gas/testsuite/gas/sh/arch/sh4a-nofpu.s +index 9522bb6..7581f47 100644 +--- a/gas/testsuite/gas/sh/arch/sh4a-nofpu.s ++++ b/gas/testsuite/gas/sh/arch/sh4a-nofpu.s +@@ -19,7 +19,7 @@ sh4a_nofpu: + prefi @r4 ;!/* 0000nnnn11010011 prefi @ */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} + synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -143,8 +143,8 @@ sh4a_nofpu: + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff --git a/gas/testsuite/gas/sh/arch/sh4a.s b/gas/testsuite/gas/sh/arch/sh4a.s +index 950ed2d..55e9611 100644 +--- a/gas/testsuite/gas/sh/arch/sh4a.s ++++ b/gas/testsuite/gas/sh/arch/sh4a.s +@@ -13,7 +13,7 @@ sh4a: + ! Instructions introduced into sh4a + fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -147,8 +147,8 @@ sh4a: + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff --git a/gas/testsuite/gas/sh/arch/sh4al-dsp.s b/gas/testsuite/gas/sh/arch/sh4al-dsp.s +index 6caaf2c..fde6c1e 100644 +--- a/gas/testsuite/gas/sh/arch/sh4al-dsp.s ++++ b/gas/testsuite/gas/sh/arch/sh4al-dsp.s +@@ -48,7 +48,7 @@ sh4al_dsp: + dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap , */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up} + dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap , */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up} + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -202,8 +202,8 @@ sh4al_dsp: + setrc #4 ;!/* 10000010i8*1.... setrc # */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff --git a/include/elf/sh.h b/include/elf/sh.h +index a54158f..109d90f 100644 +--- a/include/elf/sh.h ++++ b/include/elf/sh.h +@@ -35,6 +35,7 @@ + #define EF_SH2E 11 + #define EF_SH4A 12 + #define EF_SH2A 13 ++#define EF_SHJ2 14 + + #define EF_SH4_NOFPU 16 + #define EF_SH4A_NOFPU 17 +@@ -46,6 +47,7 @@ + #define EF_SH2A_SH3_NOFPU 22 + #define EF_SH2A_SH4 23 + #define EF_SH2A_SH3E 24 ++#define EF_SH2A_SH3_SHJ2 25 + + /* This one can only mix in objects from other EF_SH5 objects. */ + #define EF_SH5 10 +@@ -68,7 +70,8 @@ + /* EF_SH2E */ bfd_mach_sh2e , \ + /* EF_SH4A */ bfd_mach_sh4a , \ + /* EF_SH2A */ bfd_mach_sh2a , \ +-/* 14, 15 */ 0, 0, \ ++/* EF_SHJ2 */ bfd_mach_shj2 , \ ++/* 15 */ 0, \ + /* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \ + /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ + /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ +@@ -77,7 +80,8 @@ + /* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \ + /* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \ + /* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \ +-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e ++/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \ ++/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu + + /* Convert arch_sh* into EF_SH*. */ + int sh_find_elf_flags (unsigned int arch_set); +diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c +index d4e1a6d..181e21a 100644 +--- a/opcodes/sh-dis.c ++++ b/opcodes/sh-dis.c +@@ -868,6 +868,9 @@ print_insn_sh (bfd_vma memaddr, struct disassemble_info *info) + case XMTRX_M4: + fprintf_fn (stream, "xmtrx"); + break; ++ case A_IND_0: ++ fprintf_fn (stream, "@r0"); ++ break; + default: + abort (); + } +diff --git a/opcodes/sh-opc.h b/opcodes/sh-opc.h +index 5863aa9..19c5a61 100644 +--- a/opcodes/sh-opc.h ++++ b/opcodes/sh-opc.h +@@ -187,7 +187,8 @@ typedef enum + FPUL_N, + FPUL_M, + FPSCR_N, +- FPSCR_M ++ FPSCR_M, ++ A_IND_0 + } + sh_arg_type; + +@@ -214,9 +215,11 @@ sh_dsp_reg_nums; + #define arch_sh4_base (1 << 5) + #define arch_sh4a_base (1 << 6) + #define arch_sh2a_base (1 << 7) +-#define arch_sh_base_mask MASK (0, 7) ++#define arch_shj2_base (1 << 8) ++#define arch_sh2a_sh3_shj2_base (1 << 9) ++#define arch_sh_base_mask MASK (0, 9) + +-/* Bits 8 ... 24 are currently free. */ ++/* Bits 10 ... 24 are currently free. */ + + /* This is an annotation on instruction types, but we + abuse the arch field in instructions to denote it. */ +@@ -254,6 +257,8 @@ sh_dsp_reg_nums; + #define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co) + #define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu) + #define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu) ++#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co) + + #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) + #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) +@@ -319,7 +324,8 @@ SH4AL-dsp SH4A + #define arch_sh2_up (arch_sh2 \ + | arch_sh2e_up \ + | arch_sh2a_nofpu_or_sh3_nommu_up \ +- | arch_sh_dsp_up) ++ | arch_sh_dsp_up \ ++ | arch_shj2_up) + #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \ + | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ + | arch_sh2a_or_sh3e_up \ +@@ -345,6 +351,12 @@ SH4AL-dsp SH4A + #define arch_sh4a_nofpu_up (arch_sh4a_nofpu \ + | arch_sh4a_up \ + | arch_sh4al_dsp_up) ++#define arch_shj2_up ( arch_shj2) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \ ++ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ ++ | arch_sh2a_or_sh3e_up \ ++ | arch_sh3_nommu_up \ ++ | arch_shj2_up) + + /* Right branches. */ + #define arch_sh2e_up (arch_sh2e \ +@@ -713,9 +725,9 @@ const sh_opcode_info sh_table[] = + + /* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, + +-/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + +-/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + + /* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}, + +@@ -1193,7 +1205,7 @@ const sh_opcode_info sh_table[] = + {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}, + /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(,), */ + {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}, +- ++ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up}, + { 0, {0}, {0}, 0 } + }; + diff --git a/patches/binutils-2.25.1/0003-shemuls.diff b/patches/binutils-2.25.1/0003-shemuls.diff new file mode 100644 index 0000000..8705af5 --- /dev/null +++ b/patches/binutils-2.25.1/0003-shemuls.diff @@ -0,0 +1,48 @@ +diff -ur ../baseline/binutils-2.25.1/bfd/config.bfd binutils-2.25.1/bfd/config.bfd +--- ../baseline/binutils-2.25.1/bfd/config.bfd 2014-10-14 07:32:02.000000000 +0000 ++++ binutils-2.25.1/bfd/config.bfd 2015-09-04 19:24:08.678337083 +0000 +@@ -1370,6 +1370,7 @@ + sh-*-linux*) + targ_defvec=sh_elf32_linux_be_vec + targ_selvecs="sh_elf32_linux_vec sh64_elf32_linux_vec sh64_elf32_linux_be_vec sh64_elf64_linux_vec sh64_elf64_linux_be_vec" ++ targ_selvecs="${targ_selvecs} sh_elf32_vec sh_elf32_le_vec sh_elf32_fdpic_le_vec sh_elf32_fdpic_be_vec" + want64=true + ;; + #endif /* BFD64 */ +@@ -1377,10 +1378,12 @@ + sh*eb-*-linux*) + targ_defvec=sh_elf32_linux_be_vec + targ_selvecs=sh_elf32_linux_vec ++ targ_selvecs="${targ_selvecs} sh_elf32_vec sh_elf32_le_vec sh_elf32_fdpic_le_vec sh_elf32_fdpic_be_vec" + ;; + sh*-*-linux*) + targ_defvec=sh_elf32_linux_vec + targ_selvecs=sh_elf32_linux_be_vec ++ targ_selvecs="${targ_selvecs} sh_elf32_vec sh_elf32_le_vec sh_elf32_fdpic_le_vec sh_elf32_fdpic_be_vec" + ;; + + sh-*-uclinux* | sh[12]-*-uclinux*) +diff -ur ../baseline/binutils-2.25.1/ld/configure.tgt binutils-2.25.1/ld/configure.tgt +--- ../baseline/binutils-2.25.1/ld/configure.tgt 2014-10-14 07:32:04.000000000 +0000 ++++ binutils-2.25.1/ld/configure.tgt 2015-09-04 19:22:05.151677949 +0000 +@@ -623,15 +623,17 @@ + score-*-elf) targ_emul=score7_elf + targ_extra_emuls=score3_elf ;; + sh-*-linux*) targ_emul=shlelf_linux +- targ_extra_emuls=shelf_linux ++ targ_extra_emuls="shelf_linux shlelf_fd shelf_fd shlelf shelf" + targ_extra_libpath=shelf_linux ;; + sh64eb-*-linux*) targ_emul=shelf32_linux + targ_extra_emuls="shlelf32_linux" ;; + sh64-*-linux*) targ_emul=shlelf32_linux + targ_extra_emuls="shelf32_linux" + targ_extra_libpath=shelf32_linux ;; +-sh*eb-*-linux*) targ_emul=shelf_linux ;; +-sh*-*-linux*) targ_emul=shlelf_linux ;; ++sh*eb-*-linux*) targ_emul=shelf_linux ++ targ_extra_emuls="shelf_fd shelf" ;; ++sh*-*-linux*) targ_emul=shlelf_linux ++ targ_extra_emuls="shlelf_fd shlelf" ;; + sh5le-*-netbsd*) targ_emul=shlelf32_nbsd + targ_extra_emuls="shelf32_nbsd shelf64_nbsd shlelf64_nbsd shelf_nbsd shlelf_nbsd" ;; + sh5-*-netbsd*) targ_emul=shelf32_nbsd diff --git a/patches/binutils-2.25.1/0004-shfdpicflag.diff b/patches/binutils-2.25.1/0004-shfdpicflag.diff new file mode 100644 index 0000000..4416d25 --- /dev/null +++ b/patches/binutils-2.25.1/0004-shfdpicflag.diff @@ -0,0 +1,21 @@ +diff -ur binutils-2.25.1.orig/bfd/elf32-sh.c binutils-2.25.1/bfd/elf32-sh.c +--- binutils-2.25.1.orig/bfd/elf32-sh.c 2015-09-03 21:52:17.000000000 +0000 ++++ binutils-2.25.1/bfd/elf32-sh.c 2015-09-14 17:08:48.114426847 +0000 +@@ -5487,7 +5487,7 @@ + input_bfd, input_section, rel->r_offset, symname); + } + +- elf_elfheader (output_bfd)->e_flags &= ~EF_SH_PIC; ++ elf_elfheader (output_bfd)->e_flags |= EF_SH_PIC; + } + + if (r != bfd_reloc_ok) +@@ -6644,7 +6644,7 @@ + elf_elfheader (obfd)->e_flags = elf_elfheader (ibfd)->e_flags; + sh_elf_set_mach_from_flags (obfd); + if (elf_elfheader (obfd)->e_flags & EF_SH_FDPIC) +- elf_elfheader (obfd)->e_flags |= EF_SH_PIC; ++ elf_elfheader (obfd)->e_flags &= ~EF_SH_PIC; + } + + if (! sh_merge_bfd_arch (ibfd, obfd)) diff --git a/patches/binutils-2.25.1/0005-shfdpicgot.diff b/patches/binutils-2.25.1/0005-shfdpicgot.diff new file mode 100644 index 0000000..7bc6565 --- /dev/null +++ b/patches/binutils-2.25.1/0005-shfdpicgot.diff @@ -0,0 +1,11 @@ +--- binutils-2.25.1/bfd/elf32-sh.c.orig 2015-10-08 16:33:04.413334344 +0000 ++++ binutils-2.25.1/bfd/elf32-sh.c 2015-10-08 16:23:05.709980166 +0000 +@@ -3604,7 +3604,7 @@ sh_elf_size_dynamic_sections (bfd *outpu + return FALSE; + } + else if ((elf_elfheader (output_bfd)->e_flags & EF_SH_FDPIC) +- && htab->sgot->size != 0) ++ /* && htab->sgot->size != 0 */) + { + if (! add_dynamic_entry (DT_PLTGOT, 0)) + return FALSE; diff --git a/patches/binutils-2.25.1/0006-mbbadsymindx.diff b/patches/binutils-2.25.1/0006-mbbadsymindx.diff new file mode 100644 index 0000000..1195b9e --- /dev/null +++ b/patches/binutils-2.25.1/0006-mbbadsymindx.diff @@ -0,0 +1,12 @@ +--- binutils-2.25.1/bfd/elf32-microblaze.c.orig 2016-02-11 23:12:00.301992882 +0000 ++++ binutils-2.25.1/bfd/elf32-microblaze.c 2016-02-11 23:28:12.043074209 +0000 +@@ -3293,8 +3293,7 @@ + The entry in the global offset table will already have been + initialized in the relocate_section function. */ + if (info->shared +- && (info->symbolic || h->dynindx == -1) +- && h->def_regular) ++ && ((info->symbolic && h->def_regular) || h->dynindx == -1)) + { + asection *sec = h->root.u.def.section; + microblaze_elf_output_dynamic_relocation (output_bfd, diff --git a/patches/binutils-2.25.1/0007-tcarm.diff b/patches/binutils-2.25.1/0007-tcarm.diff new file mode 100644 index 0000000..e1af9c9 --- /dev/null +++ b/patches/binutils-2.25.1/0007-tcarm.diff @@ -0,0 +1,21 @@ +From d840c081f8082e8b9e63fead5306643975a97bb3 Mon Sep 17 00:00:00 2001 +From: Richard Earnshaw +Date: Thu, 20 Nov 2014 17:02:47 +0000 +Subject: [PATCH] * config/tc-arm.c (rotate_left): Avoid undefined behaviour + when N = 0. + +--- + +diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c +index 5077f87..9100fb2 100644 +--- a/gas/config/tc-arm.c ++++ b/gas/config/tc-arm.c +@@ -7251,7 +7251,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb) + + /* Functions for operand encoding. ARM, then Thumb. */ + +-#define rotate_left(v, n) (v << n | v >> (32 - n)) ++#define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31)) + + /* If VAL can be encoded in the immediate field of an ARM instruction, + return the encoded form. Otherwise, return FAIL. */ diff --git a/patches/binutils-2.25.1/0008-mips-pie-tls.diff b/patches/binutils-2.25.1/0008-mips-pie-tls.diff new file mode 100644 index 0000000..f1df3a4 --- /dev/null +++ b/patches/binutils-2.25.1/0008-mips-pie-tls.diff @@ -0,0 +1,21 @@ +diff -ur binutils-2.25.1.orig/bfd/elfxx-mips.c binutils-2.25.1/bfd/elfxx-mips.c +--- binutils-2.25.1.orig/bfd/elfxx-mips.c 2018-01-31 11:26:12.000000000 -0500 ++++ binutils-2.25.1/bfd/elfxx-mips.c 2018-01-31 12:16:00.179841734 -0500 +@@ -3228,7 +3228,7 @@ + && (!info->shared || !SYMBOL_REFERENCES_LOCAL (info, h))) + indx = h->dynindx; + +- if ((info->shared || indx != 0) ++ if ((!info->executable || indx != 0) + && (h == NULL + || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + || h->root.type != bfd_link_hash_undefweak)) +@@ -3338,7 +3338,7 @@ + if (entry->tls_initialized) + return; + +- if ((info->shared || indx != 0) ++ if ((!info->executable || indx != 0) + && (h == NULL + || ELF_ST_VISIBILITY (h->root.other) == STV_DEFAULT + || h->root.type != bfd_link_hash_undefweak)) diff --git a/patches/binutils-2.25.1/0009-arm-pie-tls.diff b/patches/binutils-2.25.1/0009-arm-pie-tls.diff new file mode 100644 index 0000000..9ef8449 --- /dev/null +++ b/patches/binutils-2.25.1/0009-arm-pie-tls.diff @@ -0,0 +1,47 @@ +--- binutils-2.25.1/bfd/elf32-arm.c.orig 2019-10-06 20:40:39.213623570 -0400 ++++ binutils-2.25.1/bfd/elf32-arm.c 2019-10-06 20:45:09.688207243 -0400 +@@ -4097,7 +4097,7 @@ + { + int is_local = (h == NULL); + +- if (info->shared || (h && h->root.type == bfd_link_hash_undefweak)) ++ if (!info->executable || (h && h->root.type == bfd_link_hash_undefweak)) + return r_type; + + /* We do not support relaxations for Old TLS models. */ +@@ -9493,7 +9493,7 @@ + { + /* If we don't know the module number, create a relocation + for it. */ +- if (info->shared) ++ if (!info->executable) + { + Elf_Internal_Rela outrel; + +@@ -9581,7 +9581,7 @@ + now, and emit any relocations. If both an IE GOT and a + GD GOT are necessary, we emit the GD first. */ + +- if ((info->shared || indx != 0) ++ if ((!info->executable || indx != 0) + && (h == NULL + || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + || h->root.type != bfd_link_hash_undefweak)) +@@ -9597,7 +9597,7 @@ + /* We should have relaxed, unless this is an undefined + weak symbol. */ + BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak)) +- || info->shared); ++ || !info->executable); + BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8 + <= globals->root.sgotplt->size); + +@@ -13504,7 +13504,7 @@ + indx = h->dynindx; + + if (tls_type != GOT_NORMAL +- && (info->shared || indx != 0) ++ && (!info->executable || indx != 0) + && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + || h->root.type != bfd_link_hash_undefweak)) + { diff --git a/patches/binutils-2.25.1/0010-arm-tlsdesc-64bithost.diff b/patches/binutils-2.25.1/0010-arm-tlsdesc-64bithost.diff new file mode 100644 index 0000000..a95cbc0 --- /dev/null +++ b/patches/binutils-2.25.1/0010-arm-tlsdesc-64bithost.diff @@ -0,0 +1,16 @@ +diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c +index bb53e039e3..d52c046979 100644 +--- a/bfd/elf32-arm.c ++++ b/bfd/elf32-arm.c +@@ -12027,9 +12027,9 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, + unsigned long data, insn; + unsigned thumb; + +- data = bfd_get_32 (input_bfd, hit_data); ++ data = bfd_get_signed_32 (input_bfd, hit_data); + thumb = data & 1; +- data &= ~1u; ++ data &= ~1ul; + + if (thumb) + { diff --git a/patches/binutils-2.27/0001-j2.diff b/patches/binutils-2.27/0001-j2.diff new file mode 100644 index 0000000..6fc2caf --- /dev/null +++ b/patches/binutils-2.27/0001-j2.diff @@ -0,0 +1,617 @@ +diff -ur binutils-2.27.orig/bfd/archures.c binutils-2.27/bfd/archures.c +--- binutils-2.27.orig/bfd/archures.c 2016-08-03 03:36:50.000000000 -0400 ++++ binutils-2.27/bfd/archures.c 2016-11-06 22:13:54.556453406 -0500 +@@ -310,10 +310,12 @@ + .#define bfd_mach_sh_dsp 0x2d + .#define bfd_mach_sh2a 0x2a + .#define bfd_mach_sh2a_nofpu 0x2b ++.#define bfd_mach_shj2 0x2c + .#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1 + .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + .#define bfd_mach_sh2a_or_sh4 0x2a3 + .#define bfd_mach_sh2a_or_sh3e 0x2a4 ++.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 + .#define bfd_mach_sh2e 0x2e + .#define bfd_mach_sh3 0x30 + .#define bfd_mach_sh3_nommu 0x31 +diff -ur binutils-2.27.orig/bfd/bfd-in2.h binutils-2.27/bfd/bfd-in2.h +--- binutils-2.27.orig/bfd/bfd-in2.h 2016-08-03 03:36:50.000000000 -0400 ++++ binutils-2.27/bfd/bfd-in2.h 2016-11-06 22:13:54.562451813 -0500 +@@ -2121,10 +2121,12 @@ + #define bfd_mach_sh_dsp 0x2d + #define bfd_mach_sh2a 0x2a + #define bfd_mach_sh2a_nofpu 0x2b ++#define bfd_mach_shj2 0x2c + #define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1 + #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + #define bfd_mach_sh2a_or_sh4 0x2a3 + #define bfd_mach_sh2a_or_sh3e 0x2a4 ++#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 + #define bfd_mach_sh2e 0x2e + #define bfd_mach_sh3 0x30 + #define bfd_mach_sh3_nommu 0x31 +diff -ur binutils-2.27.orig/bfd/cpu-sh.c binutils-2.27/bfd/cpu-sh.c +--- binutils-2.27.orig/bfd/cpu-sh.c 2016-08-03 03:36:50.000000000 -0400 ++++ binutils-2.27/bfd/cpu-sh.c 2016-11-06 22:13:54.562451813 -0500 +@@ -44,7 +44,9 @@ + #define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17 + #define SH2A_OR_SH4_NEXT arch_info_struct + 18 + #define SH2A_OR_SH3E_NEXT arch_info_struct + 19 +-#define SH64_NEXT NULL ++#define SH64_NEXT arch_info_struct + 20 ++#define SHJ2_NEXT arch_info_struct + 21 ++#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT NULL + + static const bfd_arch_info_type arch_info_struct[] = + { +@@ -348,6 +350,36 @@ + bfd_arch_default_fill, + SH64_NEXT + }, ++ { ++ 32, /* 32 bits in a word. */ ++ 32, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_sh, ++ bfd_mach_shj2, ++ "sh", /* Architecture name. . */ ++ "j2", /* Machine name. */ ++ 1, ++ FALSE, /* Not the default. */ ++ bfd_default_compatible, ++ bfd_default_scan, ++ bfd_arch_default_fill, ++ SHJ2_NEXT ++ }, ++ { ++ 32, /* 32 bits in a word. */ ++ 32, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_sh, ++ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, ++ "sh", /* Architecture name. . */ ++ "sh2a-or-sh3e-or-j2", /* Machine name. */ ++ 1, ++ FALSE, /* Not the default. */ ++ bfd_default_compatible, ++ bfd_default_scan, ++ bfd_arch_default_fill, ++ SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT ++ }, + }; + + const bfd_arch_info_type bfd_sh_arch = +@@ -398,6 +430,8 @@ + { bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up }, + { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up }, + { bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up }, ++ { bfd_mach_shj2, arch_shj2, arch_shj2_up }, ++ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up }, + { 0, 0, 0 } /* Terminator. */ + }; + +diff -ur binutils-2.27.orig/binutils/readelf.c binutils-2.27/binutils/readelf.c +--- binutils-2.27.orig/binutils/readelf.c 2016-08-03 03:36:51.000000000 -0400 ++++ binutils-2.27/binutils/readelf.c 2016-11-06 22:13:54.571449425 -0500 +@@ -3307,6 +3307,8 @@ + case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break; + case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break; + case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break; ++ case EF_SHJ2: strcat (buf, ", j2"); break; ++ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break; + default: strcat (buf, _(", unknown ISA")); break; + } + +diff -ur binutils-2.27.orig/gas/config/tc-sh.c binutils-2.27/gas/config/tc-sh.c +--- binutils-2.27.orig/gas/config/tc-sh.c 2016-08-03 03:36:51.000000000 -0400 ++++ binutils-2.27/gas/config/tc-sh.c 2016-11-06 22:13:54.575448363 -0500 +@@ -1648,6 +1648,8 @@ + ptr++; + } + get_operand (&ptr, operand + 2); ++ if (strcmp (info->name,"cas") == 0) ++ operand[2].type = A_IND_0; + } + else + { +@@ -2187,7 +2189,10 @@ + goto fail; + reg_m = 4; + break; +- ++ case A_IND_0: ++ if (user->reg != 0) ++ goto fail; ++ break; + default: + printf (_("unhandled %d\n"), arg); + goto fail; +diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2015-11-13 03:27:41.000000000 -0500 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2016-11-06 22:13:54.576448097 -0500 +@@ -12,8 +12,6 @@ + sh2a_nofpu_or_sh3_nommu: + ! Instructions introduced into sh2a-nofpu-or-sh3-nommu + pref @r4 ;!/* 0000nnnn10000011 pref @ */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + + ! Instructions inherited from ancestors: sh sh2 + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} +diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2015-11-13 03:27:41.000000000 -0500 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2016-11-06 22:13:54.576448097 -0500 +@@ -12,7 +12,7 @@ + sh2a_nofpu_or_sh4_nommu_nofpu: + ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -119,8 +119,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2015-11-13 03:27:41.000000000 -0500 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2016-11-06 22:13:54.577447832 -0500 +@@ -64,7 +64,7 @@ + movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(,), */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} + movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(,), */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -171,8 +171,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2015-11-13 03:27:41.000000000 -0500 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2016-11-06 22:13:54.578447567 -0500 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh2a-or-sh3e + fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -124,8 +124,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2015-11-13 03:27:41.000000000 -0500 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2016-11-06 22:13:54.579447301 -0500 +@@ -39,7 +39,7 @@ + fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub ,*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} + ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc ,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -150,8 +150,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a.s 2015-11-13 03:27:41.000000000 -0500 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a.s 2016-11-06 22:13:54.579447301 -0500 +@@ -16,7 +16,7 @@ + fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s ,@(,) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32} + fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(,), */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -140,8 +140,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.27/gas/testsuite/gas/sh/arch/sh3-dsp.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s 2015-11-13 03:27:41.000000000 -0500 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh3-dsp.s 2016-11-06 22:13:54.580447036 -0500 +@@ -12,7 +12,7 @@ + sh3_dsp: + ! Instructions introduced into sh3-dsp + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -152,8 +152,8 @@ + setrc #4 ;!/* 10000010i8*1.... setrc # */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh3-nommu.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s 2015-11-13 03:27:41.000000000 -0500 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh3-nommu.s 2016-11-06 22:13:54.581446771 -0500 +@@ -26,7 +26,7 @@ + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@- */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@- */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -133,8 +133,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.27/gas/testsuite/gas/sh/arch/sh3.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3.s 2015-11-13 03:27:41.000000000 -0500 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh3.s 2016-11-06 22:13:54.581446771 -0500 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh3 + ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -128,8 +128,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.27/gas/testsuite/gas/sh/arch/sh3e.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3e.s 2015-11-13 03:27:41.000000000 -0500 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh3e.s 2016-11-06 22:13:54.582446505 -0500 +@@ -12,7 +12,7 @@ + sh3e: + ! Instructions introduced into sh3e + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -132,8 +132,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4-nofpu.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2015-11-13 03:27:41.000000000 -0500 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2016-11-06 22:13:54.583446240 -0500 +@@ -12,7 +12,7 @@ + sh4_nofpu: + ! Instructions introduced into sh4-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -136,8 +136,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2015-11-13 03:27:41.000000000 -0500 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2016-11-06 22:13:54.583446240 -0500 +@@ -24,7 +24,7 @@ + stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@- */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@- */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -139,8 +139,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4.s 2015-11-13 03:27:41.000000000 -0500 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4.s 2016-11-06 22:13:54.584445974 -0500 +@@ -17,7 +17,7 @@ + fsrra fr1 ;!/* 1111nnnn01111101 fsrra */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up} + ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -145,8 +145,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4a-nofpu.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2015-11-13 03:27:41.000000000 -0500 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2016-11-06 22:13:54.584445974 -0500 +@@ -19,7 +19,7 @@ + prefi @r4 ;!/* 0000nnnn11010011 prefi @ */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} + synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -143,8 +143,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4a.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4a.s 2015-11-13 03:27:41.000000000 -0500 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4a.s 2016-11-06 22:13:54.585445709 -0500 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh4a + fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -147,8 +147,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4al-dsp.s +--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2015-11-13 03:27:41.000000000 -0500 ++++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2016-11-06 22:13:54.586445443 -0500 +@@ -48,7 +48,7 @@ + dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap , */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up} + dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap , */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up} + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -202,8 +202,8 @@ + setrc #4 ;!/* 10000010i8*1.... setrc # */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.27.orig/include/elf/sh.h binutils-2.27/include/elf/sh.h +--- binutils-2.27.orig/include/elf/sh.h 2016-08-03 03:36:53.000000000 -0400 ++++ binutils-2.27/include/elf/sh.h 2016-11-06 22:13:54.586445443 -0500 +@@ -39,6 +39,7 @@ + #define EF_SH2E 11 + #define EF_SH4A 12 + #define EF_SH2A 13 ++#define EF_SHJ2 14 + + #define EF_SH4_NOFPU 16 + #define EF_SH4A_NOFPU 17 +@@ -50,6 +51,7 @@ + #define EF_SH2A_SH3_NOFPU 22 + #define EF_SH2A_SH4 23 + #define EF_SH2A_SH3E 24 ++#define EF_SH2A_SH3_SHJ2 25 + + /* This one can only mix in objects from other EF_SH5 objects. */ + #define EF_SH5 10 +@@ -72,7 +74,8 @@ + /* EF_SH2E */ bfd_mach_sh2e , \ + /* EF_SH4A */ bfd_mach_sh4a , \ + /* EF_SH2A */ bfd_mach_sh2a , \ +-/* 14, 15 */ 0, 0, \ ++/* EF_SHJ2 */ bfd_mach_shj2 , \ ++/* 15 */ 0, \ + /* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \ + /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ + /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ +@@ -81,7 +84,8 @@ + /* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \ + /* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \ + /* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \ +-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e ++/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \ ++/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu + + /* Convert arch_sh* into EF_SH*. */ + int sh_find_elf_flags (unsigned int arch_set); +diff -ur binutils-2.27.orig/opcodes/sh-dis.c binutils-2.27/opcodes/sh-dis.c +--- binutils-2.27.orig/opcodes/sh-dis.c 2016-08-03 03:36:55.000000000 -0400 ++++ binutils-2.27/opcodes/sh-dis.c 2016-11-06 22:13:54.587445178 -0500 +@@ -868,6 +868,9 @@ + case XMTRX_M4: + fprintf_fn (stream, "xmtrx"); + break; ++ case A_IND_0: ++ fprintf_fn (stream, "@r0"); ++ break; + default: + abort (); + } +diff -ur binutils-2.27.orig/opcodes/sh-opc.h binutils-2.27/opcodes/sh-opc.h +--- binutils-2.27.orig/opcodes/sh-opc.h 2016-08-03 03:36:55.000000000 -0400 ++++ binutils-2.27/opcodes/sh-opc.h 2016-11-06 22:13:54.588444913 -0500 +@@ -191,7 +191,8 @@ + FPUL_N, + FPUL_M, + FPSCR_N, +- FPSCR_M ++ FPSCR_M, ++ A_IND_0 + } + sh_arg_type; + +@@ -218,9 +219,11 @@ + #define arch_sh4_base (1 << 5) + #define arch_sh4a_base (1 << 6) + #define arch_sh2a_base (1 << 7) +-#define arch_sh_base_mask MASK (0, 7) ++#define arch_shj2_base (1 << 8) ++#define arch_sh2a_sh3_shj2_base (1 << 9) ++#define arch_sh_base_mask MASK (0, 9) + +-/* Bits 8 ... 24 are currently free. */ ++/* Bits 10 ... 24 are currently free. */ + + /* This is an annotation on instruction types, but we + abuse the arch field in instructions to denote it. */ +@@ -258,6 +261,8 @@ + #define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co) + #define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu) + #define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu) ++#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co) + + #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) + #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) +@@ -323,7 +328,8 @@ + #define arch_sh2_up (arch_sh2 \ + | arch_sh2e_up \ + | arch_sh2a_nofpu_or_sh3_nommu_up \ +- | arch_sh_dsp_up) ++ | arch_sh_dsp_up \ ++ | arch_shj2_up) + #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \ + | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ + | arch_sh2a_or_sh3e_up \ +@@ -349,6 +355,12 @@ + #define arch_sh4a_nofpu_up (arch_sh4a_nofpu \ + | arch_sh4a_up \ + | arch_sh4al_dsp_up) ++#define arch_shj2_up ( arch_shj2) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \ ++ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ ++ | arch_sh2a_or_sh3e_up \ ++ | arch_sh3_nommu_up \ ++ | arch_shj2_up) + + /* Right branches. */ + #define arch_sh2e_up (arch_sh2e \ +@@ -717,9 +729,9 @@ + + /* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, + +-/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + +-/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + + /* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}, + +@@ -1197,7 +1209,7 @@ + {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}, + /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(,), */ + {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}, +- ++ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up}, + { 0, {0}, {0}, 0 } + }; + diff --git a/patches/binutils-2.27/0002-pr17739-sh-gc-sections-bug.diff b/patches/binutils-2.27/0002-pr17739-sh-gc-sections-bug.diff new file mode 100644 index 0000000..b1fc193 --- /dev/null +++ b/patches/binutils-2.27/0002-pr17739-sh-gc-sections-bug.diff @@ -0,0 +1,364 @@ +From a94d834c9d0108f0bb50ddc311554d1bed320f54 Mon Sep 17 00:00:00 2001 +From: Nick Clifton +Date: Tue, 2 Aug 2016 11:56:55 +0100 +Subject: [PATCH] Fix SH GOT allocation in the presence of linker garbage collection. + + PR ld/17739 +ld * emulparams/shelf.sh (CHECK_RELOCS_AFTER_OPEN_INPUT): Define with + valye 'yes'. + * emulparams/shelf32.sh: Likewise. + * emulparams/shelf32.sh: Likewise. + * emulparams/shelf_nto.sh: Likewise. + * emulparams/shelf_nto.sh: Likewise. + * emulparams/shelf_vxworks.sh: Likewise. + * emulparams/shelf_vxworks.sh: Likewise. + * emulparams/shlelf32_linux.sh: Likewise. + * emulparams/shlelf32_linux.sh: Likewise. + * emulparams/shlelf_linux.sh: Likewise. + * emulparams/shlelf_linux.sh: Likewise. + * emulparams/shlelf_nto.sh: Likewise. + * emulparams/shlelf_nto.sh: Likewise. + +bfd * elf32-sh.c (sh_elf_gc_sweep_hook): Delete. + (elf_backend_sweep_hook): Delete. +--- + bfd/elf32-sh.c | 215 --------------------------------------- + ld/emulparams/shelf.sh | 3 + + ld/emulparams/shelf32.sh | 3 + + ld/emulparams/shelf_nto.sh | 3 + + ld/emulparams/shelf_vxworks.sh | 4 + + ld/emulparams/shlelf32_linux.sh | 4 +- + ld/emulparams/shlelf_linux.sh | 3 + + ld/emulparams/shlelf_nto.sh | 3 + + 10 files changed, 46 insertions(+), 216 deletions(-) + +diff --git a/bfd/elf32-sh.c b/bfd/elf32-sh.c +index 52a5fd1..84c5b1e 100644 +--- a/bfd/elf32-sh.c ++++ b/bfd/elf32-sh.c +@@ -5682,220 +5682,6 @@ sh_elf_gc_mark_hook (asection *sec, + return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym); + } + +-/* Update the got entry reference counts for the section being removed. */ +- +-static bfd_boolean +-sh_elf_gc_sweep_hook (bfd *abfd, struct bfd_link_info *info, +- asection *sec, const Elf_Internal_Rela *relocs) +-{ +- Elf_Internal_Shdr *symtab_hdr; +- struct elf_link_hash_entry **sym_hashes; +- bfd_signed_vma *local_got_refcounts; +- union gotref *local_funcdesc; +- const Elf_Internal_Rela *rel, *relend; +- +- if (bfd_link_relocatable (info)) +- return TRUE; +- +- elf_section_data (sec)->local_dynrel = NULL; +- +- symtab_hdr = &elf_symtab_hdr (abfd); +- sym_hashes = elf_sym_hashes (abfd); +- local_got_refcounts = elf_local_got_refcounts (abfd); +- local_funcdesc = sh_elf_local_funcdesc (abfd); +- +- relend = relocs + sec->reloc_count; +- for (rel = relocs; rel < relend; rel++) +- { +- unsigned long r_symndx; +- unsigned int r_type; +- struct elf_link_hash_entry *h = NULL; +-#ifdef INCLUDE_SHMEDIA +- int seen_stt_datalabel = 0; +-#endif +- +- r_symndx = ELF32_R_SYM (rel->r_info); +- if (r_symndx >= symtab_hdr->sh_info) +- { +- struct elf_sh_link_hash_entry *eh; +- struct elf_sh_dyn_relocs **pp; +- struct elf_sh_dyn_relocs *p; +- +- h = sym_hashes[r_symndx - symtab_hdr->sh_info]; +- while (h->root.type == bfd_link_hash_indirect +- || h->root.type == bfd_link_hash_warning) +- { +-#ifdef INCLUDE_SHMEDIA +- seen_stt_datalabel |= h->type == STT_DATALABEL; +-#endif +- h = (struct elf_link_hash_entry *) h->root.u.i.link; +- } +- eh = (struct elf_sh_link_hash_entry *) h; +- for (pp = &eh->dyn_relocs; (p = *pp) != NULL; pp = &p->next) +- if (p->sec == sec) +- { +- /* Everything must go for SEC. */ +- *pp = p->next; +- break; +- } +- } +- +- r_type = ELF32_R_TYPE (rel->r_info); +- switch (sh_elf_optimized_tls_reloc (info, r_type, h != NULL)) +- { +- case R_SH_TLS_LD_32: +- if (sh_elf_hash_table (info)->tls_ldm_got.refcount > 0) +- sh_elf_hash_table (info)->tls_ldm_got.refcount -= 1; +- break; +- +- case R_SH_GOT32: +- case R_SH_GOT20: +- case R_SH_GOTOFF: +- case R_SH_GOTOFF20: +- case R_SH_GOTPC: +-#ifdef INCLUDE_SHMEDIA +- case R_SH_GOT_LOW16: +- case R_SH_GOT_MEDLOW16: +- case R_SH_GOT_MEDHI16: +- case R_SH_GOT_HI16: +- case R_SH_GOT10BY4: +- case R_SH_GOT10BY8: +- case R_SH_GOTOFF_LOW16: +- case R_SH_GOTOFF_MEDLOW16: +- case R_SH_GOTOFF_MEDHI16: +- case R_SH_GOTOFF_HI16: +- case R_SH_GOTPC_LOW16: +- case R_SH_GOTPC_MEDLOW16: +- case R_SH_GOTPC_MEDHI16: +- case R_SH_GOTPC_HI16: +-#endif +- case R_SH_TLS_GD_32: +- case R_SH_TLS_IE_32: +- case R_SH_GOTFUNCDESC: +- case R_SH_GOTFUNCDESC20: +- if (h != NULL) +- { +-#ifdef INCLUDE_SHMEDIA +- if (seen_stt_datalabel) +- { +- struct elf_sh_link_hash_entry *eh; +- eh = (struct elf_sh_link_hash_entry *) h; +- if (eh->datalabel_got.refcount > 0) +- eh->datalabel_got.refcount -= 1; +- } +- else +-#endif +- if (h->got.refcount > 0) +- h->got.refcount -= 1; +- } +- else if (local_got_refcounts != NULL) +- { +-#ifdef INCLUDE_SHMEDIA +- if (rel->r_addend & 1) +- { +- if (local_got_refcounts[symtab_hdr->sh_info + r_symndx] > 0) +- local_got_refcounts[symtab_hdr->sh_info + r_symndx] -= 1; +- } +- else +-#endif +- if (local_got_refcounts[r_symndx] > 0) +- local_got_refcounts[r_symndx] -= 1; +- } +- break; +- +- case R_SH_FUNCDESC: +- if (h != NULL) +- sh_elf_hash_entry (h)->abs_funcdesc_refcount -= 1; +- else if (sh_elf_hash_table (info)->fdpic_p && !bfd_link_pic (info)) +- sh_elf_hash_table (info)->srofixup->size -= 4; +- +- /* Fall through. */ +- +- case R_SH_GOTOFFFUNCDESC: +- case R_SH_GOTOFFFUNCDESC20: +- if (h != NULL) +- sh_elf_hash_entry (h)->funcdesc.refcount -= 1; +- else +- local_funcdesc[r_symndx].refcount -= 1; +- break; +- +- case R_SH_DIR32: +- if (sh_elf_hash_table (info)->fdpic_p && !bfd_link_pic (info) +- && (sec->flags & SEC_ALLOC) != 0) +- sh_elf_hash_table (info)->srofixup->size -= 4; +- /* Fall thru */ +- +- case R_SH_REL32: +- if (bfd_link_pic (info)) +- break; +- /* Fall thru */ +- +- case R_SH_PLT32: +-#ifdef INCLUDE_SHMEDIA +- case R_SH_PLT_LOW16: +- case R_SH_PLT_MEDLOW16: +- case R_SH_PLT_MEDHI16: +- case R_SH_PLT_HI16: +-#endif +- if (h != NULL) +- { +- if (h->plt.refcount > 0) +- h->plt.refcount -= 1; +- } +- break; +- +- case R_SH_GOTPLT32: +-#ifdef INCLUDE_SHMEDIA +- case R_SH_GOTPLT_LOW16: +- case R_SH_GOTPLT_MEDLOW16: +- case R_SH_GOTPLT_MEDHI16: +- case R_SH_GOTPLT_HI16: +- case R_SH_GOTPLT10BY4: +- case R_SH_GOTPLT10BY8: +-#endif +- if (h != NULL) +- { +- struct elf_sh_link_hash_entry *eh; +- eh = (struct elf_sh_link_hash_entry *) h; +- if (eh->gotplt_refcount > 0) +- { +- eh->gotplt_refcount -= 1; +- if (h->plt.refcount > 0) +- h->plt.refcount -= 1; +- } +-#ifdef INCLUDE_SHMEDIA +- else if (seen_stt_datalabel) +- { +- if (eh->datalabel_got.refcount > 0) +- eh->datalabel_got.refcount -= 1; +- } +-#endif +- else if (h->got.refcount > 0) +- h->got.refcount -= 1; +- } +- else if (local_got_refcounts != NULL) +- { +-#ifdef INCLUDE_SHMEDIA +- if (rel->r_addend & 1) +- { +- if (local_got_refcounts[symtab_hdr->sh_info + r_symndx] > 0) +- local_got_refcounts[symtab_hdr->sh_info + r_symndx] -= 1; +- } +- else +-#endif +- if (local_got_refcounts[r_symndx] > 0) +- local_got_refcounts[r_symndx] -= 1; +- } +- break; +- +- default: +- break; +- } +- } +- +- return TRUE; +-} +- + /* Copy the extra info we tack onto an elf_link_hash_entry. */ + + static void +@@ -7455,7 +7241,6 @@ sh_elf_encode_eh_address (bfd *abfd, + sh_elf_merge_private_data + + #define elf_backend_gc_mark_hook sh_elf_gc_mark_hook +-#define elf_backend_gc_sweep_hook sh_elf_gc_sweep_hook + #define elf_backend_check_relocs sh_elf_check_relocs + #define elf_backend_copy_indirect_symbol \ + sh_elf_copy_indirect_symbol +diff --git a/ld/emulparams/shelf.sh b/ld/emulparams/shelf.sh +index 83680a6..d3f4752 100644 +--- a/ld/emulparams/shelf.sh ++++ b/ld/emulparams/shelf.sh +@@ -11,6 +11,9 @@ MACHINE= + TEMPLATE_NAME=elf32 + GENERATE_SHLIB_SCRIPT=yes + EMBEDDED=yes ++# PR 17739. Delay checking relocs until after all files have ++# been opened and linker garbage collection has taken place. ++CHECK_RELOCS_AFTER_OPEN_INPUT=yes + + # These are for compatibility with the COFF toolchain. + ENTRY=start +diff --git a/ld/emulparams/shelf32.sh b/ld/emulparams/shelf32.sh +index 966bd30..bf362c5 100644 +--- a/ld/emulparams/shelf32.sh ++++ b/ld/emulparams/shelf32.sh +@@ -11,6 +11,9 @@ ALIGNMENT=8 + TEMPLATE_NAME=elf32 + GENERATE_SHLIB_SCRIPT=yes + EMBEDDED=yes ++# PR 17739. Delay checking relocs until after all files have ++# been opened and linker garbage collection has taken place. ++CHECK_RELOCS_AFTER_OPEN_INPUT=yes + + DATA_START_SYMBOLS='PROVIDE (___data = .);' + +diff --git a/ld/emulparams/shelf_nto.sh b/ld/emulparams/shelf_nto.sh +index c4d71aa..46efd87 100644 +--- a/ld/emulparams/shelf_nto.sh ++++ b/ld/emulparams/shelf_nto.sh +@@ -9,3 +9,6 @@ TEMPLATE_NAME=elf32 + GENERATE_SHLIB_SCRIPT=yes + TEXT_START_SYMBOLS='_btext = .;' + ENTRY=_start ++# PR 17739. Delay checking relocs until after all files have ++# been opened and linker garbage collection has taken place. ++CHECK_RELOCS_AFTER_OPEN_INPUT=yes +diff --git a/ld/emulparams/shelf_vxworks.sh b/ld/emulparams/shelf_vxworks.sh +index 77619cb..759ffac 100644 +--- a/ld/emulparams/shelf_vxworks.sh ++++ b/ld/emulparams/shelf_vxworks.sh +@@ -14,6 +14,10 @@ TEMPLATE_NAME=elf32 + GENERATE_SHLIB_SCRIPT=yes + ENTRY=__start + SYMPREFIX=_ ++# PR 17739. Delay checking relocs until after all files have ++# been opened and linker garbage collection has taken place. ++CHECK_RELOCS_AFTER_OPEN_INPUT=yes ++ + GOT=".got ${RELOCATING-0} : { + PROVIDE(__GLOBAL_OFFSET_TABLE_ = .); + *(.got.plt) *(.got) }" +diff --git a/ld/emulparams/shlelf32_linux.sh b/ld/emulparams/shlelf32_linux.sh +index 81aea39..0327e57 100644 +--- a/ld/emulparams/shlelf32_linux.sh ++++ b/ld/emulparams/shlelf32_linux.sh +@@ -13,7 +13,9 @@ ALIGNMENT=8 + TEMPLATE_NAME=elf32 + GENERATE_SHLIB_SCRIPT=yes + GENERATE_PIE_SCRIPT=yes +- ++# PR 17739. Delay checking relocs until after all files have ++# been opened and linker garbage collection has taken place. ++CHECK_RELOCS_AFTER_OPEN_INPUT=yes + + DATA_START_SYMBOLS='PROVIDE (___data = .);' + +diff --git a/ld/emulparams/shlelf_linux.sh b/ld/emulparams/shlelf_linux.sh +index c14aae2..4e2a581 100644 +--- a/ld/emulparams/shlelf_linux.sh ++++ b/ld/emulparams/shlelf_linux.sh +@@ -12,6 +12,9 @@ MACHINE= + TEMPLATE_NAME=elf32 + GENERATE_SHLIB_SCRIPT=yes + GENERATE_PIE_SCRIPT=yes ++# PR 17739. Delay checking relocs until after all files have ++# been opened and linker garbage collection has taken place. ++CHECK_RELOCS_AFTER_OPEN_INPUT=yes + + DATA_START_SYMBOLS='PROVIDE (__data_start = .);'; + +diff --git a/ld/emulparams/shlelf_nto.sh b/ld/emulparams/shlelf_nto.sh +index 16f6508..f8ffc13 100644 +--- a/ld/emulparams/shlelf_nto.sh ++++ b/ld/emulparams/shlelf_nto.sh +@@ -9,3 +9,6 @@ TEMPLATE_NAME=elf32 + GENERATE_SHLIB_SCRIPT=yes + TEXT_START_SYMBOLS='_btext = .;' + ENTRY=_start ++# PR 17739. Delay checking relocs until after all files have ++# been opened and linker garbage collection has taken place. ++CHECK_RELOCS_AFTER_OPEN_INPUT=yes +-- +1.7.1 + diff --git a/patches/binutils-2.27/0003-microblaze-pr21017.diff b/patches/binutils-2.27/0003-microblaze-pr21017.diff new file mode 100644 index 0000000..45711d4 --- /dev/null +++ b/patches/binutils-2.27/0003-microblaze-pr21017.diff @@ -0,0 +1,10 @@ +--- binutils-2.27/bfd/elf32-microblaze.c.orig 2017-01-02 15:44:42.110115295 -0500 ++++ binutils-2.27/bfd/elf32-microblaze.c 2017-01-02 15:43:22.768999626 -0500 +@@ -2399,6 +2399,7 @@ + tls_type |= (TLS_TLS | TLS_LD); + dogottls: + sec->has_tls_reloc = 1; ++ case R_MICROBLAZE_GOTOFF_64: + case R_MICROBLAZE_GOT_64: + if (htab->sgot == NULL) + { diff --git a/patches/binutils-2.27/0004-mips-pie-tls.diff b/patches/binutils-2.27/0004-mips-pie-tls.diff new file mode 100644 index 0000000..9c4f0ff --- /dev/null +++ b/patches/binutils-2.27/0004-mips-pie-tls.diff @@ -0,0 +1,21 @@ +diff -ur binutils-2.27.orig/bfd/elfxx-mips.c binutils-2.27/bfd/elfxx-mips.c +--- binutils-2.27.orig/bfd/elfxx-mips.c 2016-08-03 03:36:51.000000000 -0400 ++++ binutils-2.27/bfd/elfxx-mips.c 2018-01-31 12:11:22.458824584 -0500 +@@ -3242,7 +3242,7 @@ + && (!bfd_link_pic (info) || !SYMBOL_REFERENCES_LOCAL (info, h))) + indx = h->dynindx; + +- if ((bfd_link_pic (info) || indx != 0) ++ if ((bfd_link_dll (info) || indx != 0) + && (h == NULL + || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + || h->root.type != bfd_link_hash_undefweak)) +@@ -3354,7 +3354,7 @@ + if (entry->tls_initialized) + return; + +- if ((bfd_link_pic (info) || indx != 0) ++ if ((bfd_link_dll (info) || indx != 0) + && (h == NULL + || ELF_ST_VISIBILITY (h->root.other) == STV_DEFAULT + || h->root.type != bfd_link_hash_undefweak)) diff --git a/patches/binutils-2.27/0005-mips-reproducible.patch b/patches/binutils-2.27/0005-mips-reproducible.patch new file mode 100644 index 0000000..5b92ce7 --- /dev/null +++ b/patches/binutils-2.27/0005-mips-reproducible.patch @@ -0,0 +1,21 @@ +[PATCH] fix deterministic output for mips archiver + +for historical reasons mips uses a slightly different archive format, +and when the --enable-deterministic-archives option was implemented, +it was only done for the generic archive format, but not for the one +used by mips. + +Signed-off-by: John Spencer + +--- binutils-2.24.90.org/bfd/archive64.c ++++ binutils-2.24.90/bfd/archive64.c +@@ -171,7 +171,8 @@ + if (!_bfd_ar_sizepad (hdr.ar_size, sizeof (hdr.ar_size), mapsize)) + return FALSE; + _bfd_ar_spacepad (hdr.ar_date, sizeof (hdr.ar_date), "%ld", +- time (NULL)); ++ ((arch->flags & BFD_DETERMINISTIC_OUTPUT) == 0 ++ ? time (NULL) : 0)); + /* This, at least, is what Intel coff sets the values to.: */ + _bfd_ar_spacepad (hdr.ar_uid, sizeof (hdr.ar_uid), "%ld", 0); + _bfd_ar_spacepad (hdr.ar_gid, sizeof (hdr.ar_gid), "%ld", 0); diff --git a/patches/binutils-2.27/0006-arm-pie-tls.diff b/patches/binutils-2.27/0006-arm-pie-tls.diff new file mode 100644 index 0000000..897b2a1 --- /dev/null +++ b/patches/binutils-2.27/0006-arm-pie-tls.diff @@ -0,0 +1,83 @@ +From 7d6e280a0f3b9978b0edb20173d067d071531a3d Mon Sep 17 00:00:00 2001 +From: Szabolcs Nagy +Date: Wed, 2 Oct 2019 19:46:46 +0100 +Subject: [PATCH] [PR ld/22263][PR ld/25056] arm: Avoid dynamic TLS relocs in + PIE + +Dynamic relocs are only needed in an executable for TLS symbols if +those are defined in an external module and even then TLS access +can be relaxed to use IE model instead of GD. + +Several bfd_link_pic checks are turned into bfd_link_dll checks +to fix TLS handling in PIE, for the same fix some other targets +used !bfd_link_executable checks, but that includes relocatable +objects so dll seems safer (in most cases either should work, since +dynamic relocations are not applied in relocatable objects). + +On arm* fixes +FAIL: Build pr22263-1 + +bfd/ +2019-10-02 Szabolcs Nagy + PR ld/22263 + PR ld/25056 + * elf32-arm.c (elf32_arm_tls_transition): Use bfd_link_dll instead of + bfd_link_pic for TLS checks. + (elf32_arm_final_link_relocate): Likewise. + (allocate_dynrelocs_for_symbol): Likewise. +--- + bfd/elf32-arm.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c +index bb53e039e3..451949d278 100644 +--- a/bfd/elf32-arm.c ++++ b/bfd/elf32-arm.c +@@ -4914,7 +4914,7 @@ elf32_arm_tls_transition (struct bfd_link_info *info, int r_type, + { + int is_local = (h == NULL); + +- if (bfd_link_pic (info) ++ if (bfd_link_dll (info) + || (h && h->root.type == bfd_link_hash_undefweak)) + return r_type; + +@@ -11700,7 +11700,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, + { + /* If we don't know the module number, create a relocation + for it. */ +- if (bfd_link_pic (info)) ++ if (bfd_link_dll (info)) + { + Elf_Internal_Rela outrel; + +@@ -11804,7 +11804,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, + now, and emit any relocations. If both an IE GOT and a + GD GOT are necessary, we emit the GD first. */ + +- if ((bfd_link_pic (info) || indx != 0) ++ if ((bfd_link_dll (info) || indx != 0) + && (h == NULL + || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + && !resolved_to_zero) +@@ -11821,7 +11821,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, + /* We should have relaxed, unless this is an undefined + weak symbol. */ + BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak)) +- || bfd_link_pic (info)); ++ || bfd_link_dll (info)); + BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8 + <= globals->root.sgotplt->size); + +@@ -16494,7 +16494,7 @@ allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf) + indx = h->dynindx; + + if (tls_type != GOT_NORMAL +- && (bfd_link_pic (info) || indx != 0) ++ && (bfd_link_dll (info) || indx != 0) + && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + || h->root.type != bfd_link_hash_undefweak)) + { +-- +2.17.1 + diff --git a/patches/binutils-2.27/0007-arm-tlsdesc-64bithost.diff b/patches/binutils-2.27/0007-arm-tlsdesc-64bithost.diff new file mode 100644 index 0000000..a95cbc0 --- /dev/null +++ b/patches/binutils-2.27/0007-arm-tlsdesc-64bithost.diff @@ -0,0 +1,16 @@ +diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c +index bb53e039e3..d52c046979 100644 +--- a/bfd/elf32-arm.c ++++ b/bfd/elf32-arm.c +@@ -12027,9 +12027,9 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, + unsigned long data, insn; + unsigned thumb; + +- data = bfd_get_32 (input_bfd, hit_data); ++ data = bfd_get_signed_32 (input_bfd, hit_data); + thumb = data & 1; +- data &= ~1u; ++ data &= ~1ul; + + if (thumb) + { diff --git a/patches/binutils-2.32/0001-j2.diff b/patches/binutils-2.32/0001-j2.diff new file mode 100644 index 0000000..f08140e --- /dev/null +++ b/patches/binutils-2.32/0001-j2.diff @@ -0,0 +1,620 @@ +diff -ur binutils-2.32.orig/bfd/archures.c binutils-2.32/bfd/archures.c +--- binutils-2.32.orig/bfd/archures.c 2019-01-19 11:01:32.000000000 -0500 ++++ binutils-2.32/bfd/archures.c 2019-05-26 15:09:15.968501965 -0400 +@@ -298,6 +298,8 @@ + .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + .#define bfd_mach_sh2a_or_sh4 0x2a3 + .#define bfd_mach_sh2a_or_sh3e 0x2a4 ++.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 ++.#define bfd_mach_shj2 0x2c + .#define bfd_mach_sh2e 0x2e + .#define bfd_mach_sh3 0x30 + .#define bfd_mach_sh3_nommu 0x31 +Only in binutils-2.32/bfd: archures.c.orig +Only in binutils-2.32/bfd: archures.c.rej +diff -ur binutils-2.32.orig/bfd/bfd-in2.h binutils-2.32/bfd/bfd-in2.h +--- binutils-2.32.orig/bfd/bfd-in2.h 2019-01-19 11:01:32.000000000 -0500 ++++ binutils-2.32/bfd/bfd-in2.h 2019-05-26 15:10:21.005775819 -0400 +@@ -2197,6 +2197,8 @@ + #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + #define bfd_mach_sh2a_or_sh4 0x2a3 + #define bfd_mach_sh2a_or_sh3e 0x2a4 ++#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 ++#define bfd_mach_shj2 0x2c + #define bfd_mach_sh2e 0x2e + #define bfd_mach_sh3 0x30 + #define bfd_mach_sh3_nommu 0x31 +Only in binutils-2.32/bfd: bfd-in2.h.orig +Only in binutils-2.32/bfd: bfd-in2.h.rej +diff -ur binutils-2.32.orig/bfd/cpu-sh.c binutils-2.32/bfd/cpu-sh.c +--- binutils-2.32.orig/bfd/cpu-sh.c 2019-01-19 11:01:32.000000000 -0500 ++++ binutils-2.32/bfd/cpu-sh.c 2019-05-26 15:13:00.461455381 -0400 +@@ -43,7 +43,10 @@ + #define SH2A_NOFPU_OR_SH4_NOMMU_NOFPU_NEXT arch_info_struct + 16 + #define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17 + #define SH2A_OR_SH4_NEXT arch_info_struct + 18 +-#define SH2A_OR_SH3E_NEXT NULL ++#define SH2A_OR_SH3E_NEXT arch_info_struct + 19 ++#define SHJ2_NEXT arch_info_struct + 20 ++#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT NULL ++ + + static const bfd_arch_info_type arch_info_struct[] = + { +@@ -332,6 +335,36 @@ + bfd_arch_default_fill, + SH2A_OR_SH3E_NEXT + }, ++ { ++ 32, /* 32 bits in a word. */ ++ 32, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_sh, ++ bfd_mach_shj2, ++ "sh", /* Architecture name. . */ ++ "j2", /* Machine name. */ ++ 1, ++ FALSE, /* Not the default. */ ++ bfd_default_compatible, ++ bfd_default_scan, ++ bfd_arch_default_fill, ++ SHJ2_NEXT ++ }, ++ { ++ 32, /* 32 bits in a word. */ ++ 32, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_sh, ++ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, ++ "sh", /* Architecture name. . */ ++ "sh2a-or-sh3e-or-j2", /* Machine name. */ ++ 1, ++ FALSE, /* Not the default. */ ++ bfd_default_compatible, ++ bfd_default_scan, ++ bfd_arch_default_fill, ++ SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT ++ }, + }; + + const bfd_arch_info_type bfd_sh_arch = +@@ -382,6 +415,8 @@ + { bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up }, + { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up }, + { bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up }, ++ { bfd_mach_shj2, arch_shj2, arch_shj2_up }, ++ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up }, + { 0, 0, 0 } /* Terminator. */ + }; + +Only in binutils-2.32/bfd: cpu-sh.c.orig +Only in binutils-2.32/bfd: cpu-sh.c.rej +diff -ur binutils-2.32.orig/binutils/readelf.c binutils-2.32/binutils/readelf.c +--- binutils-2.32.orig/binutils/readelf.c 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/binutils/readelf.c 2019-05-26 15:07:03.563950564 -0400 +@@ -3528,6 +3528,8 @@ + case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break; + case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break; + case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break; ++ case EF_SHJ2: strcat (buf, ", j2"); break; ++ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break; + default: strcat (buf, _(", unknown ISA")); break; + } + +Only in binutils-2.32/binutils: readelf.c.orig +diff -ur binutils-2.32.orig/gas/config/tc-sh.c binutils-2.32/gas/config/tc-sh.c +--- binutils-2.32.orig/gas/config/tc-sh.c 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/config/tc-sh.c 2019-05-26 15:07:03.567950581 -0400 +@@ -1251,6 +1251,8 @@ + ptr++; + } + get_operand (&ptr, operand + 2); ++ if (strcmp (info->name,"cas") == 0) ++ operand[2].type = A_IND_0; + } + else + { +@@ -1790,7 +1792,10 @@ + goto fail; + reg_m = 4; + break; +- ++ case A_IND_0: ++ if (user->reg != 0) ++ goto fail; ++ break; + default: + printf (_("unhandled %d\n"), arg); + goto fail; +Only in binutils-2.32/gas/config: tc-sh.c.orig +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2019-05-26 15:07:03.568950585 -0400 +@@ -12,8 +12,6 @@ + sh2a_nofpu_or_sh3_nommu: + ! Instructions introduced into sh2a-nofpu-or-sh3-nommu + pref @r4 ;!/* 0000nnnn10000011 pref @ */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + + ! Instructions inherited from ancestors: sh sh2 + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2019-05-26 15:07:03.570950593 -0400 +@@ -12,7 +12,7 @@ + sh2a_nofpu_or_sh4_nommu_nofpu: + ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -119,8 +119,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2019-05-26 15:07:03.571950597 -0400 +@@ -64,7 +64,7 @@ + movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(,), */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} + movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(,), */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -171,8 +171,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2019-05-26 15:07:03.572950601 -0400 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh2a-or-sh3e + fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -124,8 +124,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2019-05-26 15:07:03.574950610 -0400 +@@ -39,7 +39,7 @@ + fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub ,*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} + ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc ,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -150,8 +150,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a.s 2019-05-26 15:07:03.575950614 -0400 +@@ -16,7 +16,7 @@ + fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s ,@(,) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32} + fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(,), */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -140,8 +140,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3-dsp.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3-dsp.s 2019-05-26 15:07:03.577950622 -0400 +@@ -12,7 +12,7 @@ + sh3_dsp: + ! Instructions introduced into sh3-dsp + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -152,8 +152,8 @@ + setrc #4 ;!/* 10000010i8*1.... setrc # */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3-nommu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3-nommu.s 2019-05-26 15:07:03.578950626 -0400 +@@ -26,7 +26,7 @@ + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@- */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@- */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -133,8 +133,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3.s 2019-05-26 15:07:03.579950630 -0400 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh3 + ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -128,8 +128,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3e.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3e.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3e.s 2019-05-26 15:07:03.581950639 -0400 +@@ -12,7 +12,7 @@ + sh3e: + ! Instructions introduced into sh3e + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -132,8 +132,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nofpu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2019-05-26 15:07:03.582950643 -0400 +@@ -12,7 +12,7 @@ + sh4_nofpu: + ! Instructions introduced into sh4-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -136,8 +136,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2019-05-26 15:07:03.583950647 -0400 +@@ -24,7 +24,7 @@ + stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@- */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@- */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -139,8 +139,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4.s 2019-05-26 15:07:03.585950655 -0400 +@@ -17,7 +17,7 @@ + fsrra fr1 ;!/* 1111nnnn01111101 fsrra */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up} + ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -145,8 +145,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4a-nofpu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2019-05-26 15:07:03.586950659 -0400 +@@ -19,7 +19,7 @@ + prefi @r4 ;!/* 0000nnnn11010011 prefi @ */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} + synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -143,8 +143,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4a.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4a.s 2019-05-26 15:07:03.588950668 -0400 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh4a + fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -147,8 +147,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4al-dsp.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2019-05-26 15:07:03.589950672 -0400 +@@ -48,7 +48,7 @@ + dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap , */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up} + dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap , */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up} + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -202,8 +202,8 @@ + setrc #4 ;!/* 10000010i8*1.... setrc # */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/include/elf/sh.h binutils-2.32/include/elf/sh.h +--- binutils-2.32.orig/include/elf/sh.h 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/include/elf/sh.h 2019-05-26 15:07:03.590950676 -0400 +@@ -39,6 +39,7 @@ + #define EF_SH2E 11 + #define EF_SH4A 12 + #define EF_SH2A 13 ++#define EF_SHJ2 14 + + #define EF_SH4_NOFPU 16 + #define EF_SH4A_NOFPU 17 +@@ -50,6 +51,7 @@ + #define EF_SH2A_SH3_NOFPU 22 + #define EF_SH2A_SH4 23 + #define EF_SH2A_SH3E 24 ++#define EF_SH2A_SH3_SHJ2 25 + + /* This one can only mix in objects from other EF_SH5 objects. */ + #define EF_SH5 10 +@@ -72,7 +74,8 @@ + /* EF_SH2E */ bfd_mach_sh2e , \ + /* EF_SH4A */ bfd_mach_sh4a , \ + /* EF_SH2A */ bfd_mach_sh2a , \ +-/* 14, 15 */ 0, 0, \ ++/* EF_SHJ2 */ bfd_mach_shj2 , \ ++/* 15 */ 0, \ + /* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \ + /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ + /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ +@@ -81,7 +84,8 @@ + /* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \ + /* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \ + /* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \ +-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e ++/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \ ++/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu + + /* Convert arch_sh* into EF_SH*. */ + int sh_find_elf_flags (unsigned int arch_set); +diff -ur binutils-2.32.orig/opcodes/sh-dis.c binutils-2.32/opcodes/sh-dis.c +--- binutils-2.32.orig/opcodes/sh-dis.c 2019-01-19 11:01:34.000000000 -0500 ++++ binutils-2.32/opcodes/sh-dis.c 2019-05-26 15:07:03.593950688 -0400 +@@ -856,6 +856,9 @@ + case XMTRX_M4: + fprintf_fn (stream, "xmtrx"); + break; ++ case A_IND_0: ++ fprintf_fn (stream, "@r0"); ++ break; + default: + abort (); + } +Only in binutils-2.32/opcodes: sh-dis.c.orig +diff -ur binutils-2.32.orig/opcodes/sh-opc.h binutils-2.32/opcodes/sh-opc.h +--- binutils-2.32.orig/opcodes/sh-opc.h 2019-01-19 11:01:34.000000000 -0500 ++++ binutils-2.32/opcodes/sh-opc.h 2019-05-26 15:07:03.597950705 -0400 +@@ -191,7 +191,8 @@ + FPUL_N, + FPUL_M, + FPSCR_N, +- FPSCR_M ++ FPSCR_M, ++ A_IND_0 + } + sh_arg_type; + +@@ -215,9 +216,11 @@ + #define arch_sh4_base (1 << 5) + #define arch_sh4a_base (1 << 6) + #define arch_sh2a_base (1 << 7) +-#define arch_sh_base_mask MASK (0, 7) ++#define arch_shj2_base (1 << 8) ++#define arch_sh2a_sh3_shj2_base (1 << 9) ++#define arch_sh_base_mask MASK (0, 9) + +-/* Bits 8 ... 24 are currently free. */ ++/* Bits 10 ... 24 are currently free. */ + + /* This is an annotation on instruction types, but we + abuse the arch field in instructions to denote it. */ +@@ -255,6 +258,8 @@ + #define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co) + #define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu) + #define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu) ++#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co) + + #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) + #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) +@@ -319,7 +324,8 @@ + #define arch_sh2_up (arch_sh2 \ + | arch_sh2e_up \ + | arch_sh2a_nofpu_or_sh3_nommu_up \ +- | arch_sh_dsp_up) ++ | arch_sh_dsp_up \ ++ | arch_shj2_up) + #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \ + | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ + | arch_sh2a_or_sh3e_up \ +@@ -345,6 +351,12 @@ + #define arch_sh4a_nofpu_up (arch_sh4a_nofpu \ + | arch_sh4a_up \ + | arch_sh4al_dsp_up) ++#define arch_shj2_up ( arch_shj2) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \ ++ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ ++ | arch_sh2a_or_sh3e_up \ ++ | arch_sh3_nommu_up \ ++ | arch_shj2_up) + + /* Right branches. */ + #define arch_sh2e_up (arch_sh2e \ +@@ -713,9 +725,9 @@ + + /* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, + +-/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + +-/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + + /* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}, + +@@ -1193,7 +1205,7 @@ + {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}, + /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(,), */ + {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}, +- ++ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up}, + { 0, {0}, {0}, 0 } + }; + +Only in binutils-2.32/opcodes: sh-opc.h.orig diff --git a/patches/binutils-2.32/0002-arm-pie-tls.diff b/patches/binutils-2.32/0002-arm-pie-tls.diff new file mode 100644 index 0000000..897b2a1 --- /dev/null +++ b/patches/binutils-2.32/0002-arm-pie-tls.diff @@ -0,0 +1,83 @@ +From 7d6e280a0f3b9978b0edb20173d067d071531a3d Mon Sep 17 00:00:00 2001 +From: Szabolcs Nagy +Date: Wed, 2 Oct 2019 19:46:46 +0100 +Subject: [PATCH] [PR ld/22263][PR ld/25056] arm: Avoid dynamic TLS relocs in + PIE + +Dynamic relocs are only needed in an executable for TLS symbols if +those are defined in an external module and even then TLS access +can be relaxed to use IE model instead of GD. + +Several bfd_link_pic checks are turned into bfd_link_dll checks +to fix TLS handling in PIE, for the same fix some other targets +used !bfd_link_executable checks, but that includes relocatable +objects so dll seems safer (in most cases either should work, since +dynamic relocations are not applied in relocatable objects). + +On arm* fixes +FAIL: Build pr22263-1 + +bfd/ +2019-10-02 Szabolcs Nagy + PR ld/22263 + PR ld/25056 + * elf32-arm.c (elf32_arm_tls_transition): Use bfd_link_dll instead of + bfd_link_pic for TLS checks. + (elf32_arm_final_link_relocate): Likewise. + (allocate_dynrelocs_for_symbol): Likewise. +--- + bfd/elf32-arm.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c +index bb53e039e3..451949d278 100644 +--- a/bfd/elf32-arm.c ++++ b/bfd/elf32-arm.c +@@ -4914,7 +4914,7 @@ elf32_arm_tls_transition (struct bfd_link_info *info, int r_type, + { + int is_local = (h == NULL); + +- if (bfd_link_pic (info) ++ if (bfd_link_dll (info) + || (h && h->root.type == bfd_link_hash_undefweak)) + return r_type; + +@@ -11700,7 +11700,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, + { + /* If we don't know the module number, create a relocation + for it. */ +- if (bfd_link_pic (info)) ++ if (bfd_link_dll (info)) + { + Elf_Internal_Rela outrel; + +@@ -11804,7 +11804,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, + now, and emit any relocations. If both an IE GOT and a + GD GOT are necessary, we emit the GD first. */ + +- if ((bfd_link_pic (info) || indx != 0) ++ if ((bfd_link_dll (info) || indx != 0) + && (h == NULL + || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + && !resolved_to_zero) +@@ -11821,7 +11821,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, + /* We should have relaxed, unless this is an undefined + weak symbol. */ + BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak)) +- || bfd_link_pic (info)); ++ || bfd_link_dll (info)); + BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8 + <= globals->root.sgotplt->size); + +@@ -16494,7 +16494,7 @@ allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf) + indx = h->dynindx; + + if (tls_type != GOT_NORMAL +- && (bfd_link_pic (info) || indx != 0) ++ && (bfd_link_dll (info) || indx != 0) + && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + || h->root.type != bfd_link_hash_undefweak)) + { +-- +2.17.1 + diff --git a/patches/binutils-2.32/0003-arm-tlsdesc-64bithost.diff b/patches/binutils-2.32/0003-arm-tlsdesc-64bithost.diff new file mode 100644 index 0000000..a95cbc0 --- /dev/null +++ b/patches/binutils-2.32/0003-arm-tlsdesc-64bithost.diff @@ -0,0 +1,16 @@ +diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c +index bb53e039e3..d52c046979 100644 +--- a/bfd/elf32-arm.c ++++ b/bfd/elf32-arm.c +@@ -12027,9 +12027,9 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, + unsigned long data, insn; + unsigned thumb; + +- data = bfd_get_32 (input_bfd, hit_data); ++ data = bfd_get_signed_32 (input_bfd, hit_data); + thumb = data & 1; +- data &= ~1u; ++ data &= ~1ul; + + if (thumb) + { diff --git a/patches/binutils-2.32/0004-arm-pr22269.diff b/patches/binutils-2.32/0004-arm-pr22269.diff new file mode 100644 index 0000000..79043fb --- /dev/null +++ b/patches/binutils-2.32/0004-arm-pr22269.diff @@ -0,0 +1,55 @@ +From: Szabolcs Nagy +Date: Thu, 9 Jan 2020 17:20:56 +0000 (+0000) +Subject: [PR ld/22269] arm: Avoid dynamic relocs for undefweak symbols in static PIE +X-Git-Url: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commitdiff_plain;h=6fbcfe4762c3732339cffd82426d00d35382b858;hp=c06868784d819a45c43947180c69e168aecaf368 + +[PR ld/22269] arm: Avoid dynamic relocs for undefweak symbols in static PIE + +With static PIE linking undefined weak symbols are resolved to 0, so no +dynamic relocation is needed for them. The UNDEFWEAK_NO_DYNAMIC_RELOC +macro was introduced so this case can be handled easily, but it was not +applied consistently in the first attempt to fix ld/22269 for arm: + + commit 95b03e4ad68e7a90f5096b47df595636344b783a + arm: Check UNDEFWEAK_NO_DYNAMIC_RELOC + +This patch fixes spurious relative relocs in static PIE binaries against +GOT entries created for undefined weak symbols on arm*-*, this fixes + +FAIL: pr22269-1 (static pie undefined weak) + +bfd/ChangeLog: + + Backported from master + 2020-01-10 Szabolcs Nagy + + PR ld/22269 + * elf32-arm.c (elf32_arm_final_link_relocate): Use + UNDEFWEAK_NO_DYNAMIC_RELOC. + (allocate_dynrelocs_for_symbol): Likewise. +--- + +diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c +index cce796d..21cf4b0 100644 +--- a/bfd/elf32-arm.c ++++ b/bfd/elf32-arm.c +@@ -11572,8 +11572,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, + if (dynreloc_st_type == STT_GNU_IFUNC) + outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE); + else if (bfd_link_pic (info) +- && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT +- || h->root.type != bfd_link_hash_undefweak)) ++ && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)) + outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE); + else + { +@@ -16527,8 +16526,7 @@ allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf) + GOT entry's R_ARM_IRELATIVE relocation. */ + elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1); + else if (bfd_link_pic (info) +- && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT +- || h->root.type != bfd_link_hash_undefweak)) ++ && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)) + /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */ + elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1); + else if (htab->fdpic_p && tls_type == GOT_NORMAL) diff --git a/patches/binutils-2.33.1/0001-j2.diff b/patches/binutils-2.33.1/0001-j2.diff new file mode 100644 index 0000000..f08140e --- /dev/null +++ b/patches/binutils-2.33.1/0001-j2.diff @@ -0,0 +1,620 @@ +diff -ur binutils-2.32.orig/bfd/archures.c binutils-2.32/bfd/archures.c +--- binutils-2.32.orig/bfd/archures.c 2019-01-19 11:01:32.000000000 -0500 ++++ binutils-2.32/bfd/archures.c 2019-05-26 15:09:15.968501965 -0400 +@@ -298,6 +298,8 @@ + .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + .#define bfd_mach_sh2a_or_sh4 0x2a3 + .#define bfd_mach_sh2a_or_sh3e 0x2a4 ++.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 ++.#define bfd_mach_shj2 0x2c + .#define bfd_mach_sh2e 0x2e + .#define bfd_mach_sh3 0x30 + .#define bfd_mach_sh3_nommu 0x31 +Only in binutils-2.32/bfd: archures.c.orig +Only in binutils-2.32/bfd: archures.c.rej +diff -ur binutils-2.32.orig/bfd/bfd-in2.h binutils-2.32/bfd/bfd-in2.h +--- binutils-2.32.orig/bfd/bfd-in2.h 2019-01-19 11:01:32.000000000 -0500 ++++ binutils-2.32/bfd/bfd-in2.h 2019-05-26 15:10:21.005775819 -0400 +@@ -2197,6 +2197,8 @@ + #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2 + #define bfd_mach_sh2a_or_sh4 0x2a3 + #define bfd_mach_sh2a_or_sh3e 0x2a4 ++#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5 ++#define bfd_mach_shj2 0x2c + #define bfd_mach_sh2e 0x2e + #define bfd_mach_sh3 0x30 + #define bfd_mach_sh3_nommu 0x31 +Only in binutils-2.32/bfd: bfd-in2.h.orig +Only in binutils-2.32/bfd: bfd-in2.h.rej +diff -ur binutils-2.32.orig/bfd/cpu-sh.c binutils-2.32/bfd/cpu-sh.c +--- binutils-2.32.orig/bfd/cpu-sh.c 2019-01-19 11:01:32.000000000 -0500 ++++ binutils-2.32/bfd/cpu-sh.c 2019-05-26 15:13:00.461455381 -0400 +@@ -43,7 +43,10 @@ + #define SH2A_NOFPU_OR_SH4_NOMMU_NOFPU_NEXT arch_info_struct + 16 + #define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17 + #define SH2A_OR_SH4_NEXT arch_info_struct + 18 +-#define SH2A_OR_SH3E_NEXT NULL ++#define SH2A_OR_SH3E_NEXT arch_info_struct + 19 ++#define SHJ2_NEXT arch_info_struct + 20 ++#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT NULL ++ + + static const bfd_arch_info_type arch_info_struct[] = + { +@@ -332,6 +335,36 @@ + bfd_arch_default_fill, + SH2A_OR_SH3E_NEXT + }, ++ { ++ 32, /* 32 bits in a word. */ ++ 32, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_sh, ++ bfd_mach_shj2, ++ "sh", /* Architecture name. . */ ++ "j2", /* Machine name. */ ++ 1, ++ FALSE, /* Not the default. */ ++ bfd_default_compatible, ++ bfd_default_scan, ++ bfd_arch_default_fill, ++ SHJ2_NEXT ++ }, ++ { ++ 32, /* 32 bits in a word. */ ++ 32, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_sh, ++ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, ++ "sh", /* Architecture name. . */ ++ "sh2a-or-sh3e-or-j2", /* Machine name. */ ++ 1, ++ FALSE, /* Not the default. */ ++ bfd_default_compatible, ++ bfd_default_scan, ++ bfd_arch_default_fill, ++ SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT ++ }, + }; + + const bfd_arch_info_type bfd_sh_arch = +@@ -382,6 +415,8 @@ + { bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up }, + { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up }, + { bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up }, ++ { bfd_mach_shj2, arch_shj2, arch_shj2_up }, ++ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up }, + { 0, 0, 0 } /* Terminator. */ + }; + +Only in binutils-2.32/bfd: cpu-sh.c.orig +Only in binutils-2.32/bfd: cpu-sh.c.rej +diff -ur binutils-2.32.orig/binutils/readelf.c binutils-2.32/binutils/readelf.c +--- binutils-2.32.orig/binutils/readelf.c 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/binutils/readelf.c 2019-05-26 15:07:03.563950564 -0400 +@@ -3528,6 +3528,8 @@ + case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break; + case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break; + case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break; ++ case EF_SHJ2: strcat (buf, ", j2"); break; ++ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break; + default: strcat (buf, _(", unknown ISA")); break; + } + +Only in binutils-2.32/binutils: readelf.c.orig +diff -ur binutils-2.32.orig/gas/config/tc-sh.c binutils-2.32/gas/config/tc-sh.c +--- binutils-2.32.orig/gas/config/tc-sh.c 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/config/tc-sh.c 2019-05-26 15:07:03.567950581 -0400 +@@ -1251,6 +1251,8 @@ + ptr++; + } + get_operand (&ptr, operand + 2); ++ if (strcmp (info->name,"cas") == 0) ++ operand[2].type = A_IND_0; + } + else + { +@@ -1790,7 +1792,10 @@ + goto fail; + reg_m = 4; + break; +- ++ case A_IND_0: ++ if (user->reg != 0) ++ goto fail; ++ break; + default: + printf (_("unhandled %d\n"), arg); + goto fail; +Only in binutils-2.32/gas/config: tc-sh.c.orig +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2019-05-26 15:07:03.568950585 -0400 +@@ -12,8 +12,6 @@ + sh2a_nofpu_or_sh3_nommu: + ! Instructions introduced into sh2a-nofpu-or-sh3-nommu + pref @r4 ;!/* 0000nnnn10000011 pref @ */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + + ! Instructions inherited from ancestors: sh sh2 + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2019-05-26 15:07:03.570950593 -0400 +@@ -12,7 +12,7 @@ + sh2a_nofpu_or_sh4_nommu_nofpu: + ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -119,8 +119,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2019-05-26 15:07:03.571950597 -0400 +@@ -64,7 +64,7 @@ + movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(,), */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} + movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(,), */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -171,8 +171,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2019-05-26 15:07:03.572950601 -0400 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh2a-or-sh3e + fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -124,8 +124,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2019-05-26 15:07:03.574950610 -0400 +@@ -39,7 +39,7 @@ + fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub ,*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} + ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc ,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -150,8 +150,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a.s 2019-05-26 15:07:03.575950614 -0400 +@@ -16,7 +16,7 @@ + fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s ,@(,) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32} + fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(,), */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -140,8 +140,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3-dsp.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3-dsp.s 2019-05-26 15:07:03.577950622 -0400 +@@ -12,7 +12,7 @@ + sh3_dsp: + ! Instructions introduced into sh3-dsp + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -152,8 +152,8 @@ + setrc #4 ;!/* 10000010i8*1.... setrc # */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3-nommu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3-nommu.s 2019-05-26 15:07:03.578950626 -0400 +@@ -26,7 +26,7 @@ + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@- */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@- */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -133,8 +133,8 @@ + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3.s 2019-05-26 15:07:03.579950630 -0400 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh3 + ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -128,8 +128,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3e.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3e.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3e.s 2019-05-26 15:07:03.581950639 -0400 +@@ -12,7 +12,7 @@ + sh3e: + ! Instructions introduced into sh3e + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -132,8 +132,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nofpu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2019-05-26 15:07:03.582950643 -0400 +@@ -12,7 +12,7 @@ + sh4_nofpu: + ! Instructions introduced into sh4-nofpu + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -136,8 +136,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2019-05-26 15:07:03.583950647 -0400 +@@ -24,7 +24,7 @@ + stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@- */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@- */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -139,8 +139,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4.s 2019-05-26 15:07:03.585950655 -0400 +@@ -17,7 +17,7 @@ + fsrra fr1 ;!/* 1111nnnn01111101 fsrra */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up} + ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -145,8 +145,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4a-nofpu.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2019-05-26 15:07:03.586950659 -0400 +@@ -19,7 +19,7 @@ + prefi @r4 ;!/* 0000nnnn11010011 prefi @ */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} + synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -143,8 +143,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4a.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4a.s 2019-05-26 15:07:03.588950668 -0400 +@@ -13,7 +13,7 @@ + ! Instructions introduced into sh4a + fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up} + +-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -147,8 +147,8 @@ + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4al-dsp.s +--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2019-05-26 15:07:03.589950672 -0400 +@@ -48,7 +48,7 @@ + dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap , */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up} + dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap , */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up} + +-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu ++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #, */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add , */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc ,*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} +@@ -202,8 +202,8 @@ + setrc #4 ;!/* 10000010i8*1.... setrc # */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} +- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} +- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} ++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up} + shal r4 ;!/* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} +diff -ur binutils-2.32.orig/include/elf/sh.h binutils-2.32/include/elf/sh.h +--- binutils-2.32.orig/include/elf/sh.h 2019-01-19 11:01:33.000000000 -0500 ++++ binutils-2.32/include/elf/sh.h 2019-05-26 15:07:03.590950676 -0400 +@@ -39,6 +39,7 @@ + #define EF_SH2E 11 + #define EF_SH4A 12 + #define EF_SH2A 13 ++#define EF_SHJ2 14 + + #define EF_SH4_NOFPU 16 + #define EF_SH4A_NOFPU 17 +@@ -50,6 +51,7 @@ + #define EF_SH2A_SH3_NOFPU 22 + #define EF_SH2A_SH4 23 + #define EF_SH2A_SH3E 24 ++#define EF_SH2A_SH3_SHJ2 25 + + /* This one can only mix in objects from other EF_SH5 objects. */ + #define EF_SH5 10 +@@ -72,7 +74,8 @@ + /* EF_SH2E */ bfd_mach_sh2e , \ + /* EF_SH4A */ bfd_mach_sh4a , \ + /* EF_SH2A */ bfd_mach_sh2a , \ +-/* 14, 15 */ 0, 0, \ ++/* EF_SHJ2 */ bfd_mach_shj2 , \ ++/* 15 */ 0, \ + /* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \ + /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \ + /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \ +@@ -81,7 +84,8 @@ + /* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \ + /* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \ + /* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \ +-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e ++/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \ ++/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu + + /* Convert arch_sh* into EF_SH*. */ + int sh_find_elf_flags (unsigned int arch_set); +diff -ur binutils-2.32.orig/opcodes/sh-dis.c binutils-2.32/opcodes/sh-dis.c +--- binutils-2.32.orig/opcodes/sh-dis.c 2019-01-19 11:01:34.000000000 -0500 ++++ binutils-2.32/opcodes/sh-dis.c 2019-05-26 15:07:03.593950688 -0400 +@@ -856,6 +856,9 @@ + case XMTRX_M4: + fprintf_fn (stream, "xmtrx"); + break; ++ case A_IND_0: ++ fprintf_fn (stream, "@r0"); ++ break; + default: + abort (); + } +Only in binutils-2.32/opcodes: sh-dis.c.orig +diff -ur binutils-2.32.orig/opcodes/sh-opc.h binutils-2.32/opcodes/sh-opc.h +--- binutils-2.32.orig/opcodes/sh-opc.h 2019-01-19 11:01:34.000000000 -0500 ++++ binutils-2.32/opcodes/sh-opc.h 2019-05-26 15:07:03.597950705 -0400 +@@ -191,7 +191,8 @@ + FPUL_N, + FPUL_M, + FPSCR_N, +- FPSCR_M ++ FPSCR_M, ++ A_IND_0 + } + sh_arg_type; + +@@ -215,9 +216,11 @@ + #define arch_sh4_base (1 << 5) + #define arch_sh4a_base (1 << 6) + #define arch_sh2a_base (1 << 7) +-#define arch_sh_base_mask MASK (0, 7) ++#define arch_shj2_base (1 << 8) ++#define arch_sh2a_sh3_shj2_base (1 << 9) ++#define arch_sh_base_mask MASK (0, 9) + +-/* Bits 8 ... 24 are currently free. */ ++/* Bits 10 ... 24 are currently free. */ + + /* This is an annotation on instruction types, but we + abuse the arch field in instructions to denote it. */ +@@ -255,6 +258,8 @@ + #define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co) + #define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu) + #define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu) ++#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co) + + #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2)) + #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0) +@@ -319,7 +324,8 @@ + #define arch_sh2_up (arch_sh2 \ + | arch_sh2e_up \ + | arch_sh2a_nofpu_or_sh3_nommu_up \ +- | arch_sh_dsp_up) ++ | arch_sh_dsp_up \ ++ | arch_shj2_up) + #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \ + | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ + | arch_sh2a_or_sh3e_up \ +@@ -345,6 +351,12 @@ + #define arch_sh4a_nofpu_up (arch_sh4a_nofpu \ + | arch_sh4a_up \ + | arch_sh4al_dsp_up) ++#define arch_shj2_up ( arch_shj2) ++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \ ++ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \ ++ | arch_sh2a_or_sh3e_up \ ++ | arch_sh3_nommu_up \ ++ | arch_shj2_up) + + /* Right branches. */ + #define arch_sh2e_up (arch_sh2e \ +@@ -713,9 +725,9 @@ + + /* repeat start end # */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}, + +-/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1100 shad ,*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + +-/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}, ++/* 0100nnnnmmmm1101 shld ,*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up}, + + /* 0100nnnn00100000 shal */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}, + +@@ -1193,7 +1205,7 @@ + {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}, + /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(,), */ + {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}, +- ++ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up}, + { 0, {0}, {0}, 0 } + }; + +Only in binutils-2.32/opcodes: sh-opc.h.orig diff --git a/patches/binutils-2.33.1/0002-or1k-32bithost-1.diff b/patches/binutils-2.33.1/0002-or1k-32bithost-1.diff new file mode 100644 index 0000000..90cc09d --- /dev/null +++ b/patches/binutils-2.33.1/0002-or1k-32bithost-1.diff @@ -0,0 +1,249 @@ +From: Stafford Horne +To: GNU Binutils +Cc: Openrisc , dalias@libc.org, Stafford Horne +Subject: [PATCH 1/2] or1k: Remove 64-bit support, it's not used and it breaks 32-bit hosts +Date: Wed, 11 Dec 2019 06:49:05 +0900 + +Reported by Rich Felker when building on 32-bit hosts. Backwards jump +negative offsets were not calculated correctly due to improper 32-bit +to 64-bit zero-extension. The 64-bit fields are present because we +are mixing 32-bit and 64-bit architectures in our cpu descriptions. + +Removing 64-bit fixes the issue. We don't use 64-bit, there is an architecture +spec for 64-bit but no implementations or simulators. My thought is if +we need them in the future we should do the proper work to support both +32-bit and 64-bit implementations co-existing then. + +cpu/ChangeLog: + +yyyy-mm-dd Stafford Horne + + PR 25184 + * or1k.cpu (arch or1k): Remove or64 and or64nd machs. + (ORBIS-MACHS, ORFPX32-MACHS): Remove pmacros. + (cpu or1k64bf, mach or64, mach or64nd): Remove definitions. + * or1kcommon.cpu (h-fdr): Remove hardware. + * or1korfpx.cpu (rDDF, rADF, rBDF): Remove operand definitions. + (float-regreg-insn): Remove lf- mnemonic -d instruction pattern. + (float-setflag-insn-base): Remove lf-sf mnemonic -d pattern. + (float-cust-insn): Remove "lf-cust" cust-num "-d" pattern. + (lf-rem-d, lf-itof-d, lf-ftoi-d, lf-madd-d): Remove. +--- + cpu/or1k.cpu | 35 +++---------------------- + cpu/or1kcommon.cpu | 14 ---------- + cpu/or1korfpx.cpu | 64 ---------------------------------------------- + 3 files changed, 3 insertions(+), 110 deletions(-) + +diff --git a/cpu/or1k.cpu b/cpu/or1k.cpu +index b796862d1b..9784f7a0fa 100644 +--- a/cpu/or1k.cpu ++++ b/cpu/or1k.cpu +@@ -31,7 +31,7 @@ + (comment "OpenRISC 1000") + (default-alignment aligned) + (insn-lsb0? #t) +- (machs or32 or32nd or64 or64nd) ++ (machs or32 or32nd) + (isas openrisc) + ) + +@@ -44,10 +44,8 @@ + ) + + (define-pmacro OR32-MACHS or32,or32nd) +-(define-pmacro OR64-MACHS or64,or64nd) +-(define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd) +-(define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd) +-(define-pmacro ORFPX64-MACHS or64,or64nd) ++(define-pmacro ORBIS-MACHS or32,or32nd) ++(define-pmacro ORFPX32-MACHS or32,or32nd) + (define-pmacro ORFPX64A32-MACHS or32,or32nd) ; float64 for 32-bit machs + + (define-attr +@@ -100,33 +98,6 @@ + ) + ) + +-(if (keep-mach? (or64 or64nd)) +- (begin +- (define-cpu +- (name or1k64bf) +- (comment "OpenRISC 1000 64-bit CPU family") +- (insn-endian big) +- (data-endian big) +- (word-bitsize 64) +- (file-transform "64") +- ) +- +- (define-mach +- (name or64) +- (comment "Generic OpenRISC 1000 64-bit CPU") +- (cpu or1k64bf) +- (bfd-name "or1k64") +- ) +- +- (define-mach +- (name or64nd) +- (comment "Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot") +- (cpu or1k64bf) +- (bfd-name "or1k64nd") +- ) +- ) +- ) +- + (include "or1kcommon.cpu") + (include "or1korbis.cpu") + (include "or1korfpx.cpu") +diff --git a/cpu/or1kcommon.cpu b/cpu/or1kcommon.cpu +index 65154407df..9f102c93a1 100644 +--- a/cpu/or1kcommon.cpu ++++ b/cpu/or1kcommon.cpu +@@ -114,20 +114,6 @@ + (set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0)))) + ) + +-; +-; Hardware: virtual registerts for FPU (double precision) +-; mapped to GPRs +-; +-(define-hardware +- (name h-fdr) +- (comment "or64 floating point registers (double, virtual)") +- (attrs VIRTUAL (MACH ORFPX64-MACHS)) +- (type register DF (32)) +- (indices keyword "" REG-INDICES) +- (get (index) (subword DF (trunc DI (reg h-gpr index)) 0)) +- (set (index newval) (set UDI (reg h-gpr index) (zext UDI (subword DI newval 0)))) +- ) +- + ; + ; Register pairs are offset by 2 for registers r16 and above. This is to + ; be able to allow registers to be call saved in GCC across function calls. +diff --git a/cpu/or1korfpx.cpu b/cpu/or1korfpx.cpu +index f43522f2e6..0bd469cff5 100644 +--- a/cpu/or1korfpx.cpu ++++ b/cpu/or1korfpx.cpu +@@ -84,10 +84,6 @@ + (dnop rASF "source register A (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r2) + (dnop rBSF "source register B (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r3) + +-(dnop rDDF "or64 destination register (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1) +-(dnop rADF "or64 source register A (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r2) +-(dnop rBDF "or64 source register B (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r3) +- + (define-pmacro (double-field-and-ops mnemonic reg offbit op-comment) + (begin + (define-multi-ifield +@@ -152,14 +148,6 @@ + (set SF rDSF (mnemonic SF rASF rBSF)) + () + ) +- (dni (.sym lf- mnemonic -d) +- (.str "lf." mnemonic ".d reg/reg/reg") +- ((MACH ORFPX64-MACHS)) +- (.str "lf." mnemonic ".d $rDDF,$rADF,$rBDF") +- (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D)) +- (set DF rDDF (mnemonic DF rADF rBDF)) +- () +- ) + (dni (.sym lf- mnemonic -d32) + (.str "lf." mnemonic ".d regpair/regpair/regpair") + ((MACH ORFPX64A32-MACHS)) +@@ -185,15 +173,6 @@ + () + ) + +-(dni lf-rem-d +- "lf.rem.d reg/reg/reg" +- ((MACH ORFPX64-MACHS)) +- "lf.rem.d $rDDF,$rADF,$rBDF" +- (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_D) +- (set DF rDDF (rem DF rADF rBDF)) +- () +- ) +- + (dni lf-rem-d32 + "lf.rem.d regpair/regpair/regpair" + ((MACH ORFPX64A32-MACHS)) +@@ -221,15 +200,6 @@ + () + ) + +-(dni lf-itof-d +- "lf.itof.d reg/reg" +- ((MACH ORFPX64-MACHS)) +- "lf.itof.d $rDDF,$rA" +- (+ OPC_FLOAT rDDF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D) +- (set DF rDDF (float DF (get-rounding-mode) rA)) +- () +- ) +- + (dni lf-itof-d32 + "lf.itof.d regpair/regpair" + ((MACH ORFPX64A32-MACHS)) +@@ -248,15 +218,6 @@ + () + ) + +-(dni lf-ftoi-d +- "lf.ftoi.d reg/reg" +- ((MACH ORFPX64-MACHS)) +- "lf.ftoi.d $rD,$rADF" +- (+ OPC_FLOAT rD rADF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_D) +- (set WI rD (fix WI (get-rounding-mode) rADF)) +- () +- ) +- + (dni lf-ftoi-d32 + "lf.ftoi.d regpair/regpair" + ((MACH ORFPX64A32-MACHS)) +@@ -276,14 +237,6 @@ + (symantics rtx-mnemonic SF rASF rBSF) + () + ) +- (dni (.sym lf-sf mnemonic -d) +- (.str "lf.sf" mnemonic ".d reg/reg") +- ((MACH ORFPX64-MACHS)) +- (.str "lf.sf" mnemonic ".d $rADF,$rBDF") +- (+ OPC_FLOAT (f-r1 0) rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D)) +- (symantics rtx-mnemonic DF rADF rBDF) +- () +- ) + (dni (.sym lf-sf mnemonic -d32) + (.str "lf.sf" mnemonic ".d regpair/regpair") + ((MACH ORFPX64A32-MACHS)) +@@ -336,15 +289,6 @@ + () + ) + +-(dni lf-madd-d +- "lf.madd.d reg/reg/reg" +- ((MACH ORFPX64-MACHS)) +- "lf.madd.d $rDDF,$rADF,$rBDF" +- (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_D) +- (set DF rDDF (add DF (mul DF rADF rBDF) rDDF)) +- () +- ) +- + (dni lf-madd-d32 + "lf.madd.d regpair/regpair/regpair" + ((MACH ORFPX64A32-MACHS)) +@@ -364,14 +308,6 @@ + (nop) + () + ) +- (dni (.sym "lf-cust" cust-num "-d") +- (.str "lf.cust" cust-num ".d") +- ((MACH ORFPX64-MACHS)) +- (.str "lf.cust" cust-num ".d") +- (+ OPC_FLOAT (f-resv-25-5 0) rADF rBDF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D")) +- (nop) +- () +- ) + (dni (.sym "lf-cust" cust-num "-d32") + (.str "lf.cust" cust-num ".d") + ((MACH ORFPX64A32-MACHS)) +-- +2.21.0 + + diff --git a/patches/binutils-2.33.1/0003-or1k-32bithost-2.diff b/patches/binutils-2.33.1/0003-or1k-32bithost-2.diff new file mode 100644 index 0000000..7716879 --- /dev/null +++ b/patches/binutils-2.33.1/0003-or1k-32bithost-2.diff @@ -0,0 +1,4308 @@ +From: Stafford Horne +To: GNU Binutils +Cc: Openrisc , dalias@libc.org, Stafford Horne +Subject: [PATCH 2/2] or1k: Regnerate opcode files after removing 64-bit support +Date: Wed, 11 Dec 2019 06:49:06 +0900 + +opcodes/ChangeLog: + +yyyy-mm-dd Stafford Horne + + * or1k-asm.c: Regenerate. + * or1k-desc.c: Regenerate. + * or1k-desc.h: Regenerate. + * or1k-dis.c: Regenerate. + * or1k-ibld.c: Regenerate. + * or1k-opc.c: Regenerate. + * or1k-opc.h: Regenerate. + * or1k-opinst.c: Regenerate. +--- + opcodes/or1k-asm.c | 9 - + opcodes/or1k-desc.c | 1811 +++++++++++++++++++---------------------- + opcodes/or1k-desc.h | 332 ++++---- + opcodes/or1k-dis.c | 9 - + opcodes/or1k-ibld.c | 60 +- + opcodes/or1k-opc.c | 152 ---- + opcodes/or1k-opc.h | 28 +- + opcodes/or1k-opinst.c | 428 +++++----- + 8 files changed, 1182 insertions(+), 1647 deletions(-) + +diff --git a/opcodes/or1k-asm.c b/opcodes/or1k-asm.c +index 55668afee5..11f25868bb 100644 +--- a/opcodes/or1k-asm.c ++++ b/opcodes/or1k-asm.c +@@ -519,9 +519,6 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd, + case OR1K_OPERAND_RAD32F : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RAD32F, (unsigned long *) (& fields->f_rad32)); + break; +- case OR1K_OPERAND_RADF : +- errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r2); +- break; + case OR1K_OPERAND_RADI : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RADI, (unsigned long *) (& fields->f_rad32)); + break; +@@ -534,9 +531,6 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd, + case OR1K_OPERAND_RBD32F : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RBD32F, (unsigned long *) (& fields->f_rbd32)); + break; +- case OR1K_OPERAND_RBDF : +- errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r3); +- break; + case OR1K_OPERAND_RBDI : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RBDI, (unsigned long *) (& fields->f_rbd32)); + break; +@@ -549,9 +543,6 @@ or1k_cgen_parse_operand (CGEN_CPU_DESC cd, + case OR1K_OPERAND_RDD32F : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RDD32F, (unsigned long *) (& fields->f_rdd32)); + break; +- case OR1K_OPERAND_RDDF : +- errmsg = cgen_parse_keyword (cd, strp, & or1k_cgen_opval_h_fdr, & fields->f_r1); +- break; + case OR1K_OPERAND_RDDI : + errmsg = parse_regpair (cd, strp, OR1K_OPERAND_RDDI, (unsigned long *) (& fields->f_rdd32)); + break; +diff --git a/opcodes/or1k-desc.c b/opcodes/or1k-desc.c +index 3357849a27..10158cd076 100644 +--- a/opcodes/or1k-desc.c ++++ b/opcodes/or1k-desc.c +@@ -49,8 +49,6 @@ static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = + { "base", MACH_BASE }, + { "or32", MACH_OR32 }, + { "or32nd", MACH_OR32ND }, +- { "or64", MACH_OR64 }, +- { "or64nd", MACH_OR64ND }, + { "max", MACH_MAX }, + { 0, 0 } + }; +@@ -129,8 +127,6 @@ static const CGEN_ISA or1k_cgen_isa_table[] = { + static const CGEN_MACH or1k_cgen_mach_table[] = { + { "or32", "or1k", MACH_OR32, 0 }, + { "or32nd", "or1knd", MACH_OR32ND, 0 }, +- { "or64", "or1k64", MACH_OR64, 0 }, +- { "or64nd", "or1k64nd", MACH_OR64ND, 0 }, + { 0, 0, 0, 0 } + }; + +@@ -226,52 +222,6 @@ CGEN_KEYWORD or1k_cgen_opval_h_fsr = + 0, 0, 0, 0, "" + }; + +-static CGEN_KEYWORD_ENTRY or1k_cgen_opval_h_fdr_entries[] = +-{ +- { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, +- { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, +- { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, +- { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, +- { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, +- { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, +- { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, +- { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, +- { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, +- { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, +- { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, +- { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, +- { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, +- { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, +- { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, +- { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, +- { "r16", 16, {0, {{{0, 0}}}}, 0, 0 }, +- { "r17", 17, {0, {{{0, 0}}}}, 0, 0 }, +- { "r18", 18, {0, {{{0, 0}}}}, 0, 0 }, +- { "r19", 19, {0, {{{0, 0}}}}, 0, 0 }, +- { "r20", 20, {0, {{{0, 0}}}}, 0, 0 }, +- { "r21", 21, {0, {{{0, 0}}}}, 0, 0 }, +- { "r22", 22, {0, {{{0, 0}}}}, 0, 0 }, +- { "r23", 23, {0, {{{0, 0}}}}, 0, 0 }, +- { "r24", 24, {0, {{{0, 0}}}}, 0, 0 }, +- { "r25", 25, {0, {{{0, 0}}}}, 0, 0 }, +- { "r26", 26, {0, {{{0, 0}}}}, 0, 0 }, +- { "r27", 27, {0, {{{0, 0}}}}, 0, 0 }, +- { "r28", 28, {0, {{{0, 0}}}}, 0, 0 }, +- { "r29", 29, {0, {{{0, 0}}}}, 0, 0 }, +- { "r30", 30, {0, {{{0, 0}}}}, 0, 0 }, +- { "r31", 31, {0, {{{0, 0}}}}, 0, 0 }, +- { "lr", 9, {0, {{{0, 0}}}}, 0, 0 }, +- { "sp", 1, {0, {{{0, 0}}}}, 0, 0 }, +- { "fp", 2, {0, {{{0, 0}}}}, 0, 0 } +-}; +- +-CGEN_KEYWORD or1k_cgen_opval_h_fdr = +-{ +- & or1k_cgen_opval_h_fdr_entries[0], +- 35, +- 0, 0, 0, 0, "" +-}; +- + + /* The hardware table. */ + +@@ -284,642 +234,641 @@ const CGEN_HW_ENTRY or1k_cgen_hw_table[] = + { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<f_rad32, 0|(1<f_r2, 0); +- break; + case OR1K_OPERAND_RADI : + print_regpair (cd, info, fields->f_rad32, 0|(1<f_rbd32, 0|(1<f_r3, 0); +- break; + case OR1K_OPERAND_RBDI : + print_regpair (cd, info, fields->f_rbd32, 0|(1<f_rdd32, 0|(1<f_r1, 0); +- break; + case OR1K_OPERAND_RDDI : + print_regpair (cd, info, fields->f_rdd32, 0|(1<f_disp21; +- value = ((((DI) (value) >> (13))) - (((DI) (pc) >> (13)))); ++ value = ((((SI) (value) >> (13))) - (((SI) (pc) >> (13)))); + errmsg = insert_normal (cd, value, 0|(1<f_disp26; +- value = ((DI) (((value) - (pc))) >> (2)); ++ value = ((SI) (((value) - (pc))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_r2, 0, 0, 20, 5, 32, total_length, buffer); +- break; + case OR1K_OPERAND_RADI : + { + { +@@ -641,9 +638,6 @@ or1k_cgen_insert_operand (CGEN_CPU_DESC cd, + break; + } + break; +- case OR1K_OPERAND_RBDF : +- errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); +- break; + case OR1K_OPERAND_RBDI : + { + { +@@ -678,9 +672,6 @@ or1k_cgen_insert_operand (CGEN_CPU_DESC cd, + break; + } + break; +- case OR1K_OPERAND_RDDF : +- errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); +- break; + case OR1K_OPERAND_RDDI : + { + { +@@ -783,7 +774,7 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd, + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<> (13))))) << (13)); ++ value = ((((value) + (((SI) (pc) >> (13))))) << (13)); + fields->f_disp21 = value; + } + break; +@@ -807,9 +798,6 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd, + FLD (f_rad32) = ((FLD (f_r2)) | (((FLD (f_raoff_9_1)) << (5)))); + } + break; +- case OR1K_OPERAND_RADF : +- length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); +- break; + case OR1K_OPERAND_RADI : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); +@@ -834,9 +822,6 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd, + FLD (f_rbd32) = ((FLD (f_r3)) | (((FLD (f_rboff_8_1)) << (5)))); + } + break; +- case OR1K_OPERAND_RBDF : +- length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); +- break; + case OR1K_OPERAND_RBDI : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); +@@ -861,9 +846,6 @@ or1k_cgen_extract_operand (CGEN_CPU_DESC cd, + FLD (f_rdd32) = ((FLD (f_r1)) | (((FLD (f_rdoff_10_1)) << (5)))); + } + break; +- case OR1K_OPERAND_RDDF : +- length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); +- break; + case OR1K_OPERAND_RDDI : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); +@@ -954,9 +936,6 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RAD32F : + value = fields->f_rad32; + break; +- case OR1K_OPERAND_RADF : +- value = fields->f_r2; +- break; + case OR1K_OPERAND_RADI : + value = fields->f_rad32; + break; +@@ -969,9 +948,6 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RBD32F : + value = fields->f_rbd32; + break; +- case OR1K_OPERAND_RBDF : +- value = fields->f_r3; +- break; + case OR1K_OPERAND_RBDI : + value = fields->f_rbd32; + break; +@@ -984,9 +960,6 @@ or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RDD32F : + value = fields->f_rdd32; + break; +- case OR1K_OPERAND_RDDF : +- value = fields->f_r1; +- break; + case OR1K_OPERAND_RDDI : + value = fields->f_rdd32; + break; +@@ -1041,9 +1014,6 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RAD32F : + value = fields->f_rad32; + break; +- case OR1K_OPERAND_RADF : +- value = fields->f_r2; +- break; + case OR1K_OPERAND_RADI : + value = fields->f_rad32; + break; +@@ -1056,9 +1026,6 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RBD32F : + value = fields->f_rbd32; + break; +- case OR1K_OPERAND_RBDF : +- value = fields->f_r3; +- break; + case OR1K_OPERAND_RBDI : + value = fields->f_rbd32; + break; +@@ -1071,9 +1038,6 @@ or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RDD32F : + value = fields->f_rdd32; + break; +- case OR1K_OPERAND_RDDF : +- value = fields->f_r1; +- break; + case OR1K_OPERAND_RDDI : + value = fields->f_rdd32; + break; +@@ -1135,9 +1099,6 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RAD32F : + fields->f_rad32 = value; + break; +- case OR1K_OPERAND_RADF : +- fields->f_r2 = value; +- break; + case OR1K_OPERAND_RADI : + fields->f_rad32 = value; + break; +@@ -1150,9 +1111,6 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RBD32F : + fields->f_rbd32 = value; + break; +- case OR1K_OPERAND_RBDF : +- fields->f_r3 = value; +- break; + case OR1K_OPERAND_RBDI : + fields->f_rbd32 = value; + break; +@@ -1165,9 +1123,6 @@ or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RDD32F : + fields->f_rdd32 = value; + break; +- case OR1K_OPERAND_RDDF : +- fields->f_r1 = value; +- break; + case OR1K_OPERAND_RDDI : + fields->f_rdd32 = value; + break; +@@ -1219,9 +1174,6 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RAD32F : + fields->f_rad32 = value; + break; +- case OR1K_OPERAND_RADF : +- fields->f_r2 = value; +- break; + case OR1K_OPERAND_RADI : + fields->f_rad32 = value; + break; +@@ -1234,9 +1186,6 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RBD32F : + fields->f_rbd32 = value; + break; +- case OR1K_OPERAND_RBDF : +- fields->f_r3 = value; +- break; + case OR1K_OPERAND_RBDI : + fields->f_rbd32 = value; + break; +@@ -1249,9 +1198,6 @@ or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + case OR1K_OPERAND_RDD32F : + fields->f_rdd32 = value; + break; +- case OR1K_OPERAND_RDDF : +- fields->f_r1 = value; +- break; + case OR1K_OPERAND_RDDI : + fields->f_rdd32 = value; + break; +diff --git a/opcodes/or1k-opc.c b/opcodes/or1k-opc.c +index 86e421099a..c390f85e52 100644 +--- a/opcodes/or1k-opc.c ++++ b/opcodes/or1k-opc.c +@@ -163,10 +163,6 @@ static const CGEN_IFMT ifmt_lf_add_s ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } + }; + +-static const CGEN_IFMT ifmt_lf_add_d ATTRIBUTE_UNUSED = { +- 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } +-}; +- + static const CGEN_IFMT ifmt_lf_add_d32 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0000ff, { { F (F_OPCODE) }, { F (F_RDD32) }, { F (F_RAD32) }, { F (F_RBD32) }, { F (F_OP_7_8) }, { 0 } } + }; +@@ -175,10 +171,6 @@ static const CGEN_IFMT ifmt_lf_itof_s ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } + }; + +-static const CGEN_IFMT ifmt_lf_itof_d ATTRIBUTE_UNUSED = { +- 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } +-}; +- + static const CGEN_IFMT ifmt_lf_itof_d32 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00f9ff, { { F (F_OPCODE) }, { F (F_R3) }, { F (F_RDD32) }, { F (F_RAD32) }, { F (F_RESV_8_1) }, { F (F_OP_7_8) }, { 0 } } + }; +@@ -187,10 +179,6 @@ static const CGEN_IFMT ifmt_lf_ftoi_s ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } + }; + +-static const CGEN_IFMT ifmt_lf_ftoi_d ATTRIBUTE_UNUSED = { +- 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } +-}; +- + static const CGEN_IFMT ifmt_lf_ftoi_d32 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc00f9ff, { { F (F_OPCODE) }, { F (F_R3) }, { F (F_RDD32) }, { F (F_RAD32) }, { F (F_RESV_8_1) }, { F (F_OP_7_8) }, { 0 } } + }; +@@ -199,10 +187,6 @@ static const CGEN_IFMT ifmt_lf_sfeq_s ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } + }; + +-static const CGEN_IFMT ifmt_lf_sfeq_d ATTRIBUTE_UNUSED = { +- 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } +-}; +- + static const CGEN_IFMT ifmt_lf_sfeq_d32 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe004ff, { { F (F_OPCODE) }, { F (F_R1) }, { F (F_RESV_10_1) }, { F (F_RAD32) }, { F (F_RBD32) }, { F (F_OP_7_8) }, { 0 } } + }; +@@ -211,10 +195,6 @@ static const CGEN_IFMT ifmt_lf_cust1_s ATTRIBUTE_UNUSED = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } + }; + +-static const CGEN_IFMT ifmt_lf_cust1_d ATTRIBUTE_UNUSED = { +- 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_R2) }, { F (F_R3) }, { F (F_RESV_10_3) }, { F (F_OP_7_8) }, { 0 } } +-}; +- + static const CGEN_IFMT ifmt_lf_cust1_d32 ATTRIBUTE_UNUSED = { + 32, 32, 0xffe004ff, { { F (F_OPCODE) }, { F (F_RESV_25_5) }, { F (F_RESV_10_1) }, { F (F_RAD32) }, { F (F_RBD32) }, { F (F_OP_7_8) }, { 0 } } + }; +@@ -828,12 +808,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_add_s, { 0xc8000000 } + }, +-/* lf.add.d $rDDF,$rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_add_d, { 0xc8000010 } +- }, + /* lf.add.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -846,12 +820,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_add_s, { 0xc8000001 } + }, +-/* lf.sub.d $rDDF,$rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_add_d, { 0xc8000011 } +- }, + /* lf.sub.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -864,12 +832,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_add_s, { 0xc8000002 } + }, +-/* lf.mul.d $rDDF,$rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_add_d, { 0xc8000012 } +- }, + /* lf.mul.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -882,12 +844,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_add_s, { 0xc8000003 } + }, +-/* lf.div.d $rDDF,$rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_add_d, { 0xc8000013 } +- }, + /* lf.div.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -900,12 +856,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_add_s, { 0xc8000006 } + }, +-/* lf.rem.d $rDDF,$rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_add_d, { 0xc8000016 } +- }, + /* lf.rem.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -918,12 +868,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RDSF), ',', OP (RA), 0 } }, + & ifmt_lf_itof_s, { 0xc8000004 } + }, +-/* lf.itof.d $rDDF,$rA */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RDDF), ',', OP (RA), 0 } }, +- & ifmt_lf_itof_d, { 0xc8000014 } +- }, + /* lf.itof.d $rDD32F,$rADI */ + { + { 0, 0, 0, 0 }, +@@ -936,12 +880,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RD), ',', OP (RASF), 0 } }, + & ifmt_lf_ftoi_s, { 0xc8000005 } + }, +-/* lf.ftoi.d $rD,$rADF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RD), ',', OP (RADF), 0 } }, +- & ifmt_lf_ftoi_d, { 0xc8000015 } +- }, + /* lf.ftoi.d $rDDI,$rAD32F */ + { + { 0, 0, 0, 0 }, +@@ -954,12 +892,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc8000008 } + }, +-/* lf.sfeq.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc8000018 } +- }, + /* lf.sfeq.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -972,12 +904,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc8000009 } + }, +-/* lf.sfne.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc8000019 } +- }, + /* lf.sfne.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -990,12 +916,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800000b } + }, +-/* lf.sfge.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800001b } +- }, + /* lf.sfge.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1008,12 +928,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800000a } + }, +-/* lf.sfgt.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800001a } +- }, + /* lf.sfgt.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1026,12 +940,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800000c } + }, +-/* lf.sflt.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800001c } +- }, + /* lf.sflt.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1044,12 +952,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800000d } + }, +-/* lf.sfle.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800001d } +- }, + /* lf.sfle.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1062,12 +964,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc8000028 } + }, +-/* lf.sfueq.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc8000038 } +- }, + /* lf.sfueq.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1080,12 +976,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc8000029 } + }, +-/* lf.sfune.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc8000039 } +- }, + /* lf.sfune.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1098,12 +988,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800002a } + }, +-/* lf.sfugt.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800003a } +- }, + /* lf.sfugt.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1116,12 +1000,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800002b } + }, +-/* lf.sfuge.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800003b } +- }, + /* lf.sfuge.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1134,12 +1012,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800002c } + }, +-/* lf.sfult.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800003c } +- }, + /* lf.sfult.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1152,12 +1024,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800002d } + }, +-/* lf.sfule.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800003d } +- }, + /* lf.sfule.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1170,12 +1036,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_sfeq_s, { 0xc800002e } + }, +-/* lf.sfun.d $rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_sfeq_d, { 0xc800003e } +- }, + /* lf.sfun.d $rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1188,12 +1048,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RDSF), ',', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_add_s, { 0xc8000007 } + }, +-/* lf.madd.d $rDDF,$rADF,$rBDF */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, ' ', OP (RDDF), ',', OP (RADF), ',', OP (RBDF), 0 } }, +- & ifmt_lf_add_d, { 0xc8000017 } +- }, + /* lf.madd.d $rDD32F,$rAD32F,$rBD32F */ + { + { 0, 0, 0, 0 }, +@@ -1206,12 +1060,6 @@ static const CGEN_OPCODE or1k_cgen_insn_opcode_table[MAX_INSNS] = + { { MNEM, ' ', OP (RASF), ',', OP (RBSF), 0 } }, + & ifmt_lf_cust1_s, { 0xc80000d0 } + }, +-/* lf.cust1.d */ +- { +- { 0, 0, 0, 0 }, +- { { MNEM, 0 } }, +- & ifmt_lf_cust1_d, { 0xc80000e0 } +- }, + /* lf.cust1.d */ + { + { 0, 0, 0, 0 }, +diff --git a/opcodes/or1k-opc.h b/opcodes/or1k-opc.h +index 2ec4b4b323..0c392274a2 100644 +--- a/opcodes/or1k-opc.h ++++ b/opcodes/or1k-opc.h +@@ -70,23 +70,17 @@ typedef enum cgen_insn_type { + , OR1K_INSN_L_MACU, OR1K_INSN_L_MSB, OR1K_INSN_L_MSBU, OR1K_INSN_L_CUST1 + , OR1K_INSN_L_CUST2, OR1K_INSN_L_CUST3, OR1K_INSN_L_CUST4, OR1K_INSN_L_CUST5 + , OR1K_INSN_L_CUST6, OR1K_INSN_L_CUST7, OR1K_INSN_L_CUST8, OR1K_INSN_LF_ADD_S +- , OR1K_INSN_LF_ADD_D, OR1K_INSN_LF_ADD_D32, OR1K_INSN_LF_SUB_S, OR1K_INSN_LF_SUB_D +- , OR1K_INSN_LF_SUB_D32, OR1K_INSN_LF_MUL_S, OR1K_INSN_LF_MUL_D, OR1K_INSN_LF_MUL_D32 +- , OR1K_INSN_LF_DIV_S, OR1K_INSN_LF_DIV_D, OR1K_INSN_LF_DIV_D32, OR1K_INSN_LF_REM_S +- , OR1K_INSN_LF_REM_D, OR1K_INSN_LF_REM_D32, OR1K_INSN_LF_ITOF_S, OR1K_INSN_LF_ITOF_D +- , OR1K_INSN_LF_ITOF_D32, OR1K_INSN_LF_FTOI_S, OR1K_INSN_LF_FTOI_D, OR1K_INSN_LF_FTOI_D32 +- , OR1K_INSN_LF_SFEQ_S, OR1K_INSN_LF_SFEQ_D, OR1K_INSN_LF_SFEQ_D32, OR1K_INSN_LF_SFNE_S +- , OR1K_INSN_LF_SFNE_D, OR1K_INSN_LF_SFNE_D32, OR1K_INSN_LF_SFGE_S, OR1K_INSN_LF_SFGE_D +- , OR1K_INSN_LF_SFGE_D32, OR1K_INSN_LF_SFGT_S, OR1K_INSN_LF_SFGT_D, OR1K_INSN_LF_SFGT_D32 +- , OR1K_INSN_LF_SFLT_S, OR1K_INSN_LF_SFLT_D, OR1K_INSN_LF_SFLT_D32, OR1K_INSN_LF_SFLE_S +- , OR1K_INSN_LF_SFLE_D, OR1K_INSN_LF_SFLE_D32, OR1K_INSN_LF_SFUEQ_S, OR1K_INSN_LF_SFUEQ_D +- , OR1K_INSN_LF_SFUEQ_D32, OR1K_INSN_LF_SFUNE_S, OR1K_INSN_LF_SFUNE_D, OR1K_INSN_LF_SFUNE_D32 +- , OR1K_INSN_LF_SFUGT_S, OR1K_INSN_LF_SFUGT_D, OR1K_INSN_LF_SFUGT_D32, OR1K_INSN_LF_SFUGE_S +- , OR1K_INSN_LF_SFUGE_D, OR1K_INSN_LF_SFUGE_D32, OR1K_INSN_LF_SFULT_S, OR1K_INSN_LF_SFULT_D +- , OR1K_INSN_LF_SFULT_D32, OR1K_INSN_LF_SFULE_S, OR1K_INSN_LF_SFULE_D, OR1K_INSN_LF_SFULE_D32 +- , OR1K_INSN_LF_SFUN_S, OR1K_INSN_LF_SFUN_D, OR1K_INSN_LF_SFUN_D32, OR1K_INSN_LF_MADD_S +- , OR1K_INSN_LF_MADD_D, OR1K_INSN_LF_MADD_D32, OR1K_INSN_LF_CUST1_S, OR1K_INSN_LF_CUST1_D +- , OR1K_INSN_LF_CUST1_D32 ++ , OR1K_INSN_LF_ADD_D32, OR1K_INSN_LF_SUB_S, OR1K_INSN_LF_SUB_D32, OR1K_INSN_LF_MUL_S ++ , OR1K_INSN_LF_MUL_D32, OR1K_INSN_LF_DIV_S, OR1K_INSN_LF_DIV_D32, OR1K_INSN_LF_REM_S ++ , OR1K_INSN_LF_REM_D32, OR1K_INSN_LF_ITOF_S, OR1K_INSN_LF_ITOF_D32, OR1K_INSN_LF_FTOI_S ++ , OR1K_INSN_LF_FTOI_D32, OR1K_INSN_LF_SFEQ_S, OR1K_INSN_LF_SFEQ_D32, OR1K_INSN_LF_SFNE_S ++ , OR1K_INSN_LF_SFNE_D32, OR1K_INSN_LF_SFGE_S, OR1K_INSN_LF_SFGE_D32, OR1K_INSN_LF_SFGT_S ++ , OR1K_INSN_LF_SFGT_D32, OR1K_INSN_LF_SFLT_S, OR1K_INSN_LF_SFLT_D32, OR1K_INSN_LF_SFLE_S ++ , OR1K_INSN_LF_SFLE_D32, OR1K_INSN_LF_SFUEQ_S, OR1K_INSN_LF_SFUEQ_D32, OR1K_INSN_LF_SFUNE_S ++ , OR1K_INSN_LF_SFUNE_D32, OR1K_INSN_LF_SFUGT_S, OR1K_INSN_LF_SFUGT_D32, OR1K_INSN_LF_SFUGE_S ++ , OR1K_INSN_LF_SFUGE_D32, OR1K_INSN_LF_SFULT_S, OR1K_INSN_LF_SFULT_D32, OR1K_INSN_LF_SFULE_S ++ , OR1K_INSN_LF_SFULE_D32, OR1K_INSN_LF_SFUN_S, OR1K_INSN_LF_SFUN_D32, OR1K_INSN_LF_MADD_S ++ , OR1K_INSN_LF_MADD_D32, OR1K_INSN_LF_CUST1_S, OR1K_INSN_LF_CUST1_D32 + } CGEN_INSN_TYPE; + + /* Index of `invalid' insn place holder. */ +diff --git a/opcodes/or1k-opinst.c b/opcodes/or1k-opinst.c +index 84a0dfe9bc..7be3e5210d 100644 +--- a/opcodes/or1k-opinst.c ++++ b/opcodes/or1k-opinst.c +@@ -43,54 +43,54 @@ static const CGEN_OPINST sfmt_empty_ops[] ATTRIBUTE_UNUSED = { + }; + + static const CGEN_OPINST sfmt_l_j_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP26), 0, 0 }, +- { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP26), 0, 0 }, ++ { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_adrp_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "disp21", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP21), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { INPUT, "disp21", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP21), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_jal_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP26), 0, 0 }, +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "h_gpr_UDI_9", HW_H_GPR, CGEN_MODE_UDI, 0, 9, 0 }, +- { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP26), 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "h_gpr_USI_9", HW_H_GPR, CGEN_MODE_USI, 0, 9, 0 }, ++ { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_jr_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_jalr_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "h_gpr_UDI_9", HW_H_GPR, CGEN_MODE_UDI, 0, 9, 0 }, +- { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "h_gpr_USI_9", HW_H_GPR, CGEN_MODE_USI, 0, 9, 0 }, ++ { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_bnf_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_UDI, OP_ENT (DISP26), 0, COND_REF }, +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, ++ { INPUT, "disp26", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP26), 0, COND_REF }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "sys_cpucfgr_nd", HW_H_SYS_CPUCFGR_ND, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_trap_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + +@@ -105,94 +105,94 @@ static const CGEN_OPINST sfmt_l_nop_imm_ops[] ATTRIBUTE_UNUSED = { + + static const CGEN_OPINST sfmt_l_movhi_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "uimm16", HW_H_UIMM16, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_macrc_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_mfspr_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "uimm16", HW_H_UIMM16, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_mtspr_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, + { INPUT, "uimm16_split", HW_H_UIMM16, CGEN_MODE_UINT, OP_ENT (UIMM16_SPLIT), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_lwz_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_USI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_4", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_lws_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_SI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_4", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_lwa_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_USI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_4", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, + { OUTPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 }, + { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_lbz_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_UQI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_1", HW_H_MEMORY, CGEN_MODE_UQI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_lbs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_QI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_1", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_lhz_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_UHI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_2", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_lhs_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "h_memory_HI_c_call__AI_@cpu@_make_load_store_addr_rA_ext__SI_simm16_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_sw_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, + { INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 }, + { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_USI_addr", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, 0 }, +@@ -201,8 +201,8 @@ static const CGEN_OPINST sfmt_l_sw_ops[] ATTRIBUTE_UNUSED = { + + static const CGEN_OPINST sfmt_l_sb_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, + { INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 }, + { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UQI_addr", HW_H_MEMORY, CGEN_MODE_UQI, 0, 0, 0 }, +@@ -211,8 +211,8 @@ static const CGEN_OPINST sfmt_l_sb_ops[] ATTRIBUTE_UNUSED = { + + static const CGEN_OPINST sfmt_l_sh_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, + { INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 }, + { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, COND_REF }, + { OUTPUT, "h_memory_UHI_addr", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, 0 }, +@@ -222,228 +222,228 @@ static const CGEN_OPINST sfmt_l_sh_ops[] ATTRIBUTE_UNUSED = { + static const CGEN_OPINST sfmt_l_swa_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "atomic_address", HW_H_ATOMIC_ADDRESS, CGEN_MODE_SI, 0, 0, 0 }, + { INPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, COND_REF }, + { INPUT, "simm16_split", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16_SPLIT), 0, 0 }, +- { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 }, + { OUTPUT, "atomic_reserve", HW_H_ATOMIC_RESERVE, CGEN_MODE_BI, 0, 0, 0 }, + { OUTPUT, "h_memory_USI_addr", HW_H_MEMORY, CGEN_MODE_USI, 0, 0, COND_REF }, +- { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_sll_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_slli_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "uimm6", HW_H_UIMM6, CGEN_MODE_UINT, OP_ENT (UIMM6), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_and_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_add_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, +- { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_addc_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, +- { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_mul_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_muld_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_mulu_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, +- { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_div_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, COND_REF }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, COND_REF }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, COND_REF }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, COND_REF }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, COND_REF }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_divu_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, COND_REF }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, COND_REF }, +- { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, COND_REF }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, COND_REF }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, COND_REF }, ++ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_ff1_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_xori_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_addi_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, +- { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_addic_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, +- { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_muli_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_exths_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_cmov_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, COND_REF }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, COND_REF }, +- { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, COND_REF }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, COND_REF }, ++ { INPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, COND_REF }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_sfgts_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_sfgtsi_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_mac_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_maci_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, + { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }, +- { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_ov", HW_H_SYS_SR_OV, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_l_macu_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "pc", HW_H_PC, CGEN_MODE_UDI, 0, 0, COND_REF }, +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }, +- { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, +- { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "rB", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RB), 0, 0 }, ++ { INPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, ++ { INPUT, "sys_sr_ove", HW_H_SYS_SR_OVE, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_machi", HW_H_MAC_MACHI, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "mac_maclo", HW_H_MAC_MACLO, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_cy", HW_H_SYS_SR_CY, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + +@@ -454,13 +454,6 @@ static const CGEN_OPINST sfmt_lf_add_s_ops[] ATTRIBUTE_UNUSED = { + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + +-static const CGEN_OPINST sfmt_lf_add_d_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 }, +- { INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 }, +- { OUTPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 }, +- { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +-}; +- + static const CGEN_OPINST sfmt_lf_add_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 }, + { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 }, +@@ -469,43 +462,29 @@ static const CGEN_OPINST sfmt_lf_add_d32_ops[] ATTRIBUTE_UNUSED = { + }; + + static const CGEN_OPINST sfmt_lf_itof_s_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "rA", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RA), 0, 0 }, ++ { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_USI, 0, 0, 0 }, + { OUTPUT, "rDSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RDSF), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + +-static const CGEN_OPINST sfmt_lf_itof_d_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rA", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RA), 0, 0 }, +- { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 }, +- { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +-}; +- + static const CGEN_OPINST sfmt_lf_itof_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rADI", HW_H_I64R, CGEN_MODE_DI, OP_ENT (RADI), 0, 0 }, +- { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_USI, 0, 0, 0 }, + { OUTPUT, "rDD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RDD32F), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_lf_ftoi_s_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 }, +- { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, +- { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +-}; +- +-static const CGEN_OPINST sfmt_lf_ftoi_d_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 }, +- { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, +- { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RD), 0, 0 }, ++ { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_USI, 0, 0, 0 }, ++ { OUTPUT, "rD", HW_H_GPR, CGEN_MODE_USI, OP_ENT (RD), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_lf_ftoi_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 }, +- { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_UDI, 0, 0, 0 }, ++ { INPUT, "sys_fpcsr_rm", HW_H_SYS_FPCSR_RM, CGEN_MODE_USI, 0, 0, 0 }, + { OUTPUT, "rDDI", HW_H_I64R, CGEN_MODE_DI, OP_ENT (RDDI), 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; +@@ -513,21 +492,14 @@ static const CGEN_OPINST sfmt_lf_ftoi_d32_ops[] ATTRIBUTE_UNUSED = { + static const CGEN_OPINST sfmt_lf_sfeq_s_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rASF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RASF), 0, 0 }, + { INPUT, "rBSF", HW_H_FSR, CGEN_MODE_SF, OP_ENT (RBSF), 0, 0 }, +- { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, +- { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +-}; +- +-static const CGEN_OPINST sfmt_lf_sfeq_d_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 }, +- { INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 }, +- { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + + static const CGEN_OPINST sfmt_lf_sfeq_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 }, + { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 }, +- { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_UDI, 0, 0, 0 }, ++ { OUTPUT, "sys_sr_f", HW_H_SYS_SR_F, CGEN_MODE_USI, 0, 0, 0 }, + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + +@@ -539,14 +511,6 @@ static const CGEN_OPINST sfmt_lf_madd_s_ops[] ATTRIBUTE_UNUSED = { + { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } + }; + +-static const CGEN_OPINST sfmt_lf_madd_d_ops[] ATTRIBUTE_UNUSED = { +- { INPUT, "rADF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RADF), 0, 0 }, +- { INPUT, "rBDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RBDF), 0, 0 }, +- { INPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 }, +- { OUTPUT, "rDDF", HW_H_FDR, CGEN_MODE_DF, OP_ENT (RDDF), 0, 0 }, +- { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 } +-}; +- + static const CGEN_OPINST sfmt_lf_madd_d32_ops[] ATTRIBUTE_UNUSED = { + { INPUT, "rAD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RAD32F), 0, 0 }, + { INPUT, "rBD32F", HW_H_FD32R, CGEN_MODE_DF, OP_ENT (RBD32F), 0, 0 }, +@@ -664,71 +628,49 @@ static const CGEN_OPINST *or1k_cgen_opinst_table[MAX_INSNS] = { + & sfmt_l_msync_ops[0], + & sfmt_l_msync_ops[0], + & sfmt_lf_add_s_ops[0], +- & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], + & sfmt_lf_add_s_ops[0], +- & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], + & sfmt_lf_add_s_ops[0], +- & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], + & sfmt_lf_add_s_ops[0], +- & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], + & sfmt_lf_add_s_ops[0], +- & sfmt_lf_add_d_ops[0], + & sfmt_lf_add_d32_ops[0], + & sfmt_lf_itof_s_ops[0], +- & sfmt_lf_itof_d_ops[0], + & sfmt_lf_itof_d32_ops[0], + & sfmt_lf_ftoi_s_ops[0], +- & sfmt_lf_ftoi_d_ops[0], + & sfmt_lf_ftoi_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_sfeq_s_ops[0], +- & sfmt_lf_sfeq_d_ops[0], + & sfmt_lf_sfeq_d32_ops[0], + & sfmt_lf_madd_s_ops[0], +- & sfmt_lf_madd_d_ops[0], + & sfmt_lf_madd_d32_ops[0], + & sfmt_l_msync_ops[0], + & sfmt_l_msync_ops[0], +- & sfmt_l_msync_ops[0], + }; + + /* Function to call before using the operand instance table. */ +-- +2.21.0 + + diff --git a/patches/binutils-2.33.1/0004-arm-pr22269.diff b/patches/binutils-2.33.1/0004-arm-pr22269.diff new file mode 100644 index 0000000..79043fb --- /dev/null +++ b/patches/binutils-2.33.1/0004-arm-pr22269.diff @@ -0,0 +1,55 @@ +From: Szabolcs Nagy +Date: Thu, 9 Jan 2020 17:20:56 +0000 (+0000) +Subject: [PR ld/22269] arm: Avoid dynamic relocs for undefweak symbols in static PIE +X-Git-Url: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commitdiff_plain;h=6fbcfe4762c3732339cffd82426d00d35382b858;hp=c06868784d819a45c43947180c69e168aecaf368 + +[PR ld/22269] arm: Avoid dynamic relocs for undefweak symbols in static PIE + +With static PIE linking undefined weak symbols are resolved to 0, so no +dynamic relocation is needed for them. The UNDEFWEAK_NO_DYNAMIC_RELOC +macro was introduced so this case can be handled easily, but it was not +applied consistently in the first attempt to fix ld/22269 for arm: + + commit 95b03e4ad68e7a90f5096b47df595636344b783a + arm: Check UNDEFWEAK_NO_DYNAMIC_RELOC + +This patch fixes spurious relative relocs in static PIE binaries against +GOT entries created for undefined weak symbols on arm*-*, this fixes + +FAIL: pr22269-1 (static pie undefined weak) + +bfd/ChangeLog: + + Backported from master + 2020-01-10 Szabolcs Nagy + + PR ld/22269 + * elf32-arm.c (elf32_arm_final_link_relocate): Use + UNDEFWEAK_NO_DYNAMIC_RELOC. + (allocate_dynrelocs_for_symbol): Likewise. +--- + +diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c +index cce796d..21cf4b0 100644 +--- a/bfd/elf32-arm.c ++++ b/bfd/elf32-arm.c +@@ -11572,8 +11572,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto, + if (dynreloc_st_type == STT_GNU_IFUNC) + outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE); + else if (bfd_link_pic (info) +- && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT +- || h->root.type != bfd_link_hash_undefweak)) ++ && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)) + outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE); + else + { +@@ -16527,8 +16526,7 @@ allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf) + GOT entry's R_ARM_IRELATIVE relocation. */ + elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1); + else if (bfd_link_pic (info) +- && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT +- || h->root.type != bfd_link_hash_undefweak)) ++ && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)) + /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */ + elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1); + else if (htab->fdpic_p && tls_type == GOT_NORMAL) diff --git a/patches/binutils-397a64b3/0001-staticpie.diff b/patches/binutils-397a64b3/0001-staticpie.diff new file mode 100644 index 0000000..76688d3 --- /dev/null +++ b/patches/binutils-397a64b3/0001-staticpie.diff @@ -0,0 +1,377 @@ +diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c +index bd4b576..41803c2 100644 +--- a/bfd/elf32-arm.c ++++ b/bfd/elf32-arm.c +@@ -13786,7 +13786,7 @@ elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-bfin.c b/bfd/elf32-bfin.c +index 49ef360..8346d57 100644 +--- a/bfd/elf32-bfin.c ++++ b/bfd/elf32-bfin.c +@@ -4257,7 +4257,7 @@ elf32_bfinfdpic_size_dynamic_sections (bfd *output_bfd, + if (htab->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-cris.c b/bfd/elf32-cris.c +index 3031173..5b40524 100644 +--- a/bfd/elf32-cris.c ++++ b/bfd/elf32-cris.c +@@ -3764,7 +3764,7 @@ elf_cris_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-frv.c b/bfd/elf32-frv.c +index b55a7ab..ef72c23 100644 +--- a/bfd/elf32-frv.c ++++ b/bfd/elf32-frv.c +@@ -5444,7 +5444,7 @@ elf32_frvfdpic_size_dynamic_sections (bfd *output_bfd, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-hppa.c b/bfd/elf32-hppa.c +index 41bf5c5..62c7cf6 100644 +--- a/bfd/elf32-hppa.c ++++ b/bfd/elf32-hppa.c +@@ -2215,7 +2215,7 @@ elf32_hppa_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (htab->etab.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + sec = bfd_get_linker_section (dynobj, ".interp"); + if (sec == NULL) +diff --git a/bfd/elf32-i370.c b/bfd/elf32-i370.c +index 7fba4d1..458f694 100644 +--- a/bfd/elf32-i370.c ++++ b/bfd/elf32-i370.c +@@ -594,7 +594,7 @@ i370_elf_size_dynamic_sections (bfd *output_bfd, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-i386.c b/bfd/elf32-i386.c +index 7642d0f..b0844c8 100644 +--- a/bfd/elf32-i386.c ++++ b/bfd/elf32-i386.c +@@ -2834,7 +2834,7 @@ elf_i386_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info) + if (htab->elf.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + if (s == NULL) +diff --git a/bfd/elf32-m32r.c b/bfd/elf32-m32r.c +index 155d079..a2e3c7c 100644 +--- a/bfd/elf32-m32r.c ++++ b/bfd/elf32-m32r.c +@@ -2170,7 +2170,7 @@ m32r_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (htab->root.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-m68k.c b/bfd/elf32-m68k.c +index 10d2fcb..489f3f1 100644 +--- a/bfd/elf32-m68k.c ++++ b/bfd/elf32-m68k.c +@@ -3257,7 +3257,7 @@ elf_m68k_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-ppc.c b/bfd/elf32-ppc.c +index 8415f1e..5597051 100644 +--- a/bfd/elf32-ppc.c ++++ b/bfd/elf32-ppc.c +@@ -6191,7 +6191,7 @@ ppc_elf_size_dynamic_sections (bfd *output_bfd, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (htab->elf.dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-s390.c b/bfd/elf32-s390.c +index de37ca4..a1e628c 100644 +--- a/bfd/elf32-s390.c ++++ b/bfd/elf32-s390.c +@@ -2039,7 +2039,7 @@ elf_s390_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (htab->elf.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + if (s == NULL) +diff --git a/bfd/elf32-sh.c b/bfd/elf32-sh.c +index 012ee4e..a51453f 100644 +--- a/bfd/elf32-sh.c ++++ b/bfd/elf32-sh.c +@@ -3349,7 +3349,7 @@ sh_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (htab->root.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-vax.c b/bfd/elf32-vax.c +index 6089e8c..893ea8d 100644 +--- a/bfd/elf32-vax.c ++++ b/bfd/elf32-vax.c +@@ -1124,7 +1124,7 @@ elf_vax_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info) + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf32-xtensa.c b/bfd/elf32-xtensa.c +index 73538cd..37ea5da 100644 +--- a/bfd/elf32-xtensa.c ++++ b/bfd/elf32-xtensa.c +@@ -1637,7 +1637,7 @@ elf_xtensa_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + && htab->sgotloc != NULL); + + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + if (s == NULL) +diff --git a/bfd/elf64-alpha.c b/bfd/elf64-alpha.c +index f67b0af..1973cd0 100644 +--- a/bfd/elf64-alpha.c ++++ b/bfd/elf64-alpha.c +@@ -2877,7 +2877,7 @@ elf64_alpha_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf64-hppa.c b/bfd/elf64-hppa.c +index 6f40b88..3b628b4 100644 +--- a/bfd/elf64-hppa.c ++++ b/bfd/elf64-hppa.c +@@ -1558,7 +1558,7 @@ elf64_hppa_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info) + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + sec = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (sec != NULL); +diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c +index 8cff990..851845f 100644 +--- a/bfd/elf64-ppc.c ++++ b/bfd/elf64-ppc.c +@@ -9748,7 +9748,7 @@ ppc64_elf_size_dynamic_sections (bfd *output_bfd, + if (htab->elf.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + if (s == NULL) +diff --git a/bfd/elf64-s390.c b/bfd/elf64-s390.c +index 2e505f3..406bb66 100644 +--- a/bfd/elf64-s390.c ++++ b/bfd/elf64-s390.c +@@ -1989,7 +1989,7 @@ elf_s390_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + if (htab->elf.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + if (s == NULL) +diff --git a/bfd/elf64-sh64.c b/bfd/elf64-sh64.c +index e460895..d920598 100644 +--- a/bfd/elf64-sh64.c ++++ b/bfd/elf64-sh64.c +@@ -3404,7 +3404,7 @@ sh64_elf64_size_dynamic_sections (bfd *output_bfd, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elf64-x86-64.c b/bfd/elf64-x86-64.c +index f15d33e..870aadf 100644 +--- a/bfd/elf64-x86-64.c ++++ b/bfd/elf64-x86-64.c +@@ -3181,7 +3181,7 @@ elf_x86_64_size_dynamic_sections (bfd *output_bfd, + if (htab->elf.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + if (s == NULL) +diff --git a/bfd/elflink.c b/bfd/elflink.c +index 7f04271..5b3438d 100644 +--- a/bfd/elflink.c ++++ b/bfd/elflink.c +@@ -246,7 +246,7 @@ _bfd_elf_link_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info) + + /* A dynamically linked executable has a .interp section, but a + shared library does not. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_make_section_anyway_with_flags (abfd, ".interp", + flags | SEC_READONLY); +@@ -5763,7 +5763,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd, + bfd_boolean all_defined; + + *sinterpptr = bfd_get_section_by_name (dynobj, ".interp"); +- BFD_ASSERT (*sinterpptr != NULL || !info->executable); ++ BFD_ASSERT (*sinterpptr != NULL || !info->executable || info->nointerp); + + if (soname != NULL) + { +diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c +index be1e59a..329dec3 100644 +--- a/bfd/elfxx-mips.c ++++ b/bfd/elfxx-mips.c +@@ -9579,7 +9579,7 @@ _bfd_mips_elf_size_dynamic_sections (bfd *output_bfd, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/bfd/elfxx-sparc.c b/bfd/elfxx-sparc.c +index 9bb71a9..db0d4f1 100644 +--- a/bfd/elfxx-sparc.c ++++ b/bfd/elfxx-sparc.c +@@ -2559,7 +2559,7 @@ _bfd_sparc_elf_size_dynamic_sections (bfd *output_bfd, + if (elf_hash_table (info)->dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ +- if (info->executable) ++ if (info->executable && !info->nointerp) + { + s = bfd_get_linker_section (dynobj, ".interp"); + BFD_ASSERT (s != NULL); +diff --git a/include/bfdlink.h b/include/bfdlink.h +index 797a465..cf533dd 100644 +--- a/include/bfdlink.h ++++ b/include/bfdlink.h +@@ -433,6 +433,9 @@ struct bfd_link_info + /* TRUE if BND prefix in PLT entries is always generated. */ + unsigned int bndplt: 1; + ++ /* TRUE if generation of .interp/PT_INTERP should be suppressed. */ ++ unsigned int nointerp: 1; ++ + /* Char that may appear as the first char of a symbol, but should be + skipped (like symbol_leading_char) when looking up symbols in + wrap_hash. Used by PowerPC Linux for 'dot' symbols. */ +diff --git a/ld/ld.texinfo b/ld/ld.texinfo +index cf3b586..1e5e5cf 100644 +--- a/ld/ld.texinfo ++++ b/ld/ld.texinfo +@@ -1426,6 +1426,13 @@ generating dynamically linked ELF executables. The default dynamic + linker is normally correct; don't use this unless you know what you are + doing. + ++@kindex --no-dynamic-linker ++@item --no-dynamic-linker ++When producing an executable file, omit the request for a dynamic ++linker to be used at load-time. This is only meaningful for ELF ++executables that contain dynamic relocations, and usually requires ++entry point code that is capable of processing these relocations. ++ + @kindex --fatal-warnings + @kindex --no-fatal-warnings + @item --fatal-warnings +diff --git a/ld/lexsup.c b/ld/lexsup.c +index 59bd14f..8b57f84 100644 +--- a/ld/lexsup.c ++++ b/ld/lexsup.c +@@ -33,6 +33,7 @@ enum option_values + OPTION_DEFSYM, + OPTION_DEMANGLE, + OPTION_DYNAMIC_LINKER, ++ OPTION_NO_DYNAMIC_LINKER, + OPTION_SYSROOT, + OPTION_EB, + OPTION_EL, +diff --git a/ld/lexsup.c b/ld/lexsup.c +index 777d6e2..1b992f7 100644 +--- a/ld/lexsup.c ++++ b/ld/lexsup.c +@@ -138,6 +138,9 @@ static const struct ld_option ld_options[] = + { {"dynamic-linker", required_argument, NULL, OPTION_DYNAMIC_LINKER}, + 'I', N_("PROGRAM"), N_("Set PROGRAM as the dynamic linker to use"), + TWO_DASHES }, ++ { {"no-dynamic-linker", no_argument, NULL, OPTION_NO_DYNAMIC_LINKER}, ++ '\0', NULL, N_("Produce an executable with no program interpreter header"), ++ TWO_DASHES }, + { {"library", required_argument, NULL, 'l'}, + 'l', N_("LIBNAME"), N_("Search for library LIBNAME"), TWO_DASHES }, + { {"library-path", required_argument, NULL, 'L'}, +@@ -762,6 +765,10 @@ parse_args (unsigned argc, char **argv) + case 'I': /* Used on Solaris. */ + case OPTION_DYNAMIC_LINKER: + command_line.interpreter = optarg; ++ link_info.nointerp = 0; ++ break; ++ case OPTION_NO_DYNAMIC_LINKER: ++ link_info.nointerp = 1; + break; + case OPTION_SYSROOT: + /* Already handled in ldmain.c. */ diff --git a/patches/binutils-397a64b3/0006-noinfo.diff b/patches/binutils-397a64b3/0006-noinfo.diff new file mode 100644 index 0000000..d62c414 --- /dev/null +++ b/patches/binutils-397a64b3/0006-noinfo.diff @@ -0,0 +1,18 @@ +The binutils build notices that makeinfo is missing, but fails anyway, breaking +the build. Make it stop. + +The "info" file format is obsolete (similar to "gopher"), was never used +by anyone but the FSF, and failed to even replace man pages (which are +now available in HTML). + +--- binutils-2.18/missing 2005-07-13 20:24:56.000000000 -0500 ++++ binutils-2.18/missing 2008-08-11 02:05:47.000000000 -0500 +@@ -299,7 +299,7 @@ + fi + # If the file does not exist, the user really needs makeinfo; + # let's fail without touching anything. +- test -f $file || exit 1 ++ test -f $file || exit 0 + touch $file + ;; + diff --git a/patches/binutils-397a64b3/0007-shpcrel.diff b/patches/binutils-397a64b3/0007-shpcrel.diff new file mode 100644 index 0000000..107e828 --- /dev/null +++ b/patches/binutils-397a64b3/0007-shpcrel.diff @@ -0,0 +1,11 @@ +--- binutils-397a64b3.orig//gas/config/tc-sh.c 2015-08-11 01:29:26.000000000 +0000 ++++ binutils-397a64b3/gas/config/tc-sh.c 2015-11-02 23:17:03.931462591 +0000 +@@ -4491,6 +4496,8 @@ sh_parse_name (char const *name, + reloc_type = BFD_RELOC_SH_TLS_LE_32; + else if ((next_end = sh_end_of_match (next + 1, "DTPOFF"))) + reloc_type = BFD_RELOC_SH_TLS_LDO_32; ++ else if ((next_end = sh_end_of_match (next + 1, "PCREL"))) ++ reloc_type = BFD_RELOC_32_PCREL; + else + goto no_suffix; + diff --git a/patches/gcc-10.3.0/0001-ssp_nonshared.diff b/patches/gcc-10.3.0/0001-ssp_nonshared.diff new file mode 100644 index 0000000..9e2fcca --- /dev/null +++ b/patches/gcc-10.3.0/0001-ssp_nonshared.diff @@ -0,0 +1,14 @@ +diff --git a/gcc/gcc.c b/gcc/gcc.c +index 9f790db0daf..e6887590ae2 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -877,7 +877,8 @@ proper position among the other output files. */ + #ifndef LINK_SSP_SPEC + #ifdef TARGET_LIBC_PROVIDES_SSP + #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ +- "|fstack-protector-strong|fstack-protector-explicit:}" ++ "|fstack-protector-strong|fstack-protector-explicit" \ ++ ":-lssp_nonshared}" + #else + #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ + "|fstack-protector-strong|fstack-protector-explicit" \ diff --git a/patches/gcc-10.3.0/0002-posix_memalign.diff b/patches/gcc-10.3.0/0002-posix_memalign.diff new file mode 100644 index 0000000..21c7ad2 --- /dev/null +++ b/patches/gcc-10.3.0/0002-posix_memalign.diff @@ -0,0 +1,30 @@ +diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h +index 87344d9383f..ece428df487 100644 +--- a/gcc/config/i386/pmm_malloc.h ++++ b/gcc/config/i386/pmm_malloc.h +@@ -27,12 +27,13 @@ + #include + + /* We can't depend on since the prototype of posix_memalign +- may not be visible. */ ++ may not be visible and we can't pollute the namespace either. */ + #ifndef __cplusplus +-extern int posix_memalign (void **, size_t, size_t); ++extern int _mm_posix_memalign (void **, size_t, size_t) + #else +-extern "C" int posix_memalign (void **, size_t, size_t) throw (); ++extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw () + #endif ++__asm__("posix_memalign"); + + static __inline void * + _mm_malloc (size_t __size, size_t __alignment) +@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment) + return malloc (__size); + if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4)) + __alignment = sizeof (void *); +- if (posix_memalign (&__ptr, __alignment, __size) == 0) ++ if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0) + return __ptr; + else + return NULL; diff --git a/patches/gcc-10.3.0/0003-j2.diff b/patches/gcc-10.3.0/0003-j2.diff new file mode 100644 index 0000000..4164755 --- /dev/null +++ b/patches/gcc-10.3.0/0003-j2.diff @@ -0,0 +1,346 @@ +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 6fcdd771d4c..839a60d866e 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -547,7 +547,7 @@ s390*-*-*) + extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h" + ;; + # Note the 'l'; we need to be able to match e.g. "shle" or "shl". +-sh[123456789lbe]*-*-* | sh-*-*) ++sh[123456789lbej]*-*-* | sh-*-*) + cpu_type=sh + extra_options="${extra_options} fused-madd.opt" + extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o" +@@ -3149,18 +3149,18 @@ s390x-ibm-tpf*) + extra_options="${extra_options} s390/tpf.opt" + tmake_file="${tmake_file} s390/t-s390" + ;; +-sh-*-elf* | sh[12346l]*-*-elf* | \ +- sh-*-linux* | sh[2346lbe]*-*-linux* | \ ++sh-*-elf* | sh[12346lj]*-*-elf* | \ ++ sh-*-linux* | sh[2346lbej]*-*-linux* | \ + sh-*-netbsdelf* | shl*-*-netbsdelf*) + tmake_file="${tmake_file} sh/t-sh sh/t-elf" + if test x${with_endian} = x; then + case ${target} in +- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;; ++ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;; + shbe-*-* | sheb-*-*) with_endian=big,little ;; + sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;; + shl* | sh*-*-linux* | \ + sh-superh-elf) with_endian=little,big ;; +- sh[1234]*-*-*) with_endian=big ;; ++ sh[j1234]*-*-*) with_endian=big ;; + *) with_endian=big,little ;; + esac + fi +@@ -3227,6 +3227,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;; + sh2a*) sh_cpu_target=sh2a ;; + sh2e*) sh_cpu_target=sh2e ;; ++ shj2*) sh_cpu_target=shj2;; + sh2*) sh_cpu_target=sh2 ;; + *) sh_cpu_target=sh1 ;; + esac +@@ -3248,7 +3249,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \ + sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \ + sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \ +- sh3e | sh3 | sh2e | sh2 | sh1) ;; ++ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;; + "") sh_cpu_default=${sh_cpu_target} ;; + *) echo "with_cpu=$with_cpu not supported"; exit 1 ;; + esac +@@ -3257,9 +3258,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + case ${target} in + sh[1234]*) sh_multilibs=${sh_cpu_target} ;; + sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;; +- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;; ++ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;; + sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;; +- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;; ++ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;; + esac + if test x$with_fp = xno; then + sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`" +@@ -3274,7 +3275,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + m1 | m2 | m2e | m3 | m3e | \ + m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\ + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \ +- m2a | m2a-single | m2a-single-only | m2a-nofpu) ++ m2a | m2a-single | m2a-single-only | m2a-nofpu | \ ++ mj2) + # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition + # It is passed to MULTIILIB_OPTIONS verbatim. + TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}" +@@ -3291,7 +3293,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + done + TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'` + if test x${enable_incomplete_targets} = xyes ; then +- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1" ++ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1" + fi + tm_file="$tm_file ./sysroot-suffix.h" + tmake_file="$tmake_file t-sysroot-suffix" +@@ -5105,6 +5107,8 @@ case "${target}" in + ;; + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al) + ;; ++ mj2) ++ ;; + *) + echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2 + echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2 +@@ -5315,7 +5319,7 @@ case ${target} in + tmake_file="${cpu_type}/t-${cpu_type} ${tmake_file}" + ;; + +- sh[123456ble]*-*-* | sh-*-*) ++ sh[123456blej]*-*-* | sh-*-*) + c_target_objs="${c_target_objs} sh-c.o" + cxx_target_objs="${cxx_target_objs} sh-c.o" + ;; +diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c +index 84c0ea025b4..f15552af011 100644 +--- a/gcc/config/sh/sh.c ++++ b/gcc/config/sh/sh.c +@@ -686,6 +686,7 @@ parse_validate_atomic_model_option (const char* str) + model_names[sh_atomic_model::hard_llcs] = "hard-llcs"; + model_names[sh_atomic_model::soft_tcb] = "soft-tcb"; + model_names[sh_atomic_model::soft_imask] = "soft-imask"; ++ model_names[sh_atomic_model::hard_cas] = "hard-cas"; + + const char* model_cdef_names[sh_atomic_model::num_models]; + model_cdef_names[sh_atomic_model::none] = "NONE"; +@@ -693,6 +694,7 @@ parse_validate_atomic_model_option (const char* str) + model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS"; + model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB"; + model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK"; ++ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS"; + + sh_atomic_model ret; + ret.type = sh_atomic_model::none; +@@ -771,6 +773,9 @@ got_mode_name:; + if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE) + err_ret ("cannot use atomic model %s in user mode", ret.name); + ++ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2) ++ err_ret ("atomic model %s is only available J2 targets", ret.name); ++ + return ret; + + #undef err_ret +@@ -827,6 +832,8 @@ sh_option_override (void) + sh_cpu = PROCESSOR_SH2E; + if (TARGET_SH2A) + sh_cpu = PROCESSOR_SH2A; ++ if (TARGET_SHJ2) ++ sh_cpu = PROCESSOR_SHJ2; + if (TARGET_SH3) + sh_cpu = PROCESSOR_SH3; + if (TARGET_SH3E) +diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h +index 8ab5455505c..6ffed6da403 100644 +--- a/gcc/config/sh/sh.h ++++ b/gcc/config/sh/sh.h +@@ -85,6 +85,7 @@ extern int code_for_indirect_jump_scratch; + #define SUPPORT_SH4_SINGLE 1 + #define SUPPORT_SH2A 1 + #define SUPPORT_SH2A_SINGLE 1 ++#define SUPPORT_SHJ2 1 + #endif + + #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) +@@ -117,6 +118,7 @@ extern int code_for_indirect_jump_scratch; + #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) + #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) + #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) ++#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2) + + #if SUPPORT_SH1 + #define SUPPORT_SH2 1 +@@ -124,6 +126,7 @@ extern int code_for_indirect_jump_scratch; + #if SUPPORT_SH2 + #define SUPPORT_SH3 1 + #define SUPPORT_SH2A_NOFPU 1 ++#define SUPPORT_SHJ2 1 + #endif + #if SUPPORT_SH3 + #define SUPPORT_SH4_NOFPU 1 +@@ -156,7 +159,7 @@ extern int code_for_indirect_jump_scratch; + #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ + | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ + | MASK_HARD_SH4 | MASK_FPU_SINGLE \ +- | MASK_FPU_SINGLE_ONLY) ++ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2) + + /* This defaults us to big-endian. */ + #ifndef TARGET_ENDIAN_DEFAULT +@@ -231,7 +234,8 @@ extern int code_for_indirect_jump_scratch; + %{m2a-single:--isa=sh2a} \ + %{m2a-single-only:--isa=sh2a} \ + %{m2a-nofpu:--isa=sh2a-nofpu} \ +-%{m4al:-dsp}" ++%{m4al:-dsp} \ ++%{mj2:-isa=j2}" + + #define ASM_SPEC SH_ASM_SPEC + +@@ -347,6 +351,7 @@ struct sh_atomic_model + hard_llcs, + soft_tcb, + soft_imask, ++ hard_cas, + + num_models + }; +@@ -390,6 +395,9 @@ extern const sh_atomic_model& selected_atomic_model (void); + #define TARGET_ATOMIC_SOFT_IMASK \ + (selected_atomic_model ().type == sh_atomic_model::soft_imask) + ++#define TARGET_ATOMIC_HARD_CAS \ ++ (selected_atomic_model ().type == sh_atomic_model::hard_cas) ++ + #endif // __cplusplus + + #define SUBTARGET_OVERRIDE_OPTIONS (void) 0 +@@ -1484,7 +1492,7 @@ extern bool current_function_interrupt; + + /* Nonzero if the target supports dynamic shift instructions + like shad and shld. */ +-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) ++#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2) + + /* The cost of using the dynamic shift insns (shad, shld) are the same + if they are available. If they are not available a library function will +@@ -1747,6 +1755,7 @@ enum processor_type { + PROCESSOR_SH2, + PROCESSOR_SH2E, + PROCESSOR_SH2A, ++ PROCESSOR_SHJ2, + PROCESSOR_SH3, + PROCESSOR_SH3E, + PROCESSOR_SH4, +diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt +index 908603b92e1..e6108dabbc6 100644 +--- a/gcc/config/sh/sh.opt ++++ b/gcc/config/sh/sh.opt +@@ -65,6 +65,10 @@ m2e + Target RejectNegative Condition(SUPPORT_SH2E) + Generate SH2e code. + ++mj2 ++Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2) ++Generate J2 code. ++ + m3 + Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) + Generate SH3 code. +diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md +index 25f3b695d2f..55119386a18 100644 +--- a/gcc/config/sh/sync.md ++++ b/gcc/config/sh/sync.md +@@ -240,6 +240,9 @@ + || (TARGET_SH4A && mode == SImode && !TARGET_ATOMIC_STRICT)) + atomic_insn = gen_atomic_compare_and_swap_hard (old_val, mem, + exp_val, new_val); ++ else if (TARGET_ATOMIC_HARD_CAS && mode == SImode) ++ atomic_insn = gen_atomic_compare_and_swap_cas (old_val, mem, ++ exp_val, new_val); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic_compare_and_swap_soft_gusa (old_val, mem, + exp_val, new_val); +@@ -306,6 +309,57 @@ + } + [(set_attr "length" "14")]) + ++(define_expand "atomic_compare_and_swapsi_cas" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "r")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{ ++ rtx mem = gen_rtx_REG (SImode, 0); ++ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0))); ++ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_insn "shj2_cas" ++ [(set (match_operand:SI 0 "register_operand" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "register_operand" "=r") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "0")] ++ UNSPECV_CMPXCHG_1)) ++ (set (reg:SI T_REG) ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))] ++ "TARGET_ATOMIC_HARD_CAS" ++ "cas.l %2,%0,@%1" ++ [(set_attr "length" "2")] ++) ++ ++(define_expand "atomic_compare_and_swapqi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ ++(define_expand "atomic_compare_and_swaphi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ + ;; The QIHImode llcs patterns modify the address register of the memory + ;; operand. In order to express that, we have to open code the memory + ;; operand. Initially the insn is expanded like every other atomic insn +diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh +index a402359be72..dbd0bf992bf 100644 +--- a/gcc/config/sh/t-sh ++++ b/gcc/config/sh/t-sh +@@ -50,7 +50,8 @@ MULTILIB_MATCHES = $(shell \ + m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \ + m2a-single,m2a-single-only \ + m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \ +- m4,m4-100,m4-200,m4-300,m4a; do \ ++ m4,m4-100,m4-200,m4-300,m4a \ ++ mj2; do \ + subst= ; \ + for lib in `echo $$abi|tr , ' '` ; do \ + if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \ +@@ -63,9 +64,9 @@ MULTILIB_MATCHES = $(shell \ + + # SH1 and SH2A support big endian only. + ifeq ($(DEFAULT_ENDIAN),ml) +-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + else +-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + endif + + MULTILIB_OSDIRNAMES = \ +@@ -87,7 +88,8 @@ MULTILIB_OSDIRNAMES = \ + m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \ + m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \ + m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \ +- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al ++ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \ ++ mj2=!j2 + + $(out_object_file): gt-sh.h + gt-sh.h : s-gtype ; @true diff --git a/patches/gcc-10.3.0/0004-static-pie.diff b/patches/gcc-10.3.0/0004-static-pie.diff new file mode 100644 index 0000000..b265376 --- /dev/null +++ b/patches/gcc-10.3.0/0004-static-pie.diff @@ -0,0 +1,92 @@ +diff --git a/gcc/common.opt b/gcc/common.opt +index ec5235c3a41..dcee05500ba 100644 +--- a/gcc/common.opt ++++ b/gcc/common.opt +@@ -3401,11 +3401,11 @@ Driver + + no-pie + Driver RejectNegative Negative(shared) +-Don't create a dynamically linked position independent executable. ++Don't create a position independent executable. + + pie + Driver RejectNegative Negative(no-pie) +-Create a dynamically linked position independent executable. ++Create a position independent executable. + + static-pie + Driver RejectNegative Negative(pie) +diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h +index ff2e880b1fa..bafde149202 100644 +--- a/gcc/config/gnu-user.h ++++ b/gcc/config/gnu-user.h +@@ -51,13 +51,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define GNU_USER_TARGET_STARTFILE_SPEC \ + "%{shared:; \ + pg|p|profile:%{static-pie:grcrt1.o%s;:gcrt1.o%s}; \ +- static:crt1.o%s; \ +- static-pie:rcrt1.o%s; \ ++ static|static-pie:%{" PIE_SPEC ":rcrt1.o%s;:crt1.o%s}; \ + " PIE_SPEC ":Scrt1.o%s; \ + :crt1.o%s} " \ + GNU_USER_TARGET_CRTI " \ +- %{static:crtbeginT.o%s; \ +- shared|static-pie|" PIE_SPEC ":crtbeginS.o%s; \ ++ %{shared|" PIE_SPEC ":crtbeginS.o%s; \ ++ static:crtbeginT.o%s; \ + :crtbegin.o%s} \ + %{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_start_preinit.o%s; \ +@@ -73,11 +72,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + GNU userspace "finalizer" file, `crtn.o'. */ + + #define GNU_USER_TARGET_ENDFILE_SPEC \ +- "%{!static:%{fvtable-verify=none:%s; \ ++ "%{static|static-pie:; \ ++ fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_end_preinit.o%s; \ +- fvtable-verify=std:vtv_end.o%s}} \ +- %{static:crtend.o%s; \ +- shared|static-pie|" PIE_SPEC ":crtendS.o%s; \ ++ fvtable-verify=std:vtv_end.o%s} \ ++ %{shared|" PIE_SPEC ":crtendS.o%s; \ + :crtend.o%s} " \ + GNU_USER_TARGET_CRTN " " \ + CRTOFFLOADEND +@@ -106,7 +105,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define LIB_SPEC GNU_USER_TARGET_LIB_SPEC + + #if defined(HAVE_LD_EH_FRAME_HDR) +-#define LINK_EH_SPEC "%{!static|static-pie:--eh-frame-hdr} " ++#define LINK_EH_SPEC "%{!static|" PIE_SPEC ":--eh-frame-hdr} " + #endif + + #define GNU_USER_TARGET_LINK_GCC_C_SEQUENCE_SPEC \ +diff --git a/gcc/gcc.c b/gcc/gcc.c +index e6887590ae2..df6e3965f13 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -907,7 +907,7 @@ proper position among the other output files. */ + #define NO_FPIE_AND_FPIC_SPEC NO_FPIE_SPEC "|" NO_FPIC_SPEC + #define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;" + #else +-#define PIE_SPEC "pie" ++#define PIE_SPEC "pie|static-pie" + #define FPIE1_SPEC "fpie" + #define NO_FPIE1_SPEC FPIE1_SPEC ":;" + #define FPIE2_SPEC "fPIE" +@@ -931,12 +931,12 @@ proper position among the other output files. */ + #ifndef LINK_PIE_SPEC + #ifdef HAVE_LD_PIE + #ifndef LD_PIE_SPEC +-#define LD_PIE_SPEC "-pie" ++#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}" + #endif + #else + #define LD_PIE_SPEC "" + #endif +-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} " ++#define LINK_PIE_SPEC "%{shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} " + #endif + + #ifndef LINK_BUILDID_SPEC diff --git a/patches/gcc-10.3.0/0005-libstdc-futex-time64.diff b/patches/gcc-10.3.0/0005-libstdc-futex-time64.diff new file mode 100644 index 0000000..8681574 --- /dev/null +++ b/patches/gcc-10.3.0/0005-libstdc-futex-time64.diff @@ -0,0 +1,30 @@ +diff --git a/libstdc++-v3/src/c++11/futex.cc b/libstdc++-v3/src/c++11/futex.cc +index 698737d9b21..230d32574c6 100644 +--- a/libstdc++-v3/src/c++11/futex.cc ++++ b/libstdc++-v3/src/c++11/futex.cc +@@ -46,13 +46,23 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + + namespace + { ++#if defined(SYS_futex_time64) && SYS_futex_time64 != SYS_futex ++ typedef struct ++ { ++ long tv_sec; ++ long tv_nsec; ++ } sys_timespec; ++#else ++ typedef struct timespec sys_timespec; ++#endif ++ + // Return the relative duration from (now_s + now_ns) to (abs_s + abs_ns) + // as a timespec. +- struct timespec ++ sys_timespec + relative_timespec(chrono::seconds abs_s, chrono::nanoseconds abs_ns, + time_t now_s, long now_ns) + { +- struct timespec rt; ++ sys_timespec rt; + + // Did we already time out? + if (now_s > abs_s.count()) diff --git a/patches/gcc-10.3.0/0006-m68k-sqrt.diff b/patches/gcc-10.3.0/0006-m68k-sqrt.diff new file mode 100644 index 0000000..e2b6eca --- /dev/null +++ b/patches/gcc-10.3.0/0006-m68k-sqrt.diff @@ -0,0 +1,20 @@ +diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md +index 8e35357ea23..65c8b10b3eb 100644 +--- a/gcc/config/m68k/m68k.md ++++ b/gcc/config/m68k/m68k.md +@@ -4174,13 +4174,13 @@ + (define_expand "sqrt2" + [(set (match_operand:FP 0 "nonimmediate_operand" "") + (sqrt:FP (match_operand:FP 1 "general_operand" "")))] +- "TARGET_HARD_FLOAT" ++ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU" + "") + + (define_insn "sqrt2_68881" + [(set (match_operand:FP 0 "nonimmediate_operand" "=f") + (sqrt:FP (match_operand:FP 1 "general_operand" "fm")))] +- "TARGET_68881" ++ "TARGET_68881 && TARGET_68040" + { + if (FP_REG_P (operands[1])) + return "fsqrt%.x %1,%0"; diff --git a/patches/gcc-11.2.0/0001-ssp_nonshared.diff b/patches/gcc-11.2.0/0001-ssp_nonshared.diff new file mode 100644 index 0000000..0b991d9 --- /dev/null +++ b/patches/gcc-11.2.0/0001-ssp_nonshared.diff @@ -0,0 +1,14 @@ +diff --git a/gcc/gcc.c b/gcc/gcc.c +index 7837553958b..3c81c5798d8 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -980,7 +980,8 @@ proper position among the other output files. */ + #ifndef LINK_SSP_SPEC + #ifdef TARGET_LIBC_PROVIDES_SSP + #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ +- "|fstack-protector-strong|fstack-protector-explicit:}" ++ "|fstack-protector-strong|fstack-protector-explicit" \ ++ ":-lssp_nonshared}" + #else + #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ + "|fstack-protector-strong|fstack-protector-explicit" \ diff --git a/patches/gcc-11.2.0/0002-posix_memalign.diff b/patches/gcc-11.2.0/0002-posix_memalign.diff new file mode 100644 index 0000000..1d80096 --- /dev/null +++ b/patches/gcc-11.2.0/0002-posix_memalign.diff @@ -0,0 +1,30 @@ +diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h +index 1b0bfe37852..d7b2b19bb3c 100644 +--- a/gcc/config/i386/pmm_malloc.h ++++ b/gcc/config/i386/pmm_malloc.h +@@ -27,12 +27,13 @@ + #include + + /* We can't depend on since the prototype of posix_memalign +- may not be visible. */ ++ may not be visible and we can't pollute the namespace either. */ + #ifndef __cplusplus +-extern int posix_memalign (void **, size_t, size_t); ++extern int _mm_posix_memalign (void **, size_t, size_t) + #else +-extern "C" int posix_memalign (void **, size_t, size_t) throw (); ++extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw () + #endif ++__asm__("posix_memalign"); + + static __inline void * + _mm_malloc (size_t __size, size_t __alignment) +@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment) + return malloc (__size); + if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4)) + __alignment = sizeof (void *); +- if (posix_memalign (&__ptr, __alignment, __size) == 0) ++ if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0) + return __ptr; + else + return NULL; diff --git a/patches/gcc-11.2.0/0003-j2.diff b/patches/gcc-11.2.0/0003-j2.diff new file mode 100644 index 0000000..245b910 --- /dev/null +++ b/patches/gcc-11.2.0/0003-j2.diff @@ -0,0 +1,346 @@ +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 357b0bed067..528add999f2 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -556,7 +556,7 @@ s390*-*-*) + extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h" + ;; + # Note the 'l'; we need to be able to match e.g. "shle" or "shl". +-sh[123456789lbe]*-*-* | sh-*-*) ++sh[123456789lbej]*-*-* | sh-*-*) + cpu_type=sh + extra_options="${extra_options} fused-madd.opt" + extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o" +@@ -3202,18 +3202,18 @@ s390x-ibm-tpf*) + extra_options="${extra_options} s390/tpf.opt" + tmake_file="${tmake_file} s390/t-s390" + ;; +-sh-*-elf* | sh[12346l]*-*-elf* | \ +- sh-*-linux* | sh[2346lbe]*-*-linux* | \ ++sh-*-elf* | sh[12346lj]*-*-elf* | \ ++ sh-*-linux* | sh[2346lbej]*-*-linux* | \ + sh-*-netbsdelf* | shl*-*-netbsdelf*) + tmake_file="${tmake_file} sh/t-sh sh/t-elf" + if test x${with_endian} = x; then + case ${target} in +- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;; ++ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;; + shbe-*-* | sheb-*-*) with_endian=big,little ;; + sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;; + shl* | sh*-*-linux* | \ + sh-superh-elf) with_endian=little,big ;; +- sh[1234]*-*-*) with_endian=big ;; ++ sh[j1234]*-*-*) with_endian=big ;; + *) with_endian=big,little ;; + esac + fi +@@ -3280,6 +3280,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;; + sh2a*) sh_cpu_target=sh2a ;; + sh2e*) sh_cpu_target=sh2e ;; ++ shj2*) sh_cpu_target=shj2;; + sh2*) sh_cpu_target=sh2 ;; + *) sh_cpu_target=sh1 ;; + esac +@@ -3301,7 +3302,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \ + sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \ + sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \ +- sh3e | sh3 | sh2e | sh2 | sh1) ;; ++ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;; + "") sh_cpu_default=${sh_cpu_target} ;; + *) echo "with_cpu=$with_cpu not supported"; exit 1 ;; + esac +@@ -3310,9 +3311,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + case ${target} in + sh[1234]*) sh_multilibs=${sh_cpu_target} ;; + sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;; +- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;; ++ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;; + sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;; +- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;; ++ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;; + esac + if test x$with_fp = xno; then + sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`" +@@ -3327,7 +3328,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + m1 | m2 | m2e | m3 | m3e | \ + m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\ + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \ +- m2a | m2a-single | m2a-single-only | m2a-nofpu) ++ m2a | m2a-single | m2a-single-only | m2a-nofpu | \ ++ mj2) + # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition + # It is passed to MULTIILIB_OPTIONS verbatim. + TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}" +@@ -3344,7 +3346,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + done + TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'` + if test x${enable_incomplete_targets} = xyes ; then +- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1" ++ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1" + fi + tm_file="$tm_file ./sysroot-suffix.h" + tmake_file="$tmake_file t-sysroot-suffix" +@@ -5175,6 +5177,8 @@ case "${target}" in + ;; + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al) + ;; ++ mj2) ++ ;; + *) + echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2 + echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2 +@@ -5385,7 +5389,7 @@ case ${target} in + tmake_file="${cpu_type}/t-${cpu_type} ${tmake_file}" + ;; + +- sh[123456ble]*-*-* | sh-*-*) ++ sh[123456blej]*-*-* | sh-*-*) + c_target_objs="${c_target_objs} sh-c.o" + cxx_target_objs="${cxx_target_objs} sh-c.o" + ;; +diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c +index 1564109c942..798c1c1c1a3 100644 +--- a/gcc/config/sh/sh.c ++++ b/gcc/config/sh/sh.c +@@ -686,6 +686,7 @@ parse_validate_atomic_model_option (const char* str) + model_names[sh_atomic_model::hard_llcs] = "hard-llcs"; + model_names[sh_atomic_model::soft_tcb] = "soft-tcb"; + model_names[sh_atomic_model::soft_imask] = "soft-imask"; ++ model_names[sh_atomic_model::hard_cas] = "hard-cas"; + + const char* model_cdef_names[sh_atomic_model::num_models]; + model_cdef_names[sh_atomic_model::none] = "NONE"; +@@ -693,6 +694,7 @@ parse_validate_atomic_model_option (const char* str) + model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS"; + model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB"; + model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK"; ++ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS"; + + sh_atomic_model ret; + ret.type = sh_atomic_model::none; +@@ -771,6 +773,9 @@ got_mode_name:; + if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE) + err_ret ("cannot use atomic model %s in user mode", ret.name); + ++ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2) ++ err_ret ("atomic model %s is only available J2 targets", ret.name); ++ + return ret; + + #undef err_ret +@@ -827,6 +832,8 @@ sh_option_override (void) + sh_cpu = PROCESSOR_SH2E; + if (TARGET_SH2A) + sh_cpu = PROCESSOR_SH2A; ++ if (TARGET_SHJ2) ++ sh_cpu = PROCESSOR_SHJ2; + if (TARGET_SH3) + sh_cpu = PROCESSOR_SH3; + if (TARGET_SH3E) +diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h +index d2280e2ffe6..3a54a896721 100644 +--- a/gcc/config/sh/sh.h ++++ b/gcc/config/sh/sh.h +@@ -85,6 +85,7 @@ extern int code_for_indirect_jump_scratch; + #define SUPPORT_SH4_SINGLE 1 + #define SUPPORT_SH2A 1 + #define SUPPORT_SH2A_SINGLE 1 ++#define SUPPORT_SHJ2 1 + #endif + + #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) +@@ -117,6 +118,7 @@ extern int code_for_indirect_jump_scratch; + #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) + #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) + #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) ++#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2) + + #if SUPPORT_SH1 + #define SUPPORT_SH2 1 +@@ -124,6 +126,7 @@ extern int code_for_indirect_jump_scratch; + #if SUPPORT_SH2 + #define SUPPORT_SH3 1 + #define SUPPORT_SH2A_NOFPU 1 ++#define SUPPORT_SHJ2 1 + #endif + #if SUPPORT_SH3 + #define SUPPORT_SH4_NOFPU 1 +@@ -156,7 +159,7 @@ extern int code_for_indirect_jump_scratch; + #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ + | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ + | MASK_HARD_SH4 | MASK_FPU_SINGLE \ +- | MASK_FPU_SINGLE_ONLY) ++ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2) + + /* This defaults us to big-endian. */ + #ifndef TARGET_ENDIAN_DEFAULT +@@ -231,7 +234,8 @@ extern int code_for_indirect_jump_scratch; + %{m2a-single:--isa=sh2a} \ + %{m2a-single-only:--isa=sh2a} \ + %{m2a-nofpu:--isa=sh2a-nofpu} \ +-%{m4al:-dsp}" ++%{m4al:-dsp} \ ++%{mj2:-isa=j2}" + + #define ASM_SPEC SH_ASM_SPEC + +@@ -347,6 +351,7 @@ struct sh_atomic_model + hard_llcs, + soft_tcb, + soft_imask, ++ hard_cas, + + num_models + }; +@@ -390,6 +395,9 @@ extern const sh_atomic_model& selected_atomic_model (void); + #define TARGET_ATOMIC_SOFT_IMASK \ + (selected_atomic_model ().type == sh_atomic_model::soft_imask) + ++#define TARGET_ATOMIC_HARD_CAS \ ++ (selected_atomic_model ().type == sh_atomic_model::hard_cas) ++ + #endif // __cplusplus + + #define SUBTARGET_OVERRIDE_OPTIONS (void) 0 +@@ -1484,7 +1492,7 @@ extern bool current_function_interrupt; + + /* Nonzero if the target supports dynamic shift instructions + like shad and shld. */ +-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) ++#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2) + + /* The cost of using the dynamic shift insns (shad, shld) are the same + if they are available. If they are not available a library function will +@@ -1747,6 +1755,7 @@ enum processor_type { + PROCESSOR_SH2, + PROCESSOR_SH2E, + PROCESSOR_SH2A, ++ PROCESSOR_SHJ2, + PROCESSOR_SH3, + PROCESSOR_SH3E, + PROCESSOR_SH4, +diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt +index b4755a812f3..0989a1c18da 100644 +--- a/gcc/config/sh/sh.opt ++++ b/gcc/config/sh/sh.opt +@@ -65,6 +65,10 @@ m2e + Target RejectNegative Condition(SUPPORT_SH2E) + Generate SH2e code. + ++mj2 ++Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2) ++Generate J2 code. ++ + m3 + Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) + Generate SH3 code. +diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md +index 2b43f8edb86..118fc5d06db 100644 +--- a/gcc/config/sh/sync.md ++++ b/gcc/config/sh/sync.md +@@ -240,6 +240,9 @@ + || (TARGET_SH4A && mode == SImode && !TARGET_ATOMIC_STRICT)) + atomic_insn = gen_atomic_compare_and_swap_hard (old_val, mem, + exp_val, new_val); ++ else if (TARGET_ATOMIC_HARD_CAS && mode == SImode) ++ atomic_insn = gen_atomic_compare_and_swap_cas (old_val, mem, ++ exp_val, new_val); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic_compare_and_swap_soft_gusa (old_val, mem, + exp_val, new_val); +@@ -306,6 +309,57 @@ + } + [(set_attr "length" "14")]) + ++(define_expand "atomic_compare_and_swapsi_cas" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "r")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{ ++ rtx mem = gen_rtx_REG (SImode, 0); ++ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0))); ++ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_insn "shj2_cas" ++ [(set (match_operand:SI 0 "register_operand" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "register_operand" "=r") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "0")] ++ UNSPECV_CMPXCHG_1)) ++ (set (reg:SI T_REG) ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))] ++ "TARGET_ATOMIC_HARD_CAS" ++ "cas.l %2,%0,@%1" ++ [(set_attr "length" "2")] ++) ++ ++(define_expand "atomic_compare_and_swapqi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ ++(define_expand "atomic_compare_and_swaphi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ + ;; The QIHImode llcs patterns modify the address register of the memory + ;; operand. In order to express that, we have to open code the memory + ;; operand. Initially the insn is expanded like every other atomic insn +diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh +index 888f8ff7f25..29fd6ae45fd 100644 +--- a/gcc/config/sh/t-sh ++++ b/gcc/config/sh/t-sh +@@ -50,7 +50,8 @@ MULTILIB_MATCHES = $(shell \ + m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \ + m2a-single,m2a-single-only \ + m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \ +- m4,m4-100,m4-200,m4-300,m4a; do \ ++ m4,m4-100,m4-200,m4-300,m4a \ ++ mj2; do \ + subst= ; \ + for lib in `echo $$abi|tr , ' '` ; do \ + if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \ +@@ -63,9 +64,9 @@ MULTILIB_MATCHES = $(shell \ + + # SH1 and SH2A support big endian only. + ifeq ($(DEFAULT_ENDIAN),ml) +-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + else +-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + endif + + MULTILIB_OSDIRNAMES = \ +@@ -87,7 +88,8 @@ MULTILIB_OSDIRNAMES = \ + m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \ + m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \ + m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \ +- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al ++ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \ ++ mj2=!j2 + + $(out_object_file): gt-sh.h + gt-sh.h : s-gtype ; @true diff --git a/patches/gcc-11.2.0/0004-static-pie.diff b/patches/gcc-11.2.0/0004-static-pie.diff new file mode 100644 index 0000000..232dc5d --- /dev/null +++ b/patches/gcc-11.2.0/0004-static-pie.diff @@ -0,0 +1,92 @@ +diff --git a/gcc/common.opt b/gcc/common.opt +index a75b44ee47e..7c564818b49 100644 +--- a/gcc/common.opt ++++ b/gcc/common.opt +@@ -3473,11 +3473,11 @@ Driver + + no-pie + Driver RejectNegative Negative(shared) +-Don't create a dynamically linked position independent executable. ++Don't create a position independent executable. + + pie + Driver RejectNegative Negative(no-pie) +-Create a dynamically linked position independent executable. ++Create a position independent executable. + + static-pie + Driver RejectNegative Negative(pie) +diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h +index 5ebbf42a13d..bb907d8e89a 100644 +--- a/gcc/config/gnu-user.h ++++ b/gcc/config/gnu-user.h +@@ -51,13 +51,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define GNU_USER_TARGET_STARTFILE_SPEC \ + "%{shared:; \ + pg|p|profile:%{static-pie:grcrt1.o%s;:gcrt1.o%s}; \ +- static:crt1.o%s; \ +- static-pie:rcrt1.o%s; \ ++ static|static-pie:%{" PIE_SPEC ":rcrt1.o%s;:crt1.o%s}; \ + " PIE_SPEC ":Scrt1.o%s; \ + :crt1.o%s} " \ + GNU_USER_TARGET_CRTI " \ +- %{static:crtbeginT.o%s; \ +- shared|static-pie|" PIE_SPEC ":crtbeginS.o%s; \ ++ %{shared|" PIE_SPEC ":crtbeginS.o%s; \ ++ static:crtbeginT.o%s; \ + :crtbegin.o%s} \ + %{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_start_preinit.o%s; \ +@@ -73,11 +72,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + GNU userspace "finalizer" file, `crtn.o'. */ + + #define GNU_USER_TARGET_ENDFILE_SPEC \ +- "%{!static:%{fvtable-verify=none:%s; \ ++ "%{static|static-pie:; \ ++ fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_end_preinit.o%s; \ +- fvtable-verify=std:vtv_end.o%s}} \ +- %{static:crtend.o%s; \ +- shared|static-pie|" PIE_SPEC ":crtendS.o%s; \ ++ fvtable-verify=std:vtv_end.o%s} \ ++ %{shared|" PIE_SPEC ":crtendS.o%s; \ + :crtend.o%s} " \ + GNU_USER_TARGET_CRTN " " \ + CRTOFFLOADEND +@@ -106,7 +105,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define LIB_SPEC GNU_USER_TARGET_LIB_SPEC + + #if defined(HAVE_LD_EH_FRAME_HDR) +-#define LINK_EH_SPEC "%{!static|static-pie:--eh-frame-hdr} " ++#define LINK_EH_SPEC "%{!static|" PIE_SPEC ":--eh-frame-hdr} " + #endif + + #define GNU_USER_TARGET_LINK_GCC_C_SEQUENCE_SPEC \ +diff --git a/gcc/gcc.c b/gcc/gcc.c +index 3c81c5798d8..cd96eac5d12 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -1010,7 +1010,7 @@ proper position among the other output files. */ + #define NO_FPIE_AND_FPIC_SPEC NO_FPIE_SPEC "|" NO_FPIC_SPEC + #define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;" + #else +-#define PIE_SPEC "pie" ++#define PIE_SPEC "pie|static-pie" + #define FPIE1_SPEC "fpie" + #define NO_FPIE1_SPEC FPIE1_SPEC ":;" + #define FPIE2_SPEC "fPIE" +@@ -1034,12 +1034,12 @@ proper position among the other output files. */ + #ifndef LINK_PIE_SPEC + #ifdef HAVE_LD_PIE + #ifndef LD_PIE_SPEC +-#define LD_PIE_SPEC "-pie" ++#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}" + #endif + #else + #define LD_PIE_SPEC "" + #endif +-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} " ++#define LINK_PIE_SPEC "%{shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} " + #endif + + #ifndef LINK_BUILDID_SPEC diff --git a/patches/gcc-11.2.0/0005-m68k-sqrt.diff b/patches/gcc-11.2.0/0005-m68k-sqrt.diff new file mode 100644 index 0000000..652efb1 --- /dev/null +++ b/patches/gcc-11.2.0/0005-m68k-sqrt.diff @@ -0,0 +1,20 @@ +diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md +index 59a456cd496..dbfddea41bd 100644 +--- a/gcc/config/m68k/m68k.md ++++ b/gcc/config/m68k/m68k.md +@@ -4174,13 +4174,13 @@ + (define_expand "sqrt2" + [(set (match_operand:FP 0 "nonimmediate_operand" "") + (sqrt:FP (match_operand:FP 1 "general_operand" "")))] +- "TARGET_HARD_FLOAT" ++ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU" + "") + + (define_insn "sqrt2_68881" + [(set (match_operand:FP 0 "nonimmediate_operand" "=f") + (sqrt:FP (match_operand:FP 1 "general_operand" "fm")))] +- "TARGET_68881" ++ "TARGET_68881 && TARGET_68040" + { + if (FP_REG_P (operands[1])) + return "fsqrt%.x %1,%0"; diff --git a/patches/gcc-4.2.1/0001-musl.diff b/patches/gcc-4.2.1/0001-musl.diff new file mode 100644 index 0000000..0feb672 --- /dev/null +++ b/patches/gcc-4.2.1/0001-musl.diff @@ -0,0 +1,360 @@ +diff --git a/config.sub b/config.sub +index fab0aa3..b83660a 100755 +--- a/config.sub ++++ b/config.sub +@@ -120,7 +120,7 @@ esac + # Here we must recognize all the valid KERNEL-OS combinations. + maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` + case $maybe_os in +- nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | \ ++ nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | linux-musl* | \ + uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | \ + storm-chaos* | os2-emx* | rtmk-nova*) + os=-$maybe_os +@@ -1211,7 +1211,7 @@ case $os in + | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ + | -chorusos* | -chorusrdb* \ + | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ +- | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* \ ++ | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* | -linux-musl* \ + | -uxpv* | -beos* | -mpeix* | -udk* \ + | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \ + | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \ +diff --git a/fixincludes/mkfixinc.sh b/fixincludes/mkfixinc.sh +index ef048f7..f1cb8a5 100755 +--- a/fixincludes/mkfixinc.sh ++++ b/fixincludes/mkfixinc.sh +@@ -28,7 +28,8 @@ case $machine in + powerpc-*-eabi* | \ + powerpc-*-rtems* | \ + powerpcle-*-eabisim* | \ +- powerpcle-*-eabi* ) ++ powerpcle-*-eabi* | \ ++ *-musl* ) + # IF there is no include fixing, + # THEN create a no-op fixer and exit + (echo "#! /bin/sh" ; echo "exit 0" ) > ${target} +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 9a142e2..25136b7 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -468,11 +468,14 @@ case ${target} in + esac + tmake_file="t-slibgcc-elf-ver t-linux" + case ${target} in ++ *-*-*musl*) ++ tm_defines="${tm_defines} UCLIBC_DEFAULT=0 MUSL_DEFAULT=1" ++ ;; + *-*-*uclibc*) +- tm_defines="${tm_defines} UCLIBC_DEFAULT=1" ++ tm_defines="${tm_defines} UCLIBC_DEFAULT=1 MUSL_DEFAULT=0" + ;; + *) +- tm_defines="${tm_defines} UCLIBC_DEFAULT=0" ++ tm_defines="${tm_defines} UCLIBC_DEFAULT=0 MUSL_DEFAULT=0" + ;; + esac + # Assume that glibc or uClibc are being used and so __cxa_atexit is provided. +diff --git a/gcc/config/arm/linux-eabi.h b/gcc/config/arm/linux-eabi.h +index 6612f74..f2ce735 100644 +--- a/gcc/config/arm/linux-eabi.h ++++ b/gcc/config/arm/linux-eabi.h +@@ -55,6 +55,23 @@ + #undef GLIBC_DYNAMIC_LINKER + #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.3" + ++/* For ARM musl currently supports four dynamic linkers: ++ - ld-musl-arm.so.1 - for the EABI-derived soft-float ABI ++ - ld-musl-armhf.so.1 - for the EABI-derived hard-float ABI ++ - ld-musl-armeb.so.1 - for the EABI-derived soft-float ABI, EB ++ - ld-musl-armebhf.so.1 - for the EABI-derived hard-float ABI, EB ++ musl does not support the legacy OABI mode. ++ All the dynamic linkers live in /lib. ++ We default to soft-float, EL. */ ++#undef MUSL_DYNAMIC_LINKER ++#if TARGET_BIG_ENDIAN_DEFAULT ++#define MUSL_DYNAMIC_LINKER_E "%{mlittle-endian:;:eb}" ++#else ++#define MUSL_DYNAMIC_LINKER_E "%{mbig-endian:eb}" ++#endif ++#define MUSL_DYNAMIC_LINKER \ ++ "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}.so.1" ++ + /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to + use the GNU/Linux version, not the generic BPABI version. */ + #undef LINK_SPEC +diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h +index 7eb2395..213b586 100644 +--- a/gcc/config/i386/linux.h ++++ b/gcc/config/i386/linux.h +@@ -103,6 +103,9 @@ Boston, MA 02110-1301, USA. */ + #define LINK_EMULATION "elf_i386" + #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" + ++#undef MUSL_DYNAMIC_LINKER ++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-i386.so.1" ++ + #undef SUBTARGET_EXTRA_SPECS + #define SUBTARGET_EXTRA_SPECS \ + { "link_emulation", LINK_EMULATION },\ +diff --git a/gcc/config/i386/linux64.h b/gcc/config/i386/linux64.h +index cc8ed16..f0f025e 100644 +--- a/gcc/config/i386/linux64.h ++++ b/gcc/config/i386/linux64.h +@@ -52,6 +52,13 @@ Boston, MA 02110-1301, USA. */ + #define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2" + #define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2" + ++#undef MUSL_DYNAMIC_LINKER32 ++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-i386.so.1" ++#undef MUSL_DYNAMIC_LINKER64 ++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-x86_64.so.1" ++#undef MUSL_DYNAMIC_LINKERX32 ++#define MUSL_DYNAMIC_LINKERX32 "/lib/ld-musl-x32.so.1" ++ + #undef LINK_SPEC + #define LINK_SPEC "%{!m32:-m elf_x86_64} %{m32:-m elf_i386} \ + %{shared:-shared} \ +diff --git a/gcc/config/linux.h b/gcc/config/linux.h +index 59e3e85..1967b46 100644 +--- a/gcc/config/linux.h ++++ b/gcc/config/linux.h +@@ -102,10 +102,12 @@ Boston, MA 02110-1301, USA. */ + /* Determine which dynamic linker to use depending on whether GLIBC or + uClibc is the default C library and whether -muclibc or -mglibc has + been passed to change the default. */ +-#if UCLIBC_DEFAULT +-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:%{muclibc:%e-mglibc and -muclibc used together}" G ";:" U "}" ++#if MUSL_DEFAULT ++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";muclibc:" U ";:" M "}" ++#elif UCLIBC_DEFAULT ++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";mmusl:" M ";:" U "}" + #else +-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:%{mglibc:%e-mglibc and -muclibc used together}" U ";:" G "}" ++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mmusl:" M ";muclibc:" U ";:" G "}" + #endif + + /* For most targets the following definitions suffice; +@@ -115,15 +117,89 @@ Boston, MA 02110-1301, USA. */ + #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0" + #define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0" + #define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0" ++/* Should be redefined for each target that supports musl. */ ++#define MUSL_DYNAMIC_LINKER "/dev/null" ++#define MUSL_DYNAMIC_LINKER32 "/dev/null" ++#define MUSL_DYNAMIC_LINKER64 "/dev/null" ++#define MUSL_DYNAMIC_LINKERX32 "/dev/null" ++ + #define LINUX_DYNAMIC_LINKER \ +- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER) ++ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER, MUSL_DYNAMIC_LINKER) + #define LINUX_DYNAMIC_LINKER32 \ +- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32) ++ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32, MUSL_DYNAMIC_LINKER32) + #define LINUX_DYNAMIC_LINKER64 \ +- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64) ++ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64, MUSL_DYNAMIC_LINKER64) + + /* Determine whether the entire c99 runtime + is present in the runtime library. */ + #define TARGET_C99_FUNCTIONS (OPTION_GLIBC) + + #define TARGET_POSIX_IO ++ ++/* musl avoids problematic includes by rearranging the include directories. ++ * Unfortunately, this is mostly duplicated from cppdefault.c */ ++#if MUSL_DEFAULT ++#define INCLUDE_DEFAULTS_MUSL_GPP \ ++ { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, 0, 0 }, \ ++ { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, 0, 1 }, \ ++ { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, 0, 0 }, ++ ++#ifdef LOCAL_INCLUDE_DIR ++#define INCLUDE_DEFAULTS_MUSL_LOCAL \ ++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, \ ++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 }, ++#else ++#define INCLUDE_DEFAULTS_MUSL_LOCAL ++#endif ++ ++#ifdef PREFIX_INCLUDE_DIR ++#define INCLUDE_DEFAULTS_MUSL_PREFIX \ ++ { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0}, ++#else ++#define INCLUDE_DEFAULTS_MUSL_PREFIX ++#endif ++ ++#ifdef CROSS_INCLUDE_DIR ++#define INCLUDE_DEFAULTS_MUSL_CROSS \ ++ { CROSS_INCLUDE_DIR, "GCC", 0, 0, 0, 0}, ++#else ++#define INCLUDE_DEFAULTS_MUSL_CROSS ++#endif ++ ++#ifdef TOOL_INCLUDE_DIR ++#define INCLUDE_DEFAULTS_MUSL_TOOL \ ++ { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1, 0, 0}, ++#else ++#define INCLUDE_DEFAULTS_MUSL_TOOL ++#endif ++ ++#ifdef NATIVE_SYSTEM_HEADER_DIR ++#define INCLUDE_DEFAULTS_MUSL_NATIVE \ ++ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 }, \ ++ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 0 }, ++#else ++#define INCLUDE_DEFAULTS_MUSL_NATIVE ++#endif ++ ++#if defined (CROSS_DIRECTORY_STRUCTURE) && !defined (TARGET_SYSTEM_ROOT) ++# undef INCLUDE_DEFAULTS_MUSL_LOCAL ++# define INCLUDE_DEFAULTS_MUSL_LOCAL ++# undef INCLUDE_DEFAULTS_MUSL_NATIVE ++# define INCLUDE_DEFAULTS_MUSL_NATIVE ++#else ++# undef INCLUDE_DEFAULTS_MUSL_CROSS ++# define INCLUDE_DEFAULTS_MUSL_CROSS ++#endif ++ ++#undef INCLUDE_DEFAULTS ++#define INCLUDE_DEFAULTS \ ++ { \ ++ INCLUDE_DEFAULTS_MUSL_GPP \ ++ INCLUDE_DEFAULTS_MUSL_PREFIX \ ++ INCLUDE_DEFAULTS_MUSL_CROSS \ ++ INCLUDE_DEFAULTS_MUSL_TOOL \ ++ INCLUDE_DEFAULTS_MUSL_NATIVE \ ++ { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 }, \ ++ { 0, 0, 0, 0, 0, 0 } \ ++ } ++#endif +diff --git a/gcc/config/linux.opt b/gcc/config/linux.opt +index 3f615bb..31fb21b 100644 +--- a/gcc/config/linux.opt ++++ b/gcc/config/linux.opt +@@ -27,3 +27,7 @@ Use uClibc instead of GNU libc + mglibc + Target RejectNegative Report InverseMask(UCLIBC, GLIBC) Var(linux_uclibc) VarExists + Use GNU libc instead of uClibc ++ ++mmusl ++Target RejectNegative Report Var(linux_musl) ++Use musl C library +diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h +index ff268d4..97bfc38 100644 +--- a/gcc/config/mips/linux.h ++++ b/gcc/config/mips/linux.h +@@ -179,3 +179,9 @@ Boston, MA 02110-1301, USA. */ + %{profile:-lc_p} %{!profile: -lc}}" + + #define MD_UNWIND_SUPPORT "config/mips/linux-unwind.h" ++ ++#undef MUSL_DYNAMIC_LINKER32 ++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-mips%{EL:el}%{msoft-float:-sf}.so.1" ++#undef MUSL_DYNAMIC_LINKER64 ++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-mips64%{EL:el}%{msoft-float:-sf}.so.1" ++#define MUSL_DYNAMIC_LINKERN32 "/lib/ld-musl-mipsn32%{EL:el}%{msoft-float:-sf}.so.1" +diff --git a/gcc/config/sh/linux-unwind.h b/gcc/config/sh/linux-unwind.h +index de84a77..98d1661 100644 +--- a/gcc/config/sh/linux-unwind.h ++++ b/gcc/config/sh/linux-unwind.h +@@ -80,10 +80,10 @@ shmedia_fallback_frame_state (struct _Unwind_Context *context, + && (*(unsigned long *) (pc+11) == 0x6ff0fff0)) + { + struct rt_sigframe { +- struct siginfo *pinfo; ++ siginfo_t *pinfo; + void *puc; +- struct siginfo info; +- struct ucontext uc; ++ siginfo_t info; ++ ucontext_t uc; + } *rt_ = context->cfa; + /* The void * cast is necessary to avoid an aliasing warning. + The aliasing warning is correct, but should not be a problem +@@ -179,8 +179,8 @@ sh_fallback_frame_state (struct _Unwind_Context *context, + && (*(unsigned short *) (pc+14) == 0x00ad)))) + { + struct rt_sigframe { +- struct siginfo info; +- struct ucontext uc; ++ siginfo_t info; ++ ucontext_t uc; + } *rt_ = context->cfa; + /* The void * cast is necessary to avoid an aliasing warning. + The aliasing warning is correct, but should not be a problem +diff --git a/gcc/config/sh/linux.h b/gcc/config/sh/linux.h +index 94c3166..306a08c 100644 +--- a/gcc/config/sh/linux.h ++++ b/gcc/config/sh/linux.h +@@ -48,6 +48,29 @@ Boston, MA 02110-1301, USA. */ + + #define TARGET_ASM_FILE_END file_end_indicate_exec_stack + ++#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN ++#define MUSL_DYNAMIC_LINKER_E "%{mb:eb}" ++#else ++#define MUSL_DYNAMIC_LINKER_E "%{!ml:eb}" ++#endif ++ ++#if TARGET_CPU_DEFAULT & ( MASK_HARD_SH2A_DOUBLE | MASK_SH4 ) ++/* "-nofpu" if any nofpu option is specified */ ++#define MUSL_DYNAMIC_LINKER_FP \ ++ "%{m1|m2|m2a-nofpu|m3|m4-nofpu|m4-100-nofpu|m4-200-nofpu|m4-300-nofpu|" \ ++ "m4-340|m4-400|m4-500|m4al|m5-32media-nofpu|m5-64media-nofpu|" \ ++ "m5-compact-nofpu:-nofpu}" ++#else ++/* "-nofpu" if none of the hard fpu options are specified */ ++#define MUSL_DYNAMIC_LINKER_FP \ ++ "%{m2a|m4|m4-100|m4-200|m4-300|m4a|m5-32media|m5-64media|m5-compact:;:-nofpu}" ++#endif ++ ++#undef MUSL_DYNAMIC_LINKER ++#define MUSL_DYNAMIC_LINKER \ ++ "/lib/ld-musl-sh" MUSL_DYNAMIC_LINKER_E MUSL_DYNAMIC_LINKER_FP \ ++ "%{mfdpic:-fdpic}.so.1" ++ + #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" + + #undef SUBTARGET_LINK_EMUL_SUFFIX +diff --git a/gcc/unwind-dw2-fde-glibc.c b/gcc/unwind-dw2-fde-glibc.c +index 25bf2bb..59f7615 100644 +--- a/gcc/unwind-dw2-fde-glibc.c ++++ b/gcc/unwind-dw2-fde-glibc.c +@@ -49,7 +49,7 @@ + #include "gthr.h" + + #if !defined(inhibit_libc) && defined(HAVE_LD_EH_FRAME_HDR) \ +- && (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ > 2) \ ++ && (!defined(__GLIBC__) || __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ > 2) \ + || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 2 && defined(DT_CONFIG))) + + #ifndef __RELOC_POINTER +diff --git a/libstdc++-v3/config/os/generic/os_defines.h b/libstdc++-v3/config/os/generic/os_defines.h +index bcc533c..a9bfded 100644 +--- a/libstdc++-v3/config/os/generic/os_defines.h ++++ b/libstdc++-v3/config/os/generic/os_defines.h +@@ -38,4 +38,9 @@ + // System-specific #define, typedefs, corrections, etc, go here. This + // file will come before all others. + ++// Disable the weak reference logic in gthr.h for os/generic because it ++// is broken on every platform unless there is implementation specific ++// workaround in gthr-posix.h and at link-time for static linking. ++#define _GLIBCXX_GTHREAD_USE_WEAK 0 ++ + #endif +diff --git a/libstdc++-v3/configure.host b/libstdc++-v3/configure.host +index 441eb4c..37e80ab 100644 +--- a/libstdc++-v3/configure.host ++++ b/libstdc++-v3/configure.host +@@ -210,6 +210,9 @@ case "${host_os}" in + freebsd*) + os_include_dir="os/bsd/freebsd" + ;; ++ linux-musl*) ++ os_include_dir="os/generic" ++ ;; + gnu* | linux* | kfreebsd*-gnu | knetbsd*-gnu) + if [ "$uclibc" = "yes" ]; then + os_include_dir="os/uclibc" diff --git a/patches/gcc-4.2.1/0002-weakbugs.diff b/patches/gcc-4.2.1/0002-weakbugs.diff new file mode 100644 index 0000000..8485912 --- /dev/null +++ b/patches/gcc-4.2.1/0002-weakbugs.diff @@ -0,0 +1,62 @@ +diff --git a/gcc/cgraph.c b/gcc/cgraph.c +index fcdc02e..db04afd 100644 +--- a/gcc/cgraph.c ++++ b/gcc/cgraph.c +@@ -1169,7 +1169,7 @@ cgraph_function_body_availability (struct cgraph_node *node) + inline and offline) having same side effect characteristics as + good optimization is what this optimization is about. */ + +- else if (!(*targetm.binds_local_p) (node->decl) ++ else if ((DECL_WEAK (node->decl) || !(*targetm.binds_local_p) (node->decl)) + && !DECL_COMDAT (node->decl) && !DECL_EXTERNAL (node->decl)) + avail = AVAIL_OVERWRITABLE; + else avail = AVAIL_AVAILABLE; +@@ -1190,7 +1190,8 @@ cgraph_variable_initializer_availability (struct cgraph_varpool_node *node) + /* If the variable can be overwritten, return OVERWRITABLE. Takes + care of at least two notable extensions - the COMDAT variables + used to share template instantiations in C++. */ +- if (!(*targetm.binds_local_p) (node->decl) && !DECL_COMDAT (node->decl)) ++ if ((DECL_WEAK (node->decl) || !(*targetm.binds_local_p) (node->decl)) ++ && !DECL_COMDAT (node->decl)) + return AVAIL_OVERWRITABLE; + return AVAIL_AVAILABLE; + } +diff --git a/gcc/ipa-inline.c b/gcc/ipa-inline.c +index 84ef830..73d9fcc 100644 +--- a/gcc/ipa-inline.c ++++ b/gcc/ipa-inline.c +@@ -300,7 +300,7 @@ cgraph_default_inline_p (struct cgraph_node *n, const char **reason) + + if (n->inline_decl) + decl = n->inline_decl; +- if (!DECL_INLINE (decl)) ++ if (!DECL_INLINE (decl) || DECL_WEAK (decl)) + { + if (reason) + *reason = N_("function not inlinable"); +diff --git a/gcc/ipa-pure-const.c b/gcc/ipa-pure-const.c +index fdaff50..1bfd577 100644 +--- a/gcc/ipa-pure-const.c ++++ b/gcc/ipa-pure-const.c +@@ -512,7 +512,7 @@ analyze_function (struct cgraph_node *fn) + /* If this function does not return normally or does not bind local, + do not touch this unless it has been marked as const or pure by the + front end. */ +- if (TREE_THIS_VOLATILE (decl) ++ if (TREE_THIS_VOLATILE (decl) || DECL_WEAK (decl) + || !targetm.binds_local_p (decl)) + { + l->pure_const_state = IPA_NEITHER; +diff --git a/gcc/tree-inline.c b/gcc/tree-inline.c +index 1c0b79b..5a3ba7e 100644 +--- a/gcc/tree-inline.c ++++ b/gcc/tree-inline.c +@@ -1522,6 +1522,8 @@ inlinable_function_p (tree fn) + else if (!DECL_INLINE (fn) && !flag_unit_at_a_time) + inlinable = false; + ++ else if (DECL_WEAK (fn)) ++ inlinable = false; + else if (inline_forbidden_p (fn)) + { + /* See if we should warn about uninlinable functions. Previously, diff --git a/patches/gcc-4.2.1/0003-shbitrot.diff b/patches/gcc-4.2.1/0003-shbitrot.diff new file mode 100644 index 0000000..b4291a9 --- /dev/null +++ b/patches/gcc-4.2.1/0003-shbitrot.diff @@ -0,0 +1,79 @@ +diff --git a/config.sub b/config.sub +index b83660a..b81ad9a 100755 +--- a/config.sub ++++ b/config.sub +@@ -277,7 +277,7 @@ case $basic_machine in + | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \ + | pyramid \ + | score \ +- | sh | sh[1234] | sh[24]a | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \ ++ | sh | sh[1234] | sh[24]a | sh[23]e | sh[1234]eb | sheb | shbe | shle | sh[1234]le | sh3ele \ + | sh64 | sh64le \ + | sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \ + | sparcv8 | sparcv9 | sparcv9b | sparcv9v \ +@@ -358,7 +358,7 @@ case $basic_machine in + | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \ + | pyramid-* \ + | romp-* | rs6000-* \ +- | sh-* | sh[1234]-* | sh[24]a-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \ ++ | sh-* | sh[1234]-* | sh[24]a-* | sh[23]e-* | sh[1234]eb-* | sheb-* | shbe-* \ + | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \ + | sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \ + | sparclite-* \ +@@ -1127,7 +1127,7 @@ case $basic_machine in + we32k) + basic_machine=we32k-att + ;; +- sh[1234] | sh[24]a | sh[34]eb | sh[1234]le | sh[23]ele) ++ sh[1234] | sh[24]a | sh[1234]eb | sh[1234]le | sh[23]ele) + basic_machine=sh-unknown + ;; + sparc | sparcv8 | sparcv9 | sparcv9b | sparcv9v) +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 25136b7..3779369 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -1967,7 +1967,7 @@ score-*-elf) + ;; + sh-*-elf* | sh[12346l]*-*-elf* | sh*-*-kaos* | \ + sh-*-symbianelf* | sh[12346l]*-*-symbianelf* | \ +- sh-*-linux* | sh[346lbe]*-*-linux* | \ ++ sh-*-linux* | sh[12346lbe]*-*-linux* | \ + sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \ + sh64-*-netbsd* | sh64l*-*-netbsd*) + tmake_file="${tmake_file} sh/t-sh sh/t-elf" +@@ -2911,7 +2911,7 @@ case "${target}" in + esac + ;; + +- sh[123456ble]-*-* | sh-*-*) ++ sh[123456ble]*-*-* | sh-*-*) + supported_defaults="cpu" + case "`echo $with_cpu | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ_ abcdefghijklmnopqrstuvwxyz- | sed s/sh/m/`" in + "" | m1 | m2 | m2e | m3 | m3e | m4 | m4-single | m4-single-only | m4-nofpu ) +diff --git a/gcc/configure b/gcc/configure +index a248d39..c12f091 100755 +--- a/gcc/configure ++++ b/gcc/configure +@@ -14564,7 +14564,7 @@ foo: .long 25 + tls_first_minor=14 + tls_as_opt="-m64 -Aesame --fatal-warnings" + ;; +- sh-*-* | sh[34]-*-*) ++ sh-*-* | sh[123456789lbe]*-*-*) + conftest_s=' + .section ".tdata","awT",@progbits + foo: .long 25 +diff --git a/gcc/configure.ac b/gcc/configure.ac +index b6c394c..1414f9e 100644 +--- a/gcc/configure.ac ++++ b/gcc/configure.ac +@@ -2538,7 +2538,7 @@ foo: .long 25 + tls_first_minor=14 + tls_as_opt="-m64 -Aesame --fatal-warnings" + ;; +- sh-*-* | sh[34]-*-*) ++ sh-*-* | sh[123456789lbe]*-*-*) + conftest_s=' + .section ".tdata","awT",@progbits + foo: .long 25 diff --git a/patches/gcc-4.2.1/0005-staticpie.diff b/patches/gcc-4.2.1/0005-staticpie.diff new file mode 100644 index 0000000..41a0975 --- /dev/null +++ b/patches/gcc-4.2.1/0005-staticpie.diff @@ -0,0 +1,28 @@ +diff --git a/gcc/config/linux.h b/gcc/config/linux.h +index 1967b46..39f8cb4 100644 +--- a/gcc/config/linux.h ++++ b/gcc/config/linux.h +@@ -41,8 +41,8 @@ Boston, MA 02110-1301, USA. */ + #undef STARTFILE_SPEC + #if defined HAVE_LD_PIE + #define STARTFILE_SPEC \ +- "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \ +- crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s}" ++ "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:%{static:rcrt1.o%s;:Scrt1.o%s};:crt1.o%s}} \ ++ crti.o%s %{shared|pie:crtbeginS.o%s;static:crtbeginT.o%s;:crtbegin.o%s}" + #else + #define STARTFILE_SPEC \ + "%{!shared: %{pg|p|profile:gcrt1.o%s;:crt1.o%s}} \ +diff --git a/gcc/gcc.c b/gcc/gcc.c +index 0b5ee4b..41d17a5 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -684,7 +684,7 @@ proper position among the other output files. */ + + #ifndef LINK_PIE_SPEC + #ifdef HAVE_LD_PIE +-#define LINK_PIE_SPEC "%{pie:-pie} " ++#define LINK_PIE_SPEC "%{pie:-pie %{static:--no-dynamic-linker}} " + #else + #define LINK_PIE_SPEC "%{pie:} " + #endif diff --git a/patches/gcc-4.2.1/0006-defaultpie.diff b/patches/gcc-4.2.1/0006-defaultpie.diff new file mode 100644 index 0000000..049aebd --- /dev/null +++ b/patches/gcc-4.2.1/0006-defaultpie.diff @@ -0,0 +1,39 @@ +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 3779369..a6d95ca 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -3101,6 +3101,12 @@ case ${target} in + ;; + esac + ++case "x${enable_default_pie}" in ++xyes) ++ tm_defines="${tm_defines} ENABLE_DEFAULT_PIE" ++ ;; ++esac ++ + t= + all_defaults="abi cpu arch tune schedule float mode fpu divide" + for option in $all_defaults +diff --git a/gcc/gcc.c b/gcc/gcc.c +index 41d17a5..b9bbcb6 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -846,8 +846,16 @@ static const char *const multilib_defaults_raw[] = MULTILIB_DEFAULTS; + #define GOMP_SELF_SPECS "%{fopenmp: -pthread}" + #endif + ++#ifndef PIE_SELF_SPECS ++#ifdef ENABLE_DEFAULT_PIE ++#define PIE_SELF_SPECS "%{shared|pie|r|nostdlib|nopie|no-pie:;:-pie} %{fpic|fPIC|fpie|fPIE|fno-pic|fno-PIC|fno-pie|fno-PIE|D__KERNEL__:;:-fPIE}" ++#else ++#define PIE_SELF_SPECS "" ++#endif ++#endif ++ + static const char *const driver_self_specs[] = { +- DRIVER_SELF_SPECS, GOMP_SELF_SPECS ++ DRIVER_SELF_SPECS, GOMP_SELF_SPECS, PIE_SELF_SPECS + }; + + #ifndef OPTION_DEFAULT_SPECS diff --git a/patches/gcc-4.2.1/0008-crossbug.diff b/patches/gcc-4.2.1/0008-crossbug.diff new file mode 100644 index 0000000..4e9b38e --- /dev/null +++ b/patches/gcc-4.2.1/0008-crossbug.diff @@ -0,0 +1,13 @@ +diff --git a/Makefile.in b/Makefile.in +index 218d8fa..45c1764 100644 +--- a/Makefile.in ++++ b/Makefile.in +@@ -208,7 +208,7 @@ BASE_TARGET_EXPORTS = \ + RANLIB="$(RANLIB_FOR_TARGET)"; export RANLIB; \ + STRIP="$(STRIP_FOR_TARGET)"; export STRIP; \ + WINDRES="$(WINDRES_FOR_TARGET)"; export WINDRES; \ +- $(RPATH_ENVVAR)=`echo "$(HOST_LIB_PATH)$(TARGET_LIB_PATH)$$$(RPATH_ENVVAR)" | sed 's,::*,:,g;s,^:*,,;s,:*$$,,'`; export $(RPATH_ENVVAR); ++ $(RPATH_ENVVAR)=`echo "$(HOST_LIB_PATH)$$$(RPATH_ENVVAR)" | sed 's,::*,:,g;s,^:*,,;s,:*$$,,'`; export $(RPATH_ENVVAR); + + RAW_CXX_TARGET_EXPORTS = \ + $(BASE_TARGET_EXPORTS) \ diff --git a/patches/gcc-4.2.1/0009-shdiv.diff b/patches/gcc-4.2.1/0009-shdiv.diff new file mode 100644 index 0000000..9b872eb --- /dev/null +++ b/patches/gcc-4.2.1/0009-shdiv.diff @@ -0,0 +1,15 @@ +diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h +index fc4e1f2..1a4cf00 100644 +--- a/gcc/config/sh/sh.h ++++ b/gcc/config/sh/sh.h +@@ -649,10 +649,6 @@ do { \ + /* ??? Should we use the integer SHmedia function instead? */ \ + else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) \ + sh_div_strategy = SH_DIV_CALL_FP; \ +- /* SH1 .. SH3 cores often go into small-footprint systems, so \ +- default to the smallest implementation available. */ \ +- else if (TARGET_SH2) /* ??? EXPERIMENTAL */ \ +- sh_div_strategy = SH_DIV_CALL_TABLE; \ + else \ + sh_div_strategy = SH_DIV_CALL_DIV1; \ + } \ diff --git a/patches/gcc-4.2.1/0010-gnuinline.diff b/patches/gcc-4.2.1/0010-gnuinline.diff new file mode 100644 index 0000000..2d90171 --- /dev/null +++ b/patches/gcc-4.2.1/0010-gnuinline.diff @@ -0,0 +1,53 @@ +diff --git a/gcc/toplev.c b/gcc/toplev.c +index 53fcdfe..85f8504 100644 +--- a/gcc/toplev.c ++++ b/gcc/toplev.c +@@ -533,6 +533,7 @@ read_integral_parameter (const char *p, const char *pname, const int defval) + + #if GCC_VERSION < 3004 || !defined (__cplusplus) + ++#if 0 + /* Given X, an unsigned number, return the largest int Y such that 2**Y <= X. + If X is 0, return -1. */ + +@@ -582,6 +583,7 @@ exact_log2 (unsigned HOST_WIDE_INT x) + return floor_log2 (x); + #endif + } ++#endif + + #endif /* GCC_VERSION < 3004 || !defined (__cplusplus) */ + +diff --git a/gcc/toplev.h b/gcc/toplev.h +index c935f7e..c8d4bb2 100644 +--- a/gcc/toplev.h ++++ b/gcc/toplev.h +@@ -152,10 +152,10 @@ extern void decode_d_option (const char *); + extern bool fast_math_flags_set_p (void); + + /* Return log2, or -1 if not exact. */ +-extern int exact_log2 (unsigned HOST_WIDE_INT); ++//extern int exact_log2 (unsigned HOST_WIDE_INT); + + /* Return floor of log2, with -1 for zero. */ +-extern int floor_log2 (unsigned HOST_WIDE_INT); ++//extern int floor_log2 (unsigned HOST_WIDE_INT); + + /* Inline versions of the above for speed. */ + #if GCC_VERSION >= 3004 +@@ -170,13 +170,13 @@ extern int floor_log2 (unsigned HOST_WIDE_INT); + # define CTZ_HWI __builtin_ctz + # endif + +-extern inline int ++static inline int + floor_log2 (unsigned HOST_WIDE_INT x) + { + return x ? HOST_BITS_PER_WIDE_INT - 1 - (int) CLZ_HWI (x) : -1; + } + +-extern inline int ++static inline int + exact_log2 (unsigned HOST_WIDE_INT x) + { + return x == (x & -x) && x ? (int) CTZ_HWI (x) : -1; diff --git a/patches/gcc-4.2.1/0011-inhibitlibc.diff b/patches/gcc-4.2.1/0011-inhibitlibc.diff new file mode 100644 index 0000000..324a047 --- /dev/null +++ b/patches/gcc-4.2.1/0011-inhibitlibc.diff @@ -0,0 +1,36 @@ +diff -ru gcc-core/gcc/config/sh/linux-unwind.h gcc-core/gcc/config/sh/linux-unwind.h +--- gcc-core/gcc/config/sh/linux-unwind.h 2005-06-28 20:45:37.000000000 -0500 ++++ gcc-core/gcc/config/sh/linux-unwind.h 2008-02-06 17:41:12.000000000 -0600 +@@ -26,6 +26,8 @@ + the Free Software Foundation, 51 Franklin Street, Fifth Floor, + Boston, MA 02110-1301, USA. */ + ++#ifndef inhibit_libc ++ + /* Do code reading to identify a signal frame, and set the frame + state data appropriately. See unwind-dw2.c for the structs. */ + +@@ -249,3 +251,5 @@ + return _URC_NO_REASON; + } + #endif /* defined (__SH5__) */ ++ ++#endif +diff -ru gcc-core/gcc/config/alpha/linux-unwind.h gcc-core2/gcc/config/alpha/linux-unwind.h +--- gcc-core/gcc/config/alpha/linux-unwind.h 2005-06-24 20:22:41.000000000 -0500 ++++ gcc-core2/gcc/config/alpha/linux-unwind.h 2010-01-10 20:05:56.000000000 -0600 +@@ -26,6 +26,8 @@ + the Free Software Foundation, 51 Franklin Street, Fifth Floor, + Boston, MA 02110-1301, USA. */ + ++#ifndef inhibit_libc ++ + /* Do code reading to identify a signal frame, and set the frame + state data appropriately. See unwind-dw2.c for the structs. */ + +@@ -80,3 +82,5 @@ + fs->retaddr_column = 64; + return _URC_NO_REASON; + } ++ ++#endif diff --git a/patches/gcc-4.2.1/0012-shletls.diff b/patches/gcc-4.2.1/0012-shletls.diff new file mode 100644 index 0000000..4837685 --- /dev/null +++ b/patches/gcc-4.2.1/0012-shletls.diff @@ -0,0 +1,10 @@ +--- gcc-4.2.1/gcc/config/sh/sh.c.orig 2015-11-06 04:41:52.683021006 +0000 ++++ gcc-4.2.1/gcc/config/sh/sh.c 2015-11-06 04:42:00.643020520 +0000 +@@ -8343,6 +8343,7 @@ nonpic_symbol_mentioned_p (rtx x) + || XINT (x, 1) == UNSPEC_GOTPLT + || XINT (x, 1) == UNSPEC_GOTTPOFF + || XINT (x, 1) == UNSPEC_DTPOFF ++ || XINT (x, 1) == UNSPEC_TPOFF + || XINT (x, 1) == UNSPEC_PLT)) + return 0; + diff --git a/patches/gcc-5.3.0/0001-musl.diff b/patches/gcc-5.3.0/0001-musl.diff new file mode 100644 index 0000000..5675aab --- /dev/null +++ b/patches/gcc-5.3.0/0001-musl.diff @@ -0,0 +1,892 @@ +diff --git a/fixincludes/mkfixinc.sh b/fixincludes/mkfixinc.sh +index 6653fed..0d96c8c 100755 +--- a/fixincludes/mkfixinc.sh ++++ b/fixincludes/mkfixinc.sh +@@ -19,7 +19,8 @@ case $machine in + powerpc-*-eabi* | \ + powerpc-*-rtems* | \ + powerpcle-*-eabisim* | \ +- powerpcle-*-eabi* ) ++ powerpcle-*-eabi* | \ ++ *-musl* ) + # IF there is no include fixing, + # THEN create a no-op fixer and exit + (echo "#! /bin/sh" ; echo "exit 0" ) > ${target} +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 3ede69b..d9eb8cf 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -575,7 +575,7 @@ case ${target} in + esac + + # Common C libraries. +-tm_defines="$tm_defines LIBC_GLIBC=1 LIBC_UCLIBC=2 LIBC_BIONIC=3" ++tm_defines="$tm_defines LIBC_GLIBC=1 LIBC_UCLIBC=2 LIBC_BIONIC=3 LIBC_MUSL=4" + + # 32-bit x86 processors supported by --with-arch=. Each processor + # MUST be separated by exactly one space. +@@ -720,6 +720,9 @@ case ${target} in + *-*-*uclibc*) + tm_defines="$tm_defines DEFAULT_LIBC=LIBC_UCLIBC" + ;; ++ *-*-*musl*) ++ tm_defines="$tm_defines DEFAULT_LIBC=LIBC_MUSL" ++ ;; + *) + tm_defines="$tm_defines DEFAULT_LIBC=LIBC_GLIBC" + ;; +diff --git a/gcc/config/aarch64/aarch64-linux.h b/gcc/config/aarch64/aarch64-linux.h +index ba7fc3b..1600a32 100644 +--- a/gcc/config/aarch64/aarch64-linux.h ++++ b/gcc/config/aarch64/aarch64-linux.h +@@ -23,6 +23,9 @@ + + #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1" + ++#undef MUSL_DYNAMIC_LINKER ++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1" ++ + #undef ASAN_CC1_SPEC + #define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}" + +diff --git a/gcc/config/alpha/linux.h b/gcc/config/alpha/linux.h +index c567f43..475ea06 100644 +--- a/gcc/config/alpha/linux.h ++++ b/gcc/config/alpha/linux.h +@@ -61,10 +61,14 @@ along with GCC; see the file COPYING3. If not see + #define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC) + #define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC) + #define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC) ++#undef OPTION_MUSL ++#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL) + #else + #define OPTION_GLIBC (linux_libc == LIBC_GLIBC) + #define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC) + #define OPTION_BIONIC (linux_libc == LIBC_BIONIC) ++#undef OPTION_MUSL ++#define OPTION_MUSL (linux_libc == LIBC_MUSL) + #endif + + /* Determine what functions are present at the runtime; +diff --git a/gcc/config/arm/linux-eabi.h b/gcc/config/arm/linux-eabi.h +index e9d65dc..f12e6bd 100644 +--- a/gcc/config/arm/linux-eabi.h ++++ b/gcc/config/arm/linux-eabi.h +@@ -77,6 +77,23 @@ + %{mfloat-abi=soft*:" GLIBC_DYNAMIC_LINKER_SOFT_FLOAT "} \ + %{!mfloat-abi=*:" GLIBC_DYNAMIC_LINKER_DEFAULT "}" + ++/* For ARM musl currently supports four dynamic linkers: ++ - ld-musl-arm.so.1 - for the EABI-derived soft-float ABI ++ - ld-musl-armhf.so.1 - for the EABI-derived hard-float ABI ++ - ld-musl-armeb.so.1 - for the EABI-derived soft-float ABI, EB ++ - ld-musl-armebhf.so.1 - for the EABI-derived hard-float ABI, EB ++ musl does not support the legacy OABI mode. ++ All the dynamic linkers live in /lib. ++ We default to soft-float, EL. */ ++#undef MUSL_DYNAMIC_LINKER ++#if TARGET_BIG_ENDIAN_DEFAULT ++#define MUSL_DYNAMIC_LINKER_E "%{mlittle-endian:;:eb}" ++#else ++#define MUSL_DYNAMIC_LINKER_E "%{mbig-endian:eb}" ++#endif ++#define MUSL_DYNAMIC_LINKER \ ++ "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}.so.1" ++ + /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to + use the GNU/Linux version, not the generic BPABI version. */ + #undef LINK_SPEC +diff --git a/gcc/config/glibc-stdint.h b/gcc/config/glibc-stdint.h +index 3fc67dc..98f4f04 100644 +--- a/gcc/config/glibc-stdint.h ++++ b/gcc/config/glibc-stdint.h +@@ -22,6 +22,12 @@ a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + ++/* Systems using musl libc should use this header and make sure ++ OPTION_MUSL is defined correctly before using the TYPE macros. */ ++#ifndef OPTION_MUSL ++#define OPTION_MUSL 0 ++#endif ++ + #define SIG_ATOMIC_TYPE "int" + + #define INT8_TYPE "signed char" +@@ -43,12 +49,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define UINT_LEAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "long long unsigned int") + + #define INT_FAST8_TYPE "signed char" +-#define INT_FAST16_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "int") +-#define INT_FAST32_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "int") ++#define INT_FAST16_TYPE (LONG_TYPE_SIZE == 64 && !OPTION_MUSL ? "long int" : "int") ++#define INT_FAST32_TYPE (LONG_TYPE_SIZE == 64 && !OPTION_MUSL ? "long int" : "int") + #define INT_FAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "long long int") + #define UINT_FAST8_TYPE "unsigned char" +-#define UINT_FAST16_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "unsigned int") +-#define UINT_FAST32_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "unsigned int") ++#define UINT_FAST16_TYPE (LONG_TYPE_SIZE == 64 && !OPTION_MUSL ? "long unsigned int" : "unsigned int") ++#define UINT_FAST32_TYPE (LONG_TYPE_SIZE == 64 && !OPTION_MUSL ? "long unsigned int" : "unsigned int") + #define UINT_FAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "long long unsigned int") + + #define INTPTR_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "int") +diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h +index a100963..385aefd 100644 +--- a/gcc/config/i386/linux.h ++++ b/gcc/config/i386/linux.h +@@ -21,3 +21,6 @@ along with GCC; see the file COPYING3. If not see + + #define GNU_USER_LINK_EMULATION "elf_i386" + #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" ++ ++#undef MUSL_DYNAMIC_LINKER ++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-i386.so.1" +diff --git a/gcc/config/i386/linux64.h b/gcc/config/i386/linux64.h +index a27d3be..e300480 100644 +--- a/gcc/config/i386/linux64.h ++++ b/gcc/config/i386/linux64.h +@@ -30,3 +30,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2" + #define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2" + #define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2" ++ ++#undef MUSL_DYNAMIC_LINKER32 ++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-i386.so.1" ++#undef MUSL_DYNAMIC_LINKER64 ++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-x86_64.so.1" ++#undef MUSL_DYNAMIC_LINKERX32 ++#define MUSL_DYNAMIC_LINKERX32 "/lib/ld-musl-x32.so.1" +diff --git a/gcc/config/linux.h b/gcc/config/linux.h +index 857389a..7bc87ab 100644 +--- a/gcc/config/linux.h ++++ b/gcc/config/linux.h +@@ -32,10 +32,14 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC) + #define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC) + #define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC) ++#undef OPTION_MUSL ++#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL) + #else + #define OPTION_GLIBC (linux_libc == LIBC_GLIBC) + #define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC) + #define OPTION_BIONIC (linux_libc == LIBC_BIONIC) ++#undef OPTION_MUSL ++#define OPTION_MUSL (linux_libc == LIBC_MUSL) + #endif + + #define GNU_USER_TARGET_OS_CPP_BUILTINS() \ +@@ -50,21 +54,25 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + } while (0) + + /* Determine which dynamic linker to use depending on whether GLIBC or +- uClibc or Bionic is the default C library and whether +- -muclibc or -mglibc or -mbionic has been passed to change the default. */ ++ uClibc or Bionic or musl is the default C library and whether ++ -muclibc or -mglibc or -mbionic or -mmusl has been passed to change ++ the default. */ + +-#define CHOOSE_DYNAMIC_LINKER1(LIBC1, LIBC2, LIBC3, LD1, LD2, LD3) \ +- "%{" LIBC2 ":" LD2 ";:%{" LIBC3 ":" LD3 ";:" LD1 "}}" ++#define CHOOSE_DYNAMIC_LINKER1(LIBC1, LIBC2, LIBC3, LIBC4, LD1, LD2, LD3, LD4) \ ++ "%{" LIBC2 ":" LD2 ";:%{" LIBC3 ":" LD3 ";:%{" LIBC4 ":" LD4 ";:" LD1 "}}}" + + #if DEFAULT_LIBC == LIBC_GLIBC +-#define CHOOSE_DYNAMIC_LINKER(G, U, B) \ +- CHOOSE_DYNAMIC_LINKER1 ("mglibc", "muclibc", "mbionic", G, U, B) ++#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \ ++ CHOOSE_DYNAMIC_LINKER1 ("mglibc", "muclibc", "mbionic", "mmusl", G, U, B, M) + #elif DEFAULT_LIBC == LIBC_UCLIBC +-#define CHOOSE_DYNAMIC_LINKER(G, U, B) \ +- CHOOSE_DYNAMIC_LINKER1 ("muclibc", "mglibc", "mbionic", U, G, B) ++#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \ ++ CHOOSE_DYNAMIC_LINKER1 ("muclibc", "mglibc", "mbionic", "mmusl", U, G, B, M) + #elif DEFAULT_LIBC == LIBC_BIONIC +-#define CHOOSE_DYNAMIC_LINKER(G, U, B) \ +- CHOOSE_DYNAMIC_LINKER1 ("mbionic", "mglibc", "muclibc", B, G, U) ++#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \ ++ CHOOSE_DYNAMIC_LINKER1 ("mbionic", "mglibc", "muclibc", "mmusl", B, G, U, M) ++#elif DEFAULT_LIBC == LIBC_MUSL ++#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \ ++ CHOOSE_DYNAMIC_LINKER1 ("mmusl", "mglibc", "muclibc", "mbionic", M, G, U, B) + #else + #error "Unsupported DEFAULT_LIBC" + #endif /* DEFAULT_LIBC */ +@@ -81,24 +89,100 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker" + #define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64" + #define BIONIC_DYNAMIC_LINKERX32 "/system/bin/linkerx32" ++/* Should be redefined for each target that supports musl. */ ++#define MUSL_DYNAMIC_LINKER "/dev/null" ++#define MUSL_DYNAMIC_LINKER32 "/dev/null" ++#define MUSL_DYNAMIC_LINKER64 "/dev/null" ++#define MUSL_DYNAMIC_LINKERX32 "/dev/null" + + #define GNU_USER_DYNAMIC_LINKER \ + CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER, \ +- BIONIC_DYNAMIC_LINKER) ++ BIONIC_DYNAMIC_LINKER, MUSL_DYNAMIC_LINKER) + #define GNU_USER_DYNAMIC_LINKER32 \ + CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32, \ +- BIONIC_DYNAMIC_LINKER32) ++ BIONIC_DYNAMIC_LINKER32, MUSL_DYNAMIC_LINKER32) + #define GNU_USER_DYNAMIC_LINKER64 \ + CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64, \ +- BIONIC_DYNAMIC_LINKER64) ++ BIONIC_DYNAMIC_LINKER64, MUSL_DYNAMIC_LINKER64) + #define GNU_USER_DYNAMIC_LINKERX32 \ + CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKERX32, UCLIBC_DYNAMIC_LINKERX32, \ +- BIONIC_DYNAMIC_LINKERX32) ++ BIONIC_DYNAMIC_LINKERX32, MUSL_DYNAMIC_LINKERX32) + + /* Whether we have Bionic libc runtime */ + #undef TARGET_HAS_BIONIC + #define TARGET_HAS_BIONIC (OPTION_BIONIC) + ++/* musl avoids problematic includes by rearranging the include directories. ++ * Unfortunately, this is mostly duplicated from cppdefault.c */ ++#if DEFAULT_LIBC == LIBC_MUSL ++#define INCLUDE_DEFAULTS_MUSL_GPP \ ++ { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, \ ++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, \ ++ { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, \ ++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 }, \ ++ { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, \ ++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, ++ ++#ifdef LOCAL_INCLUDE_DIR ++#define INCLUDE_DEFAULTS_MUSL_LOCAL \ ++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, \ ++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 }, ++#else ++#define INCLUDE_DEFAULTS_MUSL_LOCAL ++#endif ++ ++#ifdef PREFIX_INCLUDE_DIR ++#define INCLUDE_DEFAULTS_MUSL_PREFIX \ ++ { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0}, ++#else ++#define INCLUDE_DEFAULTS_MUSL_PREFIX ++#endif ++ ++#ifdef CROSS_INCLUDE_DIR ++#define INCLUDE_DEFAULTS_MUSL_CROSS \ ++ { CROSS_INCLUDE_DIR, "GCC", 0, 0, 0, 0}, ++#else ++#define INCLUDE_DEFAULTS_MUSL_CROSS ++#endif ++ ++#ifdef TOOL_INCLUDE_DIR ++#define INCLUDE_DEFAULTS_MUSL_TOOL \ ++ { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1, 0, 0}, ++#else ++#define INCLUDE_DEFAULTS_MUSL_TOOL ++#endif ++ ++#ifdef NATIVE_SYSTEM_HEADER_DIR ++#define INCLUDE_DEFAULTS_MUSL_NATIVE \ ++ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 }, \ ++ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 0 }, ++#else ++#define INCLUDE_DEFAULTS_MUSL_NATIVE ++#endif ++ ++#if defined (CROSS_DIRECTORY_STRUCTURE) && !defined (TARGET_SYSTEM_ROOT) ++# undef INCLUDE_DEFAULTS_MUSL_LOCAL ++# define INCLUDE_DEFAULTS_MUSL_LOCAL ++# undef INCLUDE_DEFAULTS_MUSL_NATIVE ++# define INCLUDE_DEFAULTS_MUSL_NATIVE ++#else ++# undef INCLUDE_DEFAULTS_MUSL_CROSS ++# define INCLUDE_DEFAULTS_MUSL_CROSS ++#endif ++ ++#undef INCLUDE_DEFAULTS ++#define INCLUDE_DEFAULTS \ ++ { \ ++ INCLUDE_DEFAULTS_MUSL_GPP \ ++ INCLUDE_DEFAULTS_MUSL_PREFIX \ ++ INCLUDE_DEFAULTS_MUSL_CROSS \ ++ INCLUDE_DEFAULTS_MUSL_TOOL \ ++ INCLUDE_DEFAULTS_MUSL_NATIVE \ ++ { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 }, \ ++ { 0, 0, 0, 0, 0, 0 } \ ++ } ++#endif ++ + #if (DEFAULT_LIBC == LIBC_UCLIBC) && defined (SINGLE_LIBC) /* uClinux */ + /* This is a *uclinux* target. We don't define below macros to normal linux + versions, because doing so would require *uclinux* targets to include +diff --git a/gcc/config/linux.opt b/gcc/config/linux.opt +index c054338..ef055a7 100644 +--- a/gcc/config/linux.opt ++++ b/gcc/config/linux.opt +@@ -28,5 +28,9 @@ Target Report RejectNegative Var(linux_libc,LIBC_GLIBC) Negative(muclibc) + Use GNU C library + + muclibc +-Target Report RejectNegative Var(linux_libc,LIBC_UCLIBC) Negative(mbionic) ++Target Report RejectNegative Var(linux_libc,LIBC_UCLIBC) Negative(mmusl) + Use uClibc C library ++ ++mmusl ++Target Report RejectNegative Var(linux_libc,LIBC_MUSL) Negative(mbionic) ++Use musl C library +diff --git a/gcc/config/microblaze/linux.h b/gcc/config/microblaze/linux.h +index 655a70f..a8a3f3e 100644 +--- a/gcc/config/microblaze/linux.h ++++ b/gcc/config/microblaze/linux.h +@@ -28,10 +28,20 @@ + #undef TLS_NEEDS_GOT + #define TLS_NEEDS_GOT 1 + +-#define DYNAMIC_LINKER "/lib/ld.so.1" ++#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" ++ ++#if TARGET_BIG_ENDIAN_DEFAULT == 0 /* LE */ ++#define MUSL_DYNAMIC_LINKER_E "%{mbig-endian:;:el}" ++#else ++#define MUSL_DYNAMIC_LINKER_E "%{mlittle-endian:el}" ++#endif ++ ++#undef MUSL_DYNAMIC_LINKER ++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-microblaze" MUSL_DYNAMIC_LINKER_E ".so.1" ++ + #undef SUBTARGET_EXTRA_SPECS + #define SUBTARGET_EXTRA_SPECS \ +- { "dynamic_linker", DYNAMIC_LINKER } ++ { "dynamic_linker", GNU_USER_DYNAMIC_LINKER } + + #undef LINK_SPEC + #define LINK_SPEC "%{shared:-shared} \ +diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h +index 91df261..fb358e2 100644 +--- a/gcc/config/mips/linux.h ++++ b/gcc/config/mips/linux.h +@@ -37,7 +37,13 @@ along with GCC; see the file COPYING3. If not see + #define UCLIBC_DYNAMIC_LINKERN32 \ + "%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}" + ++#undef MUSL_DYNAMIC_LINKER32 ++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-mips%{EL:el}%{msoft-float:-sf}.so.1" ++#undef MUSL_DYNAMIC_LINKER64 ++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-mips64%{EL:el}%{msoft-float:-sf}.so.1" ++#define MUSL_DYNAMIC_LINKERN32 "/lib/ld-musl-mipsn32%{EL:el}%{msoft-float:-sf}.so.1" ++ + #define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32" + #define GNU_USER_DYNAMIC_LINKERN32 \ + CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKERN32, UCLIBC_DYNAMIC_LINKERN32, \ +- BIONIC_DYNAMIC_LINKERN32) ++ BIONIC_DYNAMIC_LINKERN32, MUSL_DYNAMIC_LINKERN32) +diff --git a/gcc/config/rs6000/linux.h b/gcc/config/rs6000/linux.h +index fe0ebd6..a68ff69 100644 +--- a/gcc/config/rs6000/linux.h ++++ b/gcc/config/rs6000/linux.h +@@ -30,10 +30,14 @@ + #define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC) + #define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC) + #define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC) ++#undef OPTION_MUSL ++#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL) + #else + #define OPTION_GLIBC (linux_libc == LIBC_GLIBC) + #define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC) + #define OPTION_BIONIC (linux_libc == LIBC_BIONIC) ++#undef OPTION_MUSL ++#define OPTION_MUSL (linux_libc == LIBC_MUSL) + #endif + + /* Determine what functions are present at the runtime; +diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h +index 0879e7e..6a7d435 100644 +--- a/gcc/config/rs6000/linux64.h ++++ b/gcc/config/rs6000/linux64.h +@@ -299,10 +299,14 @@ extern int dot_symbols; + #define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC) + #define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC) + #define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC) ++#undef OPTION_MUSL ++#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL) + #else + #define OPTION_GLIBC (linux_libc == LIBC_GLIBC) + #define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC) + #define OPTION_BIONIC (linux_libc == LIBC_BIONIC) ++#undef OPTION_MUSL ++#define OPTION_MUSL (linux_libc == LIBC_MUSL) + #endif + + /* Determine what functions are present at the runtime; +@@ -365,17 +369,23 @@ extern int dot_symbols; + #endif + #define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0" + #define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0" ++#define MUSL_DYNAMIC_LINKER32 \ ++ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" ++#define MUSL_DYNAMIC_LINKER64 \ ++ "/lib/ld-musl-powerpc64" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" + #if DEFAULT_LIBC == LIBC_UCLIBC +-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}" ++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";:%{mmusl:" M ";:" U "}}" + #elif DEFAULT_LIBC == LIBC_GLIBC +-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:" U ";:" G "}" ++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{muclibc:" U ";:%{mmusl:" M ";:" G "}}" ++#elif DEFAULT_LIBC == LIBC_MUSL ++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";:%{muclibc:" U ";:" M "}}" + #else + #error "Unsupported DEFAULT_LIBC" + #endif + #define GNU_USER_DYNAMIC_LINKER32 \ +- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32) ++ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32, MUSL_DYNAMIC_LINKER32) + #define GNU_USER_DYNAMIC_LINKER64 \ +- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64) ++ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64, MUSL_DYNAMIC_LINKER64) + + #undef DEFAULT_ASM_ENDIAN + #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN) +diff --git a/gcc/config/rs6000/secureplt.h b/gcc/config/rs6000/secureplt.h +index b463463..77edf2a 100644 +--- a/gcc/config/rs6000/secureplt.h ++++ b/gcc/config/rs6000/secureplt.h +@@ -18,3 +18,4 @@ along with GCC; see the file COPYING3. If not see + . */ + + #define CC1_SECURE_PLT_DEFAULT_SPEC "-msecure-plt" ++#define LINK_SECURE_PLT_DEFAULT_SPEC "--secure-plt" +diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h +index 9917c2f..68365de 100644 +--- a/gcc/config/rs6000/sysv4.h ++++ b/gcc/config/rs6000/sysv4.h +@@ -537,6 +537,9 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN) + #ifndef CC1_SECURE_PLT_DEFAULT_SPEC + #define CC1_SECURE_PLT_DEFAULT_SPEC "" + #endif ++#ifndef LINK_SECURE_PLT_DEFAULT_SPEC ++#define LINK_SECURE_PLT_DEFAULT_SPEC "" ++#endif + + /* Pass -G xxx to the compiler. */ + #undef CC1_SPEC +@@ -574,7 +577,8 @@ + %{R*} \ + %(link_shlib) \ + %{!T*: %(link_start) } \ +-%(link_os)" ++%(link_os) \ ++%{!mbss-plt: %{!msecure-plt: %(link_secure_plt_default)}}" + + /* Shared libraries are not default. */ + #define LINK_SHLIB_SPEC "\ +@@ -762,17 +766,23 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN) + + #define LINK_START_LINUX_SPEC "" + ++#define MUSL_DYNAMIC_LINKER_E ENDIAN_SELECT("","le","") ++ + #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" + #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0" ++#define MUSL_DYNAMIC_LINKER \ ++ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" + #if DEFAULT_LIBC == LIBC_UCLIBC +-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}" ++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";:%{mmusl:" M ";:" U "}}" ++#elif DEFAULT_LIBC == LIBC_MUSL ++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";:%{muclibc:" U ";:" M "}}" + #elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC +-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:" U ";:" G "}" ++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{muclibc:" U ";:%{mmusl:" M ";:" G "}}" + #else + #error "Unsupported DEFAULT_LIBC" + #endif + #define GNU_USER_DYNAMIC_LINKER \ +- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER) ++ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER, MUSL_DYNAMIC_LINKER) + + #define LINK_OS_LINUX_SPEC "-m elf32ppclinux %{!shared: %{!static: \ + %{rdynamic:-export-dynamic} \ +@@ -895,6 +905,7 @@ ncrtn.o%s" + { "link_os_openbsd", LINK_OS_OPENBSD_SPEC }, \ + { "link_os_default", LINK_OS_DEFAULT_SPEC }, \ + { "cc1_secure_plt_default", CC1_SECURE_PLT_DEFAULT_SPEC }, \ ++ { "link_secure_plt_default", LINK_SECURE_PLT_DEFAULT_SPEC }, \ + { "cpp_os_ads", CPP_OS_ADS_SPEC }, \ + { "cpp_os_yellowknife", CPP_OS_YELLOWKNIFE_SPEC }, \ + { "cpp_os_mvme", CPP_OS_MVME_SPEC }, \ +@@ -949,3 +960,72 @@ ncrtn.o%s" + /* This target uses the sysv4.opt file. */ + #define TARGET_USES_SYSV4_OPT 1 + ++/* Include order changes for musl, same as in generic linux.h. */ ++#if DEFAULT_LIBC == LIBC_MUSL ++#define INCLUDE_DEFAULTS_MUSL_GPP \ ++ { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, \ ++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, \ ++ { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, \ ++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 }, \ ++ { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, \ ++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, ++ ++#ifdef LOCAL_INCLUDE_DIR ++#define INCLUDE_DEFAULTS_MUSL_LOCAL \ ++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, \ ++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 }, ++#else ++#define INCLUDE_DEFAULTS_MUSL_LOCAL ++#endif ++ ++#ifdef PREFIX_INCLUDE_DIR ++#define INCLUDE_DEFAULTS_MUSL_PREFIX \ ++ { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0}, ++#else ++#define INCLUDE_DEFAULTS_MUSL_PREFIX ++#endif ++ ++#ifdef CROSS_INCLUDE_DIR ++#define INCLUDE_DEFAULTS_MUSL_CROSS \ ++ { CROSS_INCLUDE_DIR, "GCC", 0, 0, 0, 0}, ++#else ++#define INCLUDE_DEFAULTS_MUSL_CROSS ++#endif ++ ++#ifdef TOOL_INCLUDE_DIR ++#define INCLUDE_DEFAULTS_MUSL_TOOL \ ++ { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1, 0, 0}, ++#else ++#define INCLUDE_DEFAULTS_MUSL_TOOL ++#endif ++ ++#ifdef NATIVE_SYSTEM_HEADER_DIR ++#define INCLUDE_DEFAULTS_MUSL_NATIVE \ ++ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 }, \ ++ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 0 }, ++#else ++#define INCLUDE_DEFAULTS_MUSL_NATIVE ++#endif ++ ++#if defined (CROSS_DIRECTORY_STRUCTURE) && !defined (TARGET_SYSTEM_ROOT) ++# undef INCLUDE_DEFAULTS_MUSL_LOCAL ++# define INCLUDE_DEFAULTS_MUSL_LOCAL ++# undef INCLUDE_DEFAULTS_MUSL_NATIVE ++# define INCLUDE_DEFAULTS_MUSL_NATIVE ++#else ++# undef INCLUDE_DEFAULTS_MUSL_CROSS ++# define INCLUDE_DEFAULTS_MUSL_CROSS ++#endif ++ ++#undef INCLUDE_DEFAULTS ++#define INCLUDE_DEFAULTS \ ++ { \ ++ INCLUDE_DEFAULTS_MUSL_GPP \ ++ INCLUDE_DEFAULTS_MUSL_PREFIX \ ++ INCLUDE_DEFAULTS_MUSL_CROSS \ ++ INCLUDE_DEFAULTS_MUSL_TOOL \ ++ INCLUDE_DEFAULTS_MUSL_NATIVE \ ++ { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 }, \ ++ { 0, 0, 0, 0, 0, 0 } \ ++ } ++#endif +diff --git a/gcc/config/rs6000/sysv4le.h b/gcc/config/rs6000/sysv4le.h +index 7b1d6a1..064323c 100644 +--- a/gcc/config/rs6000/sysv4le.h ++++ b/gcc/config/rs6000/sysv4le.h +@@ -35,3 +35,5 @@ + /* Little-endian PowerPC64 Linux uses the ELF v2 ABI by default. */ + #define LINUX64_DEFAULT_ABI_ELFv2 + ++#undef MUSL_DYNAMIC_LINKER_E ++#define MUSL_DYNAMIC_LINKER_E ENDIAN_SELECT("","le","le") +diff --git a/gcc/config/sh/linux.h b/gcc/config/sh/linux.h +index 0f5d614..4c167c6 100644 +--- a/gcc/config/sh/linux.h ++++ b/gcc/config/sh/linux.h +@@ -43,6 +43,29 @@ along with GCC; see the file COPYING3. If not see + + #define TARGET_ASM_FILE_END file_end_indicate_exec_stack + ++#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN ++#define MUSL_DYNAMIC_LINKER_E "%{mb:eb}" ++#else ++#define MUSL_DYNAMIC_LINKER_E "%{!ml:eb}" ++#endif ++ ++#if TARGET_CPU_DEFAULT & ( MASK_HARD_SH2A_DOUBLE | MASK_SH4 ) ++/* "-nofpu" if any nofpu option is specified */ ++#define MUSL_DYNAMIC_LINKER_FP \ ++ "%{m1|m2|m2a-nofpu|m3|m4-nofpu|m4-100-nofpu|m4-200-nofpu|m4-300-nofpu|" \ ++ "m4-340|m4-400|m4-500|m4al|m5-32media-nofpu|m5-64media-nofpu|" \ ++ "m5-compact-nofpu:-nofpu}" ++#else ++/* "-nofpu" if none of the hard fpu options are specified */ ++#define MUSL_DYNAMIC_LINKER_FP \ ++ "%{m2a|m4|m4-100|m4-200|m4-300|m4a|m5-32media|m5-64media|m5-compact:;:-nofpu}" ++#endif ++ ++#undef MUSL_DYNAMIC_LINKER ++#define MUSL_DYNAMIC_LINKER \ ++ "/lib/ld-musl-sh" MUSL_DYNAMIC_LINKER_E MUSL_DYNAMIC_LINKER_FP \ ++ "%{mfdpic:-fdpic}.so.1" ++ + #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2" + + #undef SUBTARGET_LINK_EMUL_SUFFIX +diff --git a/gcc/configure b/gcc/configure +index 0037240..66aab9f 100755 +--- a/gcc/configure ++++ b/gcc/configure +@@ -27742,6 +27742,9 @@ if test "${gcc_cv_libc_provides_ssp+set}" = set; then : + else + gcc_cv_libc_provides_ssp=no + case "$target" in ++ *-*-musl*) ++ # All versions of musl provide stack protector ++ gcc_cv_libc_provides_ssp=yes;; + *-*-linux* | *-*-kfreebsd*-gnu | *-*-knetbsd*-gnu) + # glibc 2.4 and later provides __stack_chk_fail and + # either __stack_chk_guard, or TLS access to stack guard canary. +@@ -27774,6 +27777,7 @@ fi + # ) and for now + # simply assert that glibc does provide this, which is true for all + # realistically usable GNU/Hurd configurations. ++ # All supported versions of musl provide it as well + gcc_cv_libc_provides_ssp=yes;; + *-*-darwin* | *-*-freebsd*) + ac_fn_c_check_func "$LINENO" "__stack_chk_fail" "ac_cv_func___stack_chk_fail" +@@ -27870,6 +27874,9 @@ case "$target" in + gcc_cv_target_dl_iterate_phdr=no + fi + ;; ++ *-linux-musl*) ++ gcc_cv_target_dl_iterate_phdr=yes ++ ;; + esac + + if test x$gcc_cv_target_dl_iterate_phdr = xyes; then +diff --git a/gcc/configure.ac b/gcc/configure.ac +index 6f38ba1..b81960c 100644 +--- a/gcc/configure.ac ++++ b/gcc/configure.ac +@@ -5229,6 +5229,9 @@ AC_CACHE_CHECK(__stack_chk_fail in target C library, + gcc_cv_libc_provides_ssp, + [gcc_cv_libc_provides_ssp=no + case "$target" in ++ *-*-musl*) ++ # All versions of musl provide stack protector ++ gcc_cv_libc_provides_ssp=yes;; + *-*-linux* | *-*-kfreebsd*-gnu | *-*-knetbsd*-gnu) + # glibc 2.4 and later provides __stack_chk_fail and + # either __stack_chk_guard, or TLS access to stack guard canary. +@@ -5255,6 +5258,7 @@ AC_CACHE_CHECK(__stack_chk_fail in target C library, + # ) and for now + # simply assert that glibc does provide this, which is true for all + # realistically usable GNU/Hurd configurations. ++ # All supported versions of musl provide it as well + gcc_cv_libc_provides_ssp=yes;; + *-*-darwin* | *-*-freebsd*) + AC_CHECK_FUNC(__stack_chk_fail,[gcc_cv_libc_provides_ssp=yes], +@@ -5328,6 +5332,9 @@ case "$target" in + gcc_cv_target_dl_iterate_phdr=no + fi + ;; ++ *-linux-musl*) ++ gcc_cv_target_dl_iterate_phdr=yes ++ ;; + esac + GCC_TARGET_TEMPLATE([TARGET_DL_ITERATE_PHDR]) + if test x$gcc_cv_target_dl_iterate_phdr = xyes; then +diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi +index f84a199..ee9765b 100644 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -667,7 +667,7 @@ Objective-C and Objective-C++ Dialects}. + -mcpu=@var{cpu}} + + @emph{GNU/Linux Options} +-@gccoptlist{-mglibc -muclibc -mbionic -mandroid @gol ++@gccoptlist{-mglibc -muclibc -mmusl -mbionic -mandroid @gol + -tno-android-cc -tno-android-ld} + + @emph{H8/300 Options} +@@ -15324,13 +15324,19 @@ These @samp{-m} options are defined for GNU/Linux targets: + @item -mglibc + @opindex mglibc + Use the GNU C library. This is the default except +-on @samp{*-*-linux-*uclibc*} and @samp{*-*-linux-*android*} targets. ++on @samp{*-*-linux-*uclibc*}, @samp{*-*-linux-*musl*} and ++@samp{*-*-linux-*android*} targets. + + @item -muclibc + @opindex muclibc + Use uClibc C library. This is the default on + @samp{*-*-linux-*uclibc*} targets. + ++@item -mmusl ++@opindex mmusl ++Use the musl C library. This is the default on ++@samp{*-*-linux-*musl*} targets. ++ + @item -mbionic + @opindex mbionic + Use Bionic C library. This is the default on +diff --git a/libcilkrts/runtime/os-unix.c b/libcilkrts/runtime/os-unix.c +index cb582dd..e43d7d5 100644 +--- a/libcilkrts/runtime/os-unix.c ++++ b/libcilkrts/runtime/os-unix.c +@@ -51,6 +51,7 @@ + #if defined __linux__ + # include + # include ++# include + #elif defined __APPLE__ + # include + // Uses sysconf(_SC_NPROCESSORS_ONLN) in verbose output +@@ -400,28 +401,19 @@ COMMON_SYSDEP void __cilkrts_sleep(void) + + COMMON_SYSDEP void __cilkrts_yield(void) + { +-#if __APPLE__ || __FreeBSD__ || __VXWORKS__ +- // On MacOS, call sched_yield to yield quantum. I'm not sure why we +- // don't do this on Linux also. +- sched_yield(); +-#elif defined(__DragonFly__) +- // On DragonFly BSD, call sched_yield to yield quantum. +- sched_yield(); +-#elif defined(__MIC__) ++#if defined(__MIC__) + // On MIC, pthread_yield() really trashes things. Arch's measurements + // showed that calling _mm_delay_32() (or doing nothing) was a better + // option. Delaying 1024 clock cycles is a reasonable compromise between + // giving up the processor and latency starting up when work becomes + // available + _mm_delay_32(1024); +-#elif defined(__ANDROID__) || (defined(__sun__) && defined(__svr4__)) +- // On Android and Solaris, call sched_yield to yield quantum. I'm not +- // sure why we don't do this on Linux also. +- sched_yield(); +-#else +- // On Linux, call pthread_yield (which in turn will call sched_yield) +- // to yield quantum. ++#elif defined(__sun__) && !defined(__svr4__) ++ // On old SunOS call pthread_yield to yield a quantum. + pthread_yield(); ++#else ++ // On other platforms call sched_yield to yield a quantum. ++ sched_yield(); + #endif + } + +diff --git a/libgcc/unwind-dw2-fde-dip.c b/libgcc/unwind-dw2-fde-dip.c +index e1e566b..137dced 100644 +--- a/libgcc/unwind-dw2-fde-dip.c ++++ b/libgcc/unwind-dw2-fde-dip.c +@@ -59,6 +59,12 @@ + + #if !defined(inhibit_libc) && defined(HAVE_LD_EH_FRAME_HDR) \ + && defined(TARGET_DL_ITERATE_PHDR) \ ++ && defined(__linux__) ++# define USE_PT_GNU_EH_FRAME ++#endif ++ ++#if !defined(inhibit_libc) && defined(HAVE_LD_EH_FRAME_HDR) \ ++ && defined(TARGET_DL_ITERATE_PHDR) \ + && (defined(__DragonFly__) || defined(__FreeBSD__)) + # define ElfW __ElfN + # define USE_PT_GNU_EH_FRAME +diff --git a/libgfortran/acinclude.m4 b/libgfortran/acinclude.m4 +index ba890f9..30b8b1a6 100644 +--- a/libgfortran/acinclude.m4 ++++ b/libgfortran/acinclude.m4 +@@ -100,7 +100,7 @@ void foo (void); + [Define to 1 if the target supports #pragma weak]) + fi + case "$host" in +- *-*-darwin* | *-*-hpux* | *-*-cygwin* | *-*-mingw* ) ++ *-*-darwin* | *-*-hpux* | *-*-cygwin* | *-*-mingw* | *-*-musl* ) + AC_DEFINE(GTHREAD_USE_WEAK, 0, + [Define to 0 if the target shouldn't use #pragma weak]) + ;; +diff --git a/libgfortran/configure b/libgfortran/configure +index e1592f7..07542e1 100755 +--- a/libgfortran/configure ++++ b/libgfortran/configure +@@ -26447,7 +26447,7 @@ $as_echo "#define SUPPORTS_WEAK 1" >>confdefs.h + + fi + case "$host" in +- *-*-darwin* | *-*-hpux* | *-*-cygwin* | *-*-mingw* ) ++ *-*-darwin* | *-*-hpux* | *-*-cygwin* | *-*-mingw* | *-*-musl* ) + + $as_echo "#define GTHREAD_USE_WEAK 0" >>confdefs.h + +diff --git a/libitm/config/arm/hwcap.cc b/libitm/config/arm/hwcap.cc +index a1c2cfd..ea8f023 100644 +--- a/libitm/config/arm/hwcap.cc ++++ b/libitm/config/arm/hwcap.cc +@@ -40,7 +40,7 @@ int GTM_hwcap HIDDEN = 0 + + #ifdef __linux__ + #include +-#include ++#include + #include + + static void __attribute__((constructor)) +diff --git a/libitm/config/linux/x86/tls.h b/libitm/config/linux/x86/tls.h +index e731ab7..54ad8b6 100644 +--- a/libitm/config/linux/x86/tls.h ++++ b/libitm/config/linux/x86/tls.h +@@ -25,16 +25,19 @@ + #ifndef LIBITM_X86_TLS_H + #define LIBITM_X86_TLS_H 1 + +-#if defined(__GLIBC_PREREQ) && __GLIBC_PREREQ(2, 10) ++#if defined(__GLIBC_PREREQ) ++#if __GLIBC_PREREQ(2, 10) + /* Use slots in the TCB head rather than __thread lookups. + GLIBC has reserved words 10 through 13 for TM. */ + #define HAVE_ARCH_GTM_THREAD 1 + #define HAVE_ARCH_GTM_THREAD_DISP 1 + #endif ++#endif + + #include "config/generic/tls.h" + +-#if defined(__GLIBC_PREREQ) && __GLIBC_PREREQ(2, 10) ++#if defined(__GLIBC_PREREQ) ++#if __GLIBC_PREREQ(2, 10) + namespace GTM HIDDEN { + + #ifdef __x86_64__ +@@ -101,5 +104,6 @@ static inline void set_abi_disp(struct abi_dispatch *x) + + } // namespace GTM + #endif /* >= GLIBC 2.10 */ ++#endif + + #endif // LIBITM_X86_TLS_H +diff --git a/libstdc++-v3/config/os/generic/os_defines.h b/libstdc++-v3/config/os/generic/os_defines.h +index 45bf52a..103ec0e 100644 +--- a/libstdc++-v3/config/os/generic/os_defines.h ++++ b/libstdc++-v3/config/os/generic/os_defines.h +@@ -33,4 +33,9 @@ + // System-specific #define, typedefs, corrections, etc, go here. This + // file will come before all others. + ++// Disable the weak reference logic in gthr.h for os/generic because it ++// is broken on every platform unless there is implementation specific ++// workaround in gthr-posix.h and at link-time for static linking. ++#define _GLIBCXX_GTHREAD_USE_WEAK 0 ++ + #endif +diff --git a/libstdc++-v3/configure.host b/libstdc++-v3/configure.host +index 640199c..106134e 100644 +--- a/libstdc++-v3/configure.host ++++ b/libstdc++-v3/configure.host +@@ -273,6 +273,9 @@ case "${host_os}" in + freebsd*) + os_include_dir="os/bsd/freebsd" + ;; ++ linux-musl*) ++ os_include_dir="os/generic" ++ ;; + gnu* | linux* | kfreebsd*-gnu | knetbsd*-gnu) + if [ "$uclibc" = "yes" ]; then + os_include_dir="os/uclibc" diff --git a/patches/gcc-5.3.0/0002-pr66609.diff b/patches/gcc-5.3.0/0002-pr66609.diff new file mode 100644 index 0000000..5c3bd31 --- /dev/null +++ b/patches/gcc-5.3.0/0002-pr66609.diff @@ -0,0 +1,138 @@ +--- a/gcc/config/sh/sh-protos.h ++++ a/gcc/config/sh/sh-protos.h +@@ -159,6 +159,7 @@ extern int sh_eval_treg_value (rtx op); + extern HOST_WIDE_INT sh_disp_addr_displacement (rtx mem_op); + extern int sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a); + extern bool sh_movsf_ie_ra_split_p (rtx, rtx, rtx); ++extern void sh_expand_sym_label2reg (rtx, rtx, rtx, bool); + + /* Result value of sh_find_set_of_reg. */ + struct set_of_reg +--- a/gcc/config/sh/sh.c ++++ a/gcc/config/sh/sh.c +@@ -1604,6 +1604,10 @@ sh_asm_output_addr_const_extra (FILE *file, rtx x) + output_addr_const (file, XVECEXP (x, 0, 0)); + fputs ("@GOTPLT", file); + break; ++ case UNSPEC_PCREL: ++ output_addr_const (file, XVECEXP (x, 0, 0)); ++ fputs ("@PCREL", file); ++ break; + case UNSPEC_DTPOFF: + output_addr_const (file, XVECEXP (x, 0, 0)); + fputs ("@DTPOFF", file); +@@ -10441,6 +10445,7 @@ nonpic_symbol_mentioned_p (rtx x) + || XINT (x, 1) == UNSPEC_DTPOFF + || XINT (x, 1) == UNSPEC_TPOFF + || XINT (x, 1) == UNSPEC_PLT ++ || XINT (x, 1) == UNSPEC_PCREL + || XINT (x, 1) == UNSPEC_SYMOFF + || XINT (x, 1) == UNSPEC_PCREL_SYMOFF)) + return false; +@@ -10714,7 +10719,8 @@ sh_delegitimize_address (rtx orig_x) + rtx symplt = XEXP (XVECEXP (y, 0, 0), 0); + + if (GET_CODE (symplt) == UNSPEC +- && XINT (symplt, 1) == UNSPEC_PLT) ++ && (XINT (symplt, 1) == UNSPEC_PLT ++ || XINT (symplt, 1) == UNSPEC_PCREL)) + return XVECEXP (symplt, 0, 0); + } + } +@@ -11702,9 +11708,24 @@ sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) + || crtl->args.info.stack_regs == 0) + && ! sh_cfun_interrupt_handler_p () + && (! flag_pic +- || (decl && ! TREE_PUBLIC (decl)) ++ || (decl && ! (TREE_PUBLIC (decl) || DECL_WEAK (decl))) + || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT))); + } ++ ++/* Expand to appropriate sym*_label2reg for SYM and SIBCALL_P. */ ++void ++sh_expand_sym_label2reg (rtx reg, rtx sym, rtx lab, bool sibcall_p) ++{ ++ const_tree decl = SYMBOL_REF_DECL (sym); ++ bool is_weak = (decl && DECL_P (decl) && DECL_WEAK (decl)); ++ ++ if (!is_weak && SYMBOL_REF_LOCAL_P (sym)) ++ emit_insn (gen_sym_label2reg (reg, sym, lab)); ++ else if (sibcall_p) ++ emit_insn (gen_symPCREL_label2reg (reg, sym, lab)); ++ else ++ emit_insn (gen_symPLT_label2reg (reg, sym, lab)); ++} + + /* Machine specific built-in functions. */ + +--- a/gcc/config/sh/sh.md ++++ a/gcc/config/sh/sh.md +@@ -135,6 +135,7 @@ + UNSPEC_PLT + UNSPEC_CALLER + UNSPEC_GOTPLT ++ UNSPEC_PCREL + UNSPEC_ICACHE + UNSPEC_INIT_TRAMP + UNSPEC_FCOSA +@@ -9470,11 +9471,8 @@ label: + [(const_int 0)] + { + rtx lab = PATTERN (gen_call_site ()); +- +- if (SYMBOL_REF_LOCAL_P (operands[0])) +- emit_insn (gen_sym_label2reg (operands[2], operands[0], lab)); +- else +- emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab)); ++ ++ sh_expand_sym_label2reg (operands[2], operands[0], lab, false); + emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab))); + DONE; + } +@@ -9605,10 +9603,7 @@ label: + { + rtx lab = PATTERN (gen_call_site ()); + +- if (SYMBOL_REF_LOCAL_P (operands[1])) +- emit_insn (gen_sym_label2reg (operands[3], operands[1], lab)); +- else +- emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab)); ++ sh_expand_sym_label2reg (operands[3], operands[1], lab, false); + emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3], + operands[2], copy_rtx (lab))); + DONE; +@@ -10008,7 +10003,7 @@ label: + rtx lab = PATTERN (gen_call_site ()); + rtx call_insn; + +- emit_insn (gen_sym_label2reg (operands[2], operands[0], lab)); ++ sh_expand_sym_label2reg (operands[2], operands[0], lab, true); + call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1], + copy_rtx (lab))); + SIBLING_CALL_P (call_insn) = 1; +@@ -10200,7 +10195,7 @@ label: + rtx lab = PATTERN (gen_call_site ()); + rtx call_insn; + +- emit_insn (gen_sym_label2reg (operands[3], operands[1], lab)); ++ sh_expand_sym_label2reg (operands[3], operands[1], lab, true); + call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0], + operands[3], + operands[2], +@@ -10748,6 +10743,16 @@ label: + UNSPEC_SYMOFF)))] + "TARGET_SH1" "") + ++(define_expand "symPCREL_label2reg" ++ [(set (match_operand:SI 0 "" "") ++ (const:SI ++ (unspec:SI ++ [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PCREL)) ++ (const:SI (plus:SI (match_operand:SI 2 "" "") ++ (const_int 2)))] UNSPEC_PCREL_SYMOFF)))] ++ "TARGET_SH1" ++ "") ++ + (define_expand "symGOT_load" + [(set (match_dup 2) (match_operand 1 "" "")) + (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG))) diff --git a/patches/gcc-5.3.0/0003-shbitrot.diff b/patches/gcc-5.3.0/0003-shbitrot.diff new file mode 100644 index 0000000..27cbd68 --- /dev/null +++ b/patches/gcc-5.3.0/0003-shbitrot.diff @@ -0,0 +1,33 @@ +--- gcc-5.2.0.orig/gcc/config.gcc ++++ gcc-5.2.0/gcc/config.gcc +@@ -4096,7 +4099,7 @@ + esac + ;; + +- sh[123456ble]-*-* | sh-*-*) ++ sh[123456ble]*-*-* | sh-*-*) + supported_defaults="cpu" + case "`echo $with_cpu | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ_ abcdefghijklmnopqrstuvwxyz- | sed s/sh/m/`" in + "" | m1 | m2 | m2e | m3 | m3e | m4 | m4-single | m4-single-only | m4-nofpu ) +--- gcc-5.2.0.base/gcc/configure.ac 2015-08-11 16:23:36.000000000 +0000 ++++ gcc-5.2.0/gcc/configure.ac 2015-09-13 08:17:31.714972082 +0000 +@@ -3300,7 +3300,7 @@ + tls_first_minor=14 + tls_as_opt="-m64 -Aesame --fatal-warnings" + ;; +- sh-*-* | sh[34]-*-*) ++ sh-*-* | sh[123456789lbe]*-*-*) + conftest_s=' + .section ".tdata","awT",@progbits + foo: .long 25 +--- gcc-5.2.0.base/gcc/configure 2015-08-11 16:23:35.000000000 +0000 ++++ gcc-5.2.0/gcc/configure 2015-09-13 08:17:42.608304751 +0000 +@@ -23754,7 +23754,7 @@ + tls_first_minor=14 + tls_as_opt="-m64 -Aesame --fatal-warnings" + ;; +- sh-*-* | sh[34]-*-*) ++ sh-*-* | sh[123456789lbe]*-*-*) + conftest_s=' + .section ".tdata","awT",@progbits + foo: .long 25 diff --git a/patches/gcc-5.3.0/0004-j2.diff b/patches/gcc-5.3.0/0004-j2.diff new file mode 100644 index 0000000..8f69236 --- /dev/null +++ b/patches/gcc-5.3.0/0004-j2.diff @@ -0,0 +1,349 @@ +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 0f2dc32..a3d0d45 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -467,7 +467,7 @@ s390*-*-*) + extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h" + ;; + # Note the 'l'; we need to be able to match e.g. "shle" or "shl". +-sh[123456789lbe]*-*-* | sh-*-*) ++sh[123456789lbej]*-*-* | sh-*-*) + cpu_type=sh + extra_options="${extra_options} fused-madd.opt" + extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o" +@@ -2601,19 +2601,19 @@ s390x-ibm-tpf*) + extra_options="${extra_options} s390/tpf.opt" + tmake_file="${tmake_file} s390/t-s390" + ;; +-sh-*-elf* | sh[12346l]*-*-elf* | \ +- sh-*-linux* | sh[2346lbe]*-*-linux* | \ ++sh-*-elf* | sh[12346lj]*-*-elf* | \ ++ sh-*-linux* | sh[2346lbej]*-*-linux* | \ + sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \ + sh64-*-netbsd* | sh64l*-*-netbsd*) + tmake_file="${tmake_file} sh/t-sh sh/t-elf" + if test x${with_endian} = x; then + case ${target} in +- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;; ++ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;; + shbe-*-* | sheb-*-*) with_endian=big,little ;; + sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;; + shl* | sh64l* | sh*-*-linux* | \ + sh5l* | sh-superh-elf) with_endian=little,big ;; +- sh[1234]*-*-*) with_endian=big ;; ++ sh[j1234]*-*-*) with_endian=big ;; + *) with_endian=big,little ;; + esac + fi +@@ -2703,6 +2703,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;; + sh2a*) sh_cpu_target=sh2a ;; + sh2e*) sh_cpu_target=sh2e ;; ++ shj2*) sh_cpu_target=shj2;; + sh2*) sh_cpu_target=sh2 ;; + *) sh_cpu_target=sh1 ;; + esac +@@ -2727,7 +2728,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \ + sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \ + sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \ +- sh3e | sh3 | sh2e | sh2 | sh1) ;; ++ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;; + "") sh_cpu_default=${sh_cpu_target} ;; + *) echo "with_cpu=$with_cpu not supported"; exit 1 ;; + esac +@@ -2738,9 +2739,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh[1234]*) sh_multilibs=${sh_cpu_target} ;; + sh64* | sh5*) sh_multilibs=m5-32media,m5-32media-nofpu,m5-compact,m5-compact-nofpu,m5-64media,m5-64media-nofpu ;; + sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;; +- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;; ++ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;; + sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;; +- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;; ++ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;; + esac + if test x$with_fp = xno; then + sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`" +@@ -2758,7 +2759,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + m2a | m2a-single | m2a-single-only | m2a-nofpu | \ + m5-64media | m5-64media-nofpu | \ + m5-32media | m5-32media-nofpu | \ +- m5-compact | m5-compact-nofpu) ++ m5-compact | m5-compact-nofpu | \ ++ mj2) + # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition + # It is passed to MULTIILIB_OPTIONS verbatim. + TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}" +@@ -2775,7 +2777,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + done + TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'` + if test x${enable_incomplete_targets} = xyes ; then +- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1" ++ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1 SUPPORT_SHJ2=1" + fi + tm_file="$tm_file ./sysroot-suffix.h" + tmake_file="$tmake_file t-sysroot-suffix" +@@ -4106,6 +4109,8 @@ + ;; + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al) + ;; ++ mj2) ++ ;; + *) + echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2 + echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2 +@@ -4456,7 +4458,7 @@ case ${target} in + tmake_file="rs6000/t-rs6000 ${tmake_file}" + ;; + +- sh[123456ble]*-*-* | sh-*-*) ++ sh[123456blej]*-*-* | sh-*-*) + c_target_objs="${c_target_objs} sh-c.o" + cxx_target_objs="${cxx_target_objs} sh-c.o" + ;; +diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h +index b08120d..63b77fa 100644 +--- a/gcc/config/sh/sh-protos.h ++++ b/gcc/config/sh/sh-protos.h +@@ -45,6 +45,7 @@ struct sh_atomic_model + hard_llcs, + soft_tcb, + soft_imask, ++ hard_cas, + + num_models + }; +@@ -88,6 +89,9 @@ extern const sh_atomic_model& selected_atomic_model (void); + #define TARGET_ATOMIC_SOFT_IMASK \ + (selected_atomic_model ().type == sh_atomic_model::soft_imask) + ++#define TARGET_ATOMIC_HARD_CAS \ ++ (selected_atomic_model ().type == sh_atomic_model::hard_cas) ++ + #ifdef RTX_CODE + extern rtx sh_fsca_sf2int (void); + extern rtx sh_fsca_int2sf (void); +diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c +index 0b18ce5..bdf96e2 100644 +--- a/gcc/config/sh/sh.c ++++ b/gcc/config/sh/sh.c +@@ -692,6 +692,7 @@ parse_validate_atomic_model_option (const char* str) + model_names[sh_atomic_model::hard_llcs] = "hard-llcs"; + model_names[sh_atomic_model::soft_tcb] = "soft-tcb"; + model_names[sh_atomic_model::soft_imask] = "soft-imask"; ++ model_names[sh_atomic_model::hard_cas] = "hard-cas"; + + const char* model_cdef_names[sh_atomic_model::num_models]; + model_cdef_names[sh_atomic_model::none] = "NONE"; +@@ -699,6 +700,7 @@ parse_validate_atomic_model_option (const char* str) + model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS"; + model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB"; + model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK"; ++ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS"; + + sh_atomic_model ret; + ret.type = sh_atomic_model::none; +@@ -780,6 +782,9 @@ got_mode_name:; + if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE) + err_ret ("cannot use atomic model %s in user mode", ret.name); + ++ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2) ++ err_ret ("atomic model %s is only available J2 targets", ret.name); ++ + return ret; + + #undef err_ret +@@ -845,6 +850,8 @@ sh_option_override (void) + sh_cpu = PROCESSOR_SH2E; + if (TARGET_SH2A) + sh_cpu = PROCESSOR_SH2A; ++ if (TARGET_SHJ2) ++ sh_cpu = PROCESSOR_SHJ2; + if (TARGET_SH3) + sh_cpu = PROCESSOR_SH3; + if (TARGET_SH3E) +diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h +index 7187c23..9d0d1d0 100644 +--- a/gcc/config/sh/sh.h ++++ b/gcc/config/sh/sh.h +@@ -106,6 +106,7 @@ extern int code_for_indirect_jump_scratch; + #define SUPPORT_SH4_SINGLE 1 + #define SUPPORT_SH2A 1 + #define SUPPORT_SH2A_SINGLE 1 ++#define SUPPORT_SHJ2 1 + #endif + + #define TARGET_DIVIDE_INV \ +@@ -157,6 +158,7 @@ extern int code_for_indirect_jump_scratch; + #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E) + #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E) + #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3) ++#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2) + + #if SUPPORT_SH1 + #define SUPPORT_SH2 1 +@@ -164,6 +166,7 @@ extern int code_for_indirect_jump_scratch; + #if SUPPORT_SH2 + #define SUPPORT_SH3 1 + #define SUPPORT_SH2A_NOFPU 1 ++#define SUPPORT_SHJ2 1 + #endif + #if SUPPORT_SH3 + #define SUPPORT_SH4_NOFPU 1 +@@ -211,7 +214,7 @@ extern int code_for_indirect_jump_scratch; + #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ + | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ + | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5 \ +- | MASK_FPU_SINGLE_ONLY) ++ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2) + + /* This defaults us to big-endian. */ + #ifndef TARGET_ENDIAN_DEFAULT +@@ -289,8 +292,8 @@ extern int code_for_indirect_jump_scratch; + %{m5-compact*:--isa=SHcompact} \ + %{m5-32media*:--isa=SHmedia --abi=32} \ + %{m5-64media*:--isa=SHmedia --abi=64} \ +-%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}" +- ++%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround} \ ++%{mj2:-isa=j2}" + #define ASM_SPEC SH_ASM_SPEC + + #ifndef SUBTARGET_ASM_ENDIAN_SPEC +@@ -1853,7 +1856,7 @@ struct sh_args { + + /* Nonzero if the target supports dynamic shift instructions + like shad and shld. */ +-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) ++#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2) + + /* The cost of using the dynamic shift insns (shad, shld) are the same + if they are available. If they are not available a library function will +@@ -2185,6 +2188,7 @@ enum processor_type { + PROCESSOR_SH2, + PROCESSOR_SH2E, + PROCESSOR_SH2A, ++ PROCESSOR_SHJ2, + PROCESSOR_SH3, + PROCESSOR_SH3E, + PROCESSOR_SH4, +diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt +index 1026c73..bac47ed 100644 +--- a/gcc/config/sh/sh.opt ++++ b/gcc/config/sh/sh.opt +@@ -71,6 +71,10 @@ m2e + Target RejectNegative Condition(SUPPORT_SH2E) + Generate SH2e code. + ++mj2 ++Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2) ++Generate J2 code. ++ + m3 + Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) + Generate SH3 code. +diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md +index 6f1337b..cff57b8 100644 +--- a/gcc/config/sh/sync.md ++++ b/gcc/config/sh/sync.md +@@ -240,6 +240,9 @@ + || (TARGET_SH4A && mode == SImode && !TARGET_ATOMIC_STRICT)) + atomic_insn = gen_atomic_compare_and_swap_hard (old_val, mem, + exp_val, new_val); ++ else if (TARGET_ATOMIC_HARD_CAS && mode == SImode) ++ atomic_insn = gen_atomic_compare_and_swap_cas (old_val, mem, ++ exp_val, new_val); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic_compare_and_swap_soft_gusa (old_val, mem, + exp_val, new_val); +@@ -306,6 +309,57 @@ + } + [(set_attr "length" "14")]) + ++(define_expand "atomic_compare_and_swapsi_cas" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "r")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{ ++ rtx mem = gen_rtx_REG (SImode, 0); ++ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0))); ++ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_insn "shj2_cas" ++ [(set (match_operand:SI 0 "register_operand" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "register_operand" "=r") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "0")] ++ UNSPECV_CMPXCHG_1)) ++ (set (reg:SI T_REG) ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))] ++ "TARGET_ATOMIC_HARD_CAS" ++ "cas.l %2,%0,@%1" ++ [(set_attr "length" "2")] ++) ++ ++(define_expand "atomic_compare_and_swapqi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ ++(define_expand "atomic_compare_and_swaphi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ + ;; The QIHImode llcs patterns modify the address register of the memory + ;; operand. In order to express that, we have to open code the memory + ;; operand. Initially the insn is expanded like every other atomic insn +diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh +index 348cc0b..8e6bdaf 100644 +--- a/gcc/config/sh/t-sh ++++ b/gcc/config/sh/t-sh +@@ -52,7 +52,7 @@ MULTILIB_MATCHES = $(shell \ + m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \ + m4,m4-100,m4-200,m4-300,m4a \ + m5-32media,m5-compact,m5-32media \ +- m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu; do \ ++ m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu,mj2; do \ + subst= ; \ + for lib in `echo $$abi|tr , ' '` ; do \ + if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \ +@@ -65,9 +65,9 @@ MULTILIB_MATCHES = $(shell \ + + # SH1 and SH2A support big endian only. + ifeq ($(DEFAULT_ENDIAN),ml) +-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + else +-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + endif + + MULTILIB_OSDIRNAMES = \ +@@ -96,6 +96,7 @@ MULTILIB_OSDIRNAMES = \ + m5-compact-nofpu=!m5-compact-nofpu $(OTHER_ENDIAN)/m5-compact-nofpu=!$(OTHER_ENDIAN)/m5-compact-nofpu \ + m5-64media=!m5-64media $(OTHER_ENDIAN)/m5-64media=!$(OTHER_ENDIAN)/m5-64media \ + m5-64media-nofpu=!m5-64media-nofpu $(OTHER_ENDIAN)/m5-64media-nofpu=!$(OTHER_ENDIAN)/m5-64media-nofpu ++ mj2=!j2 + + $(out_object_file): gt-sh.h + gt-sh.h : s-gtype ; @true diff --git a/patches/gcc-5.3.0/0005-staticpie.diff b/patches/gcc-5.3.0/0005-staticpie.diff new file mode 100644 index 0000000..2668462 --- /dev/null +++ b/patches/gcc-5.3.0/0005-staticpie.diff @@ -0,0 +1,24 @@ +--- gcc-5.2.0.orig/gcc/config/gnu-user.h 2015-01-05 12:33:28.000000000 +0000 ++++ gcc-5.2.0/gcc/config/gnu-user.h 2015-08-25 08:15:18.354957759 +0000 +@@ -42,8 +42,8 @@ + + #if defined HAVE_LD_PIE + #define GNU_USER_TARGET_STARTFILE_SPEC \ +- "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \ +- crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \ ++ "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:%{static:rcrt1.o%s;:Scrt1.o%s};:crt1.o%s}} \ ++ crti.o%s %{shared|pie:crtbeginS.o%s;static:crtbeginT.o%s;:crtbegin.o%s} \ + %{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_start_preinit.o%s; \ + fvtable-verify=std:vtv_start.o%s}" +--- gcc-5.2.0.orig/gcc/gcc.c 2015-03-10 09:37:41.000000000 +0000 ++++ gcc-5.2.0/gcc/gcc.c 2015-09-30 00:25:33.225927941 +0000 +@@ -739,7 +739,7 @@ + + #ifndef LINK_PIE_SPEC + #ifdef HAVE_LD_PIE +-#define LINK_PIE_SPEC "%{pie:-pie} " ++#define LINK_PIE_SPEC "%{pie:-pie %{static:--no-dynamic-linker}} " + #else + #define LINK_PIE_SPEC "%{pie:} " + #endif diff --git a/patches/gcc-5.3.0/0006-defaultpie.diff b/patches/gcc-5.3.0/0006-defaultpie.diff new file mode 100644 index 0000000..b040441 --- /dev/null +++ b/patches/gcc-5.3.0/0006-defaultpie.diff @@ -0,0 +1,40 @@ +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 3779369..a6d95ca 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -3101,6 +3101,12 @@ case ${target} in + ;; + esac + ++case "x${enable_default_pie}" in ++xyes) ++ tm_defines="${tm_defines} ENABLE_DEFAULT_PIE=1" ++ ;; ++esac ++ + t= + all_defaults="abi cpu arch tune schedule float mode fpu divide" + for option in $all_defaults +--- gcc-5.2.0.orig/gcc/gcc.c 2015-03-10 09:37:41.000000000 +0000 ++++ gcc-5.2.0/gcc/gcc.c 2015-08-25 07:47:12.895060530 +0000 +@@ -1012,10 +1012,19 @@ + #define CILK_SELF_SPECS "%{fcilkplus: -pthread}" + #endif + ++/* Default to PIE */ ++#ifndef PIE_SELF_SPECS ++#ifdef ENABLE_DEFAULT_PIE ++#define PIE_SELF_SPECS "%{shared|pie|r|nostdlib|nopie|no-pie:;:-pie} %{fpic|fPIC|fpie|fPIE|fno-pic|fno-PIC|fno-pie|fno-PIE|D__KERNEL__:;:-fPIE}" ++#else ++#define PIE_SELF_SPECS "" ++#endif ++#endif ++ + static const char *const driver_self_specs[] = { + "%{fdump-final-insns:-fdump-final-insns=.} %> 3; ++ int dwords = bytes >> 3; + emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1))); +- emit_insn (gen_block_lump_real_i4 (func_addr_rtx)); ++ emit_insn (gen_block_lump_real_i4 (func_addr_rtx, lab)); + return true; + } + else +@@ -159,10 +160,10 @@ expand_block_move (rtx *operands) + rtx r5 = gen_rtx_REG (SImode, 5); + + sprintf (entry, "__movmemSI%d", bytes); +- function_symbol (func_addr_rtx, entry, SFUNC_STATIC); ++ rtx lab = function_symbol (func_addr_rtx, entry, SFUNC_STATIC).lab; + force_into (XEXP (operands[0], 0), r4); + force_into (XEXP (operands[1], 0), r5); +- emit_insn (gen_block_move_real (func_addr_rtx)); ++ emit_insn (gen_block_move_real (func_addr_rtx, lab)); + return true; + } + +@@ -176,7 +177,7 @@ expand_block_move (rtx *operands) + rtx r5 = gen_rtx_REG (SImode, 5); + rtx r6 = gen_rtx_REG (SImode, 6); + +- function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC); ++ rtx lab = function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC).lab; + force_into (XEXP (operands[0], 0), r4); + force_into (XEXP (operands[1], 0), r5); + +@@ -189,7 +190,7 @@ expand_block_move (rtx *operands) + final_switch = 16 - ((bytes / 4) % 16); + while_loop = ((bytes / 4) / 16 - 1) * 16; + emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch))); +- emit_insn (gen_block_lump_real (func_addr_rtx)); ++ emit_insn (gen_block_lump_real (func_addr_rtx, lab)); + return true; + } + +diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h +index f94459f..c64a948 100644 +--- a/gcc/config/sh/sh-protos.h ++++ b/gcc/config/sh/sh-protos.h +@@ -377,7 +377,19 @@ extern void fpscr_set_from_mem (int, HARD_REG_SET); + extern void sh_pr_interrupt (struct cpp_reader *); + extern void sh_pr_trapa (struct cpp_reader *); + extern void sh_pr_nosave_low_regs (struct cpp_reader *); +-extern rtx function_symbol (rtx, const char *, enum sh_function_kind); ++ ++struct function_symbol_result ++{ ++ function_symbol_result (void) : sym (NULL), lab (NULL) { } ++ function_symbol_result (rtx s, rtx l) : sym (s), lab (l) { } ++ ++ rtx sym; ++ rtx lab; ++}; ++ ++extern function_symbol_result function_symbol (rtx, const char *, ++ sh_function_kind); ++extern rtx sh_get_fdpic_reg_initial_val (void); + extern rtx sh_get_pr_initial_val (void); + + extern void sh_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, +@@ -396,4 +408,5 @@ extern bool sh_hard_regno_mode_ok (unsigned int, machine_mode); + extern machine_mode sh_hard_regno_caller_save_mode (unsigned int, unsigned int, + machine_mode); + extern bool sh_can_use_simple_return_p (void); ++extern rtx sh_load_function_descriptor (rtx); + #endif /* ! GCC_SH_PROTOS_H */ +diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c +index 904201b..e6a0b1e 100644 +--- a/gcc/config/sh/sh.c ++++ b/gcc/config/sh/sh.c +@@ -268,6 +268,7 @@ static rtx sh_expand_builtin (tree, rtx, rtx, machine_mode, int); + static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, + HOST_WIDE_INT, tree); + static void sh_file_start (void); ++static bool sh_assemble_integer (rtx, unsigned int, int); + static bool flow_dependent_p (rtx, rtx); + static void flow_dependent_p_1 (rtx, const_rtx, void *); + static int shiftcosts (rtx); +@@ -276,6 +277,7 @@ static int addsubcosts (rtx); + static int multcosts (rtx); + static bool unspec_caller_rtx_p (rtx); + static bool sh_cannot_copy_insn_p (rtx_insn *); ++static bool sh_cannot_force_const_mem_p (machine_mode, rtx); + static bool sh_rtx_costs (rtx, int, int, int, int *, bool); + static int sh_address_cost (rtx, machine_mode, addr_space_t, bool); + static int sh_pr_n_sets (void); +@@ -421,6 +423,9 @@ static const struct attribute_spec sh_attribute_table[] = + #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE + #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true + ++#undef TARGET_ASM_INTEGER ++#define TARGET_ASM_INTEGER sh_assemble_integer ++ + #undef TARGET_REGISTER_MOVE_COST + #define TARGET_REGISTER_MOVE_COST sh_register_move_cost + +@@ -679,6 +684,9 @@ static const struct attribute_spec sh_attribute_table[] = + #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL + #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0x80 + ++#undef TARGET_CANNOT_FORCE_CONST_MEM ++#define TARGET_CANNOT_FORCE_CONST_MEM sh_cannot_force_const_mem_p ++ + struct gcc_target targetm = TARGET_INITIALIZER; + + +@@ -996,6 +1004,13 @@ sh_option_override (void) + if (! global_options_set.x_TARGET_ZDCBRANCH && TARGET_HARD_SH4) + TARGET_ZDCBRANCH = 1; + ++ /* FDPIC code is a special form of PIC, and the vast majority of code ++ generation constraints that apply to PIC also apply to FDPIC, so we ++ set flag_pic to avoid the need to check TARGET_FDPIC everywhere ++ flag_pic is checked. */ ++ if (TARGET_FDPIC && !flag_pic) ++ flag_pic = 2; ++ + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) + if (! VALID_REGISTER_P (regno)) + sh_register_names[regno][0] = '\0'; +@@ -1687,6 +1702,14 @@ sh_asm_output_addr_const_extra (FILE *file, rtx x) + output_addr_const (file, XVECEXP (x, 0, 1)); + fputs ("-.)", file); + break; ++ case UNSPEC_GOTFUNCDESC: ++ output_addr_const (file, XVECEXP (x, 0, 0)); ++ fputs ("@GOTFUNCDESC", file); ++ break; ++ case UNSPEC_GOTOFFFUNCDESC: ++ output_addr_const (file, XVECEXP (x, 0, 0)); ++ fputs ("@GOTOFFFUNCDESC", file); ++ break; + default: + return false; + } +@@ -1871,6 +1894,9 @@ prepare_move_operands (rtx operands[], machine_mode mode) + { + case TLS_MODEL_GLOBAL_DYNAMIC: + tga_ret = gen_rtx_REG (Pmode, R0_REG); ++ if (TARGET_FDPIC) ++ emit_move_insn (gen_rtx_REG (Pmode, PIC_REG), ++ sh_get_fdpic_reg_initial_val ()); + emit_call_insn (gen_tls_global_dynamic (tga_ret, op1)); + tmp = gen_reg_rtx (Pmode); + emit_move_insn (tmp, tga_ret); +@@ -1879,6 +1905,9 @@ prepare_move_operands (rtx operands[], machine_mode mode) + + case TLS_MODEL_LOCAL_DYNAMIC: + tga_ret = gen_rtx_REG (Pmode, R0_REG); ++ if (TARGET_FDPIC) ++ emit_move_insn (gen_rtx_REG (Pmode, PIC_REG), ++ sh_get_fdpic_reg_initial_val ()); + emit_call_insn (gen_tls_local_dynamic (tga_ret, op1)); + + tmp = gen_reg_rtx (Pmode); +@@ -1896,6 +1925,9 @@ prepare_move_operands (rtx operands[], machine_mode mode) + case TLS_MODEL_INITIAL_EXEC: + tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode); + tmp = gen_sym2GOTTPOFF (op1); ++ if (TARGET_FDPIC) ++ emit_move_insn (gen_rtx_REG (Pmode, PIC_REG), ++ sh_get_fdpic_reg_initial_val ()); + emit_insn (gen_tls_initial_exec (tga_op1, tmp)); + op1 = tga_op1; + break; +@@ -1922,6 +1954,22 @@ prepare_move_operands (rtx operands[], machine_mode mode) + operands[1] = op1; + } + } ++ ++ if (SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) ++ { ++ rtx base, offset; ++ split_const (operands[1], &base, &offset); ++ ++ if (GET_CODE (base) == SYMBOL_REF ++ && !offset_within_block_p (base, INTVAL (offset))) ++ { ++ rtx tmp = can_create_pseudo_p () ? gen_reg_rtx (mode) : operands[0]; ++ emit_move_insn (tmp, base); ++ if (!arith_operand (offset, mode)) ++ offset = force_reg (mode, offset); ++ emit_insn (gen_add3_insn (operands[0], tmp, offset)); ++ } ++ } + } + + /* Implement the canonicalize_comparison target hook for the combine +@@ -3026,6 +3074,24 @@ sh_file_start (void) + } + } + ++/* Implementation of TARGET_ASM_INTEGER for SH. Pointers to functions ++ need to be output as pointers to function descriptors for ++ FDPIC. */ ++ ++static bool ++sh_assemble_integer (rtx value, unsigned int size, int aligned_p) ++{ ++ if (TARGET_FDPIC && size == UNITS_PER_WORD ++ && GET_CODE (value) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (value)) ++ { ++ fputs ("\t.long\t", asm_out_file); ++ output_addr_const (asm_out_file, value); ++ fputs ("@FUNCDESC\n", asm_out_file); ++ return true; ++ } ++ return default_assemble_integer (value, size, aligned_p); ++} ++ + /* Check if PAT includes UNSPEC_CALLER unspec pattern. */ + static bool + unspec_caller_rtx_p (rtx pat) +@@ -3061,6 +3127,17 @@ sh_cannot_copy_insn_p (rtx_insn *insn) + return false; + + pat = PATTERN (insn); ++ ++ if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == USE) ++ return false; ++ ++ if (TARGET_FDPIC && GET_CODE (pat) == PARALLEL) ++ { ++ rtx t = XVECEXP (pat, 0, XVECLEN (pat, 0) - 1); ++ if (GET_CODE (t) == USE && unspec_caller_rtx_p (XEXP (t, 0))) ++ return true; ++ } ++ + if (GET_CODE (pat) != SET) + return false; + pat = SET_SRC (pat); +@@ -4102,8 +4179,8 @@ expand_ashiftrt (rtx *operands) + /* Load the value into an arg reg and call a helper. */ + emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]); + sprintf (func, "__ashiftrt_r4_%d", value); +- function_symbol (wrk, func, SFUNC_STATIC); +- emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk)); ++ rtx lab = function_symbol (wrk, func, SFUNC_STATIC).lab; ++ emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk, lab)); + emit_move_insn (operands[0], gen_rtx_REG (SImode, 4)); + return true; + } +@@ -7954,7 +8031,8 @@ sh_expand_prologue (void) + stack_usage += d; + } + +- if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) ++ if (flag_pic && !TARGET_FDPIC ++ && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) + emit_insn (gen_GOTaddr2picreg (const0_rtx)); + + if (SHMEDIA_REGS_STACK_ADJUST ()) +@@ -10458,7 +10536,9 @@ nonpic_symbol_mentioned_p (rtx x) + || XINT (x, 1) == UNSPEC_PLT + || XINT (x, 1) == UNSPEC_PCREL + || XINT (x, 1) == UNSPEC_SYMOFF +- || XINT (x, 1) == UNSPEC_PCREL_SYMOFF)) ++ || XINT (x, 1) == UNSPEC_PCREL_SYMOFF ++ || XINT (x, 1) == UNSPEC_GOTFUNCDESC ++ || XINT (x, 1) == UNSPEC_GOTOFFFUNCDESC)) + return false; + + fmt = GET_RTX_FORMAT (GET_CODE (x)); +@@ -10493,7 +10573,26 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED, + if (reg == NULL_RTX) + reg = gen_reg_rtx (Pmode); + +- emit_insn (gen_symGOTOFF2reg (reg, orig)); ++ if (TARGET_FDPIC ++ && GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (orig)) ++ { ++ /* Weak functions may be NULL which doesn't work with ++ GOTOFFFUNCDESC because the runtime offset is not known. */ ++ if (SYMBOL_REF_WEAK (orig)) ++ emit_insn (gen_symGOTFUNCDESC2reg (reg, orig)); ++ else ++ emit_insn (gen_symGOTOFFFUNCDESC2reg (reg, orig)); ++ } ++ else if (TARGET_FDPIC ++ && (GET_CODE (orig) == LABEL_REF ++ || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_DECL (orig) ++ && (TREE_READONLY (SYMBOL_REF_DECL (orig)) ++ || SYMBOL_REF_EXTERNAL_P (orig) ++ || DECL_SECTION_NAME(SYMBOL_REF_DECL (orig)))))) ++ /* In FDPIC, GOTOFF can only be used for writable data. */ ++ emit_insn (gen_symGOT2reg (reg, orig)); ++ else ++ emit_insn (gen_symGOTOFF2reg (reg, orig)); + return reg; + } + else if (GET_CODE (orig) == SYMBOL_REF) +@@ -10501,7 +10600,10 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED, + if (reg == NULL_RTX) + reg = gen_reg_rtx (Pmode); + +- emit_insn (gen_symGOT2reg (reg, orig)); ++ if (TARGET_FDPIC && SYMBOL_REF_FUNCTION_P (orig)) ++ emit_insn (gen_symGOTFUNCDESC2reg (reg, orig)); ++ else ++ emit_insn (gen_symGOT2reg (reg, orig)); + return reg; + } + return orig; +@@ -11539,8 +11641,39 @@ sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED) + 5 0008 00000000 l1: .long area + 6 000c 00000000 l2: .long function + ++ FDPIC needs a form that includes a function descriptor and ++ code to load the GOT register: ++ 0 0000 00000000 .long l0 ++ 1 0004 00000000 .long gotval ++ 2 0008 D302 l0: mov.l l1,r3 ++ 3 000a D203 mov.l l2,r2 ++ 4 000c 6122 mov.l @r2,r1 ++ 5 000e 5C21 mov.l @(4,r2),r12 ++ 6 0010 412B jmp @r1 ++ 7 0012 0009 nop ++ 8 0014 00000000 l1: .long area ++ 9 0018 00000000 l2: .long function ++ + SH5 (compact) uses r1 instead of r3 for the static chain. */ + ++/* Emit insns to store a value at memory address + offset. */ ++static void ++sh_emit_storesi (rtx addr, HOST_WIDE_INT offset, rtx value) ++{ ++ gcc_assert ((offset & 3) == 0); ++ emit_move_insn (offset == 0 ++ ? change_address (addr, SImode, NULL_RTX) ++ : adjust_address (addr, SImode, offset), value); ++} ++ ++/* Emit insns to store w0 at addr + offset and w1 at addr + offset + 2. */ ++static void ++sh_emit_storehi (rtx addr, HOST_WIDE_INT offset, uint16_t w0, uint16_t w1) ++{ ++ sh_emit_storesi (addr, offset, gen_int_mode (TARGET_LITTLE_ENDIAN ++ ? (w0 | (w1 << 16)) ++ : (w1 | (w0 << 16)), SImode)); ++} + + /* Emit RTL insns to initialize the variable parts of a trampoline. + FNADDR is an RTX for the address of the function's pure code. +@@ -11675,20 +11808,34 @@ sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt) + emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr)); + return; + } +- emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX), +- gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301, +- SImode)); +- emit_move_insn (adjust_address (tramp_mem, SImode, 4), +- gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009, +- SImode)); +- emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt); +- emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr); ++ if (TARGET_FDPIC) ++ { ++ rtx a = force_reg (Pmode, plus_constant (Pmode, XEXP (tramp_mem, 0), 8)); ++ ++ sh_emit_storesi (tramp_mem, 0, a); ++ sh_emit_storesi (tramp_mem, 4, sh_get_fdpic_reg_initial_val ()); ++ ++ sh_emit_storehi (tramp_mem, 8, 0xd302, 0xd203); ++ sh_emit_storehi (tramp_mem, 12, 0x6122, 0x5c21); ++ sh_emit_storehi (tramp_mem, 16, 0x412b, 0x0009); ++ ++ sh_emit_storesi (tramp_mem, 20, cxt); ++ sh_emit_storesi (tramp_mem, 24, fnaddr); ++ } ++ else ++ { ++ sh_emit_storehi (tramp_mem, 0, 0xd202, 0xd301); ++ sh_emit_storehi (tramp_mem, 4, 0x422b, 0x0009); ++ ++ sh_emit_storesi (tramp_mem, 8, cxt); ++ sh_emit_storesi (tramp_mem, 12, fnaddr); ++ } + if (TARGET_HARD_SH4 || TARGET_SH5) + { + if (!TARGET_INLINE_IC_INVALIDATE + || (!(TARGET_SH4A || TARGET_SH4_300) && TARGET_USERMODE)) + emit_library_call (function_symbol (NULL, "__ic_invalidate", +- FUNCTION_ORDINARY), ++ FUNCTION_ORDINARY).sym, + LCT_NORMAL, VOIDmode, 1, tramp, SImode); + else + emit_insn (gen_ic_invalidate_line (tramp)); +@@ -11718,7 +11865,7 @@ sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) + && (! TARGET_SHCOMPACT + || crtl->args.info.stack_regs == 0) + && ! sh_cfun_interrupt_handler_p () +- && (! flag_pic ++ && (! flag_pic || TARGET_FDPIC + || (decl && ! (TREE_PUBLIC (decl) || DECL_WEAK (decl))) + || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT))); + } +@@ -11732,7 +11879,7 @@ sh_expand_sym_label2reg (rtx reg, rtx sym, rtx lab, bool sibcall_p) + + if (!is_weak && SYMBOL_REF_LOCAL_P (sym)) + emit_insn (gen_sym_label2reg (reg, sym, lab)); +- else if (sibcall_p) ++ else if (sibcall_p && SYMBOL_REF_LOCAL_P (sym)) + emit_insn (gen_symPCREL_label2reg (reg, sym, lab)); + else + emit_insn (gen_symPLT_label2reg (reg, sym, lab)); +@@ -12733,8 +12880,16 @@ sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, + #endif + if (TARGET_SH2 && flag_pic) + { +- sibcall = gen_sibcall_pcrel (funexp, const0_rtx); +- XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2; ++ if (TARGET_FDPIC) ++ { ++ sibcall = gen_sibcall_pcrel_fdpic (funexp, const0_rtx); ++ XEXP (XVECEXP (sibcall, 0, 3), 0) = scratch2; ++ } ++ else ++ { ++ sibcall = gen_sibcall_pcrel (funexp, const0_rtx); ++ XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2; ++ } + } + else + { +@@ -12775,17 +12930,25 @@ sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, + epilogue_completed = 0; + } + +-rtx +-function_symbol (rtx target, const char *name, enum sh_function_kind kind) +-{ +- rtx sym; ++/* Return an RTX pair for the address and call site label of a function ++ NAME of kind KIND, placing the result in TARGET if not NULL. For ++ SFUNC_STATIC, if FDPIC, the LAB member of result will be set to ++ (const_int 0) if jsr should be used, or a label_ref if bsrf should ++ be used. For FDPIC, both SFUNC_GOT and SFUNC_STATIC will return the ++ address of the function itself, not a function descriptor, so they ++ can only be used with functions not using the FDPIC register that ++ are known to be called directory without a PLT entry. */ + ++function_symbol_result ++function_symbol (rtx target, const char *name, sh_function_kind kind) ++{ + /* If this is not an ordinary function, the name usually comes from a + string literal or an sprintf buffer. Make sure we use the same + string consistently, so that cse will be able to unify address loads. */ + if (kind != FUNCTION_ORDINARY) + name = IDENTIFIER_POINTER (get_identifier (name)); +- sym = gen_rtx_SYMBOL_REF (Pmode, name); ++ rtx sym = gen_rtx_SYMBOL_REF (Pmode, name); ++ rtx lab = const0_rtx; + SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION; + if (flag_pic) + switch (kind) +@@ -12802,14 +12965,25 @@ function_symbol (rtx target, const char *name, enum sh_function_kind kind) + } + case SFUNC_STATIC: + { +- /* ??? To allow cse to work, we use GOTOFF relocations. +- We could add combiner patterns to transform this into +- straight pc-relative calls with sym2PIC / bsrf when +- label load and function call are still 1:1 and in the +- same basic block during combine. */ + rtx reg = target ? target : gen_reg_rtx (Pmode); + +- emit_insn (gen_symGOTOFF2reg (reg, sym)); ++ if (TARGET_FDPIC) ++ { ++ /* We use PC-relative calls, since GOTOFF can only refer ++ to writable data. This works along with sh_sfunc_call. */ ++ lab = PATTERN (gen_call_site ()); ++ emit_insn (gen_sym_label2reg (reg, sym, lab)); ++ } ++ else ++ { ++ /* ??? To allow cse to work, we use GOTOFF relocations. ++ we could add combiner patterns to transform this into ++ straight pc-relative calls with sym2PIC / bsrf when ++ label load and function call are still 1:1 and in the ++ same basic block during combine. */ ++ emit_insn (gen_symGOTOFF2reg (reg, sym)); ++ } ++ + sym = reg; + break; + } +@@ -12817,9 +12991,9 @@ function_symbol (rtx target, const char *name, enum sh_function_kind kind) + if (target && sym != target) + { + emit_move_insn (target, sym); +- return target; ++ return function_symbol_result (target, lab); + } +- return sym; ++ return function_symbol_result (sym, lab); + } + + /* Find the number of a general purpose register in S. */ +@@ -13432,6 +13606,12 @@ sh_conditional_register_usage (void) + fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; + call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; + } ++ if (TARGET_FDPIC) ++ { ++ fixed_regs[PIC_REG] = 1; ++ call_used_regs[PIC_REG] = 1; ++ call_really_used_regs[PIC_REG] = 1; ++ } + /* Renesas saves and restores mac registers on call. */ + if (TARGET_HITACHI && ! TARGET_NOMACSAVE) + { +@@ -13460,14 +13640,32 @@ sh_conditional_register_usage (void) + static bool + sh_legitimate_constant_p (machine_mode mode, rtx x) + { +- return (TARGET_SHMEDIA +- ? ((mode != DFmode && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT) +- || x == CONST0_RTX (mode) +- || !TARGET_SHMEDIA_FPU +- || TARGET_SHMEDIA64) +- : (GET_CODE (x) != CONST_DOUBLE +- || mode == DFmode || mode == SFmode +- || mode == DImode || GET_MODE (x) == VOIDmode)); ++ if (SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) ++ { ++ rtx base, offset; ++ split_const (x, &base, &offset); ++ ++ if (GET_CODE (base) == SYMBOL_REF ++ && !offset_within_block_p (base, INTVAL (offset))) ++ return false; ++ } ++ ++ if (TARGET_FDPIC ++ && (SYMBOLIC_CONST_P (x) ++ || (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS ++ && SYMBOLIC_CONST_P (XEXP (XEXP (x, 0), 0))))) ++ return false; ++ ++ if (TARGET_SHMEDIA ++ && ((mode != DFmode && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT) ++ || x == CONST0_RTX (mode) ++ || !TARGET_SHMEDIA_FPU ++ || TARGET_SHMEDIA64)) ++ return false; ++ ++ return GET_CODE (x) != CONST_DOUBLE ++ || mode == DFmode || mode == SFmode ++ || mode == DImode || GET_MODE (x) == VOIDmode; + } + + enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT; +@@ -14558,4 +14756,41 @@ sh_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size, + } + } + ++bool ++sh_cannot_force_const_mem_p (machine_mode mode ATTRIBUTE_UNUSED, ++ rtx x ATTRIBUTE_UNUSED) ++{ ++ return TARGET_FDPIC; ++} ++ ++/* Emit insns to load the function address from FUNCDESC (an FDPIC ++ function descriptor) into r1 and the GOT address into r12, ++ returning an rtx for r1. */ ++ ++rtx ++sh_load_function_descriptor (rtx funcdesc) ++{ ++ rtx r1 = gen_rtx_REG (Pmode, R1_REG); ++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG); ++ rtx fnaddr = gen_rtx_MEM (Pmode, funcdesc); ++ rtx gotaddr = gen_rtx_MEM (Pmode, plus_constant (Pmode, funcdesc, 4)); ++ ++ emit_move_insn (r1, fnaddr); ++ /* The ABI requires the entry point address to be loaded first, so ++ prevent the load from being moved after that of the GOT ++ address. */ ++ emit_insn (gen_blockage ()); ++ emit_move_insn (pic_reg, gotaddr); ++ return r1; ++} ++ ++/* Return an rtx holding the initial value of the FDPIC register (the ++ FDPIC pointer passed in from the caller). */ ++ ++rtx ++sh_get_fdpic_reg_initial_val (void) ++{ ++ return get_hard_reg_initial_val (Pmode, PIC_REG); ++} ++ + #include "gt-sh.h" +diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h +index aafcf28..e232179 100644 +--- a/gcc/config/sh/sh.h ++++ b/gcc/config/sh/sh.h +@@ -321,7 +321,7 @@ extern int code_for_indirect_jump_scratch; + #endif + + #ifndef SUBTARGET_ASM_SPEC +-#define SUBTARGET_ASM_SPEC "" ++#define SUBTARGET_ASM_SPEC "%{mfdpic:--fdpic}" + #endif + + #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN +@@ -349,7 +349,7 @@ extern int code_for_indirect_jump_scratch; + #define ASM_ISA_DEFAULT_SPEC "" + #endif /* MASK_SH5 */ + +-#define SUBTARGET_LINK_EMUL_SUFFIX "" ++#define SUBTARGET_LINK_EMUL_SUFFIX "%{mfdpic:_fd}" + #define SUBTARGET_LINK_SPEC "" + + /* Go via SH_LINK_SPEC to avoid code replication. */ +@@ -383,8 +383,18 @@ extern int code_for_indirect_jump_scratch; + "%{m2a*:%eSH2a does not support little-endian}}" + #endif + ++#ifdef FDPIC_DEFAULT ++#define FDPIC_SELF_SPECS "%{!mno-fdpic:-mfdpic}" ++#else ++#define FDPIC_SELF_SPECS ++#endif ++ + #undef DRIVER_SELF_SPECS +-#define DRIVER_SELF_SPECS UNSUPPORTED_SH2A ++#define DRIVER_SELF_SPECS UNSUPPORTED_SH2A SUBTARGET_DRIVER_SELF_SPECS \ ++ FDPIC_SELF_SPECS ++ ++#undef SUBTARGET_DRIVER_SELF_SPECS ++#define SUBTARGET_DRIVER_SELF_SPECS + + #define ASSEMBLER_DIALECT assembler_dialect + +@@ -942,6 +952,10 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ + code access to data items. */ + #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM) + ++/* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT ++ entries would need to handle saving and restoring it). */ ++#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC ++ + #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_" + + /* Definitions for register eliminations. +@@ -1566,7 +1580,8 @@ struct sh_args { + 6 000c 00000000 l2: .long function */ + + /* Length in units of the trampoline for entering a nested function. */ +-#define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16) ++#define TRAMPOLINE_SIZE \ ++ (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : TARGET_FDPIC ? 32 : 16) + + /* Alignment required for a trampoline in bits. */ + #define TRAMPOLINE_ALIGNMENT \ +@@ -1622,6 +1637,10 @@ struct sh_args { + || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \ + : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG) + ++/* True if SYMBOL + OFFSET constants must refer to something within ++ SYMBOL's section. */ ++#define SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P TARGET_FDPIC ++ + /* Maximum number of registers that can appear in a valid memory + address. */ + #define MAX_REGS_PER_ADDRESS 2 +@@ -2262,9 +2281,11 @@ extern int current_function_interrupt; + /* We have to distinguish between code and data, so that we apply + datalabel where and only where appropriate. Use sdataN for data. */ + #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ +- ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \ +- | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \ +- | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4))) ++ ((TARGET_FDPIC \ ++ ? ((GLOBAL) ? DW_EH_PE_indirect | DW_EH_PE_datarel : DW_EH_PE_pcrel) \ ++ : ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \ ++ | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))) \ ++ | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4))) + + /* Handle special EH pointer encodings. Absolute, pc-relative, and + indirect are handled automatically. */ +@@ -2277,6 +2298,17 @@ extern int current_function_interrupt; + SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \ + if (0) goto DONE; \ + } \ ++ if (TARGET_FDPIC \ ++ && ((ENCODING) & 0xf0) == (DW_EH_PE_indirect | DW_EH_PE_datarel)) \ ++ { \ ++ fputs ("\t.ualong ", FILE); \ ++ output_addr_const (FILE, ADDR); \ ++ if (GET_CODE (ADDR) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (ADDR)) \ ++ fputs ("@GOTFUNCDESC", FILE); \ ++ else \ ++ fputs ("@GOT", FILE); \ ++ goto DONE; \ ++ } \ + } while (0) + + #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ +diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md +index d758e3b..45c9995 100644 +--- a/gcc/config/sh/sh.md ++++ b/gcc/config/sh/sh.md +@@ -170,6 +170,9 @@ (define_c_enum "unspec" [ + UNSPEC_SYMOFF + ;; (unspec [OFFSET ANCHOR] UNSPEC_PCREL_SYMOFF) == OFFSET - (ANCHOR - .). + UNSPEC_PCREL_SYMOFF ++ ;; For FDPIC ++ UNSPEC_GOTFUNCDESC ++ UNSPEC_GOTOFFFUNCDESC + ;; Misc builtins + UNSPEC_BUILTIN_STRLEN + ]) +@@ -2591,15 +2594,18 @@ (define_insn "udivsi3_sh2a" + ;; This reload would clobber the value in r0 we are trying to store. + ;; If we let reload allocate r0, then this problem can never happen. + (define_insn "udivsi3_i1" +- [(set (match_operand:SI 0 "register_operand" "=z") ++ [(set (match_operand:SI 0 "register_operand" "=z,z") + (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG))) + (clobber (reg:SI T_REG)) + (clobber (reg:SI PR_REG)) + (clobber (reg:SI R1_REG)) + (clobber (reg:SI R4_REG)) +- (use (match_operand:SI 1 "arith_reg_operand" "r"))] ++ (use (match_operand:SI 1 "arith_reg_operand" "r,r")) ++ (use (match_operand 2 "" "Z,Ccl"))] + "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1" +- "jsr @%1%#" ++ "@ ++ jsr @%1%# ++ bsrf %1\n%O2:%#" + [(set_attr "type" "sfunc") + (set_attr "needs_delay_slot" "yes")]) + +@@ -2648,7 +2654,7 @@ (define_expand "udivsi3_i4_media" + }) + + (define_insn "udivsi3_i4" +- [(set (match_operand:SI 0 "register_operand" "=y") ++ [(set (match_operand:SI 0 "register_operand" "=y,y") + (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG))) + (clobber (reg:SI T_REG)) + (clobber (reg:SI PR_REG)) +@@ -2660,16 +2666,19 @@ (define_insn "udivsi3_i4" + (clobber (reg:SI R4_REG)) + (clobber (reg:SI R5_REG)) + (clobber (reg:SI FPSCR_STAT_REG)) +- (use (match_operand:SI 1 "arith_reg_operand" "r")) ++ (use (match_operand:SI 1 "arith_reg_operand" "r,r")) ++ (use (match_operand 2 "" "Z,Ccl")) + (use (reg:SI FPSCR_MODES_REG))] + "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE" +- "jsr @%1%#" ++ "@ ++ jsr @%1%# ++ bsrf %1\n%O2:%#" + [(set_attr "type" "sfunc") + (set_attr "fp_mode" "double") + (set_attr "needs_delay_slot" "yes")]) + + (define_insn "udivsi3_i4_single" +- [(set (match_operand:SI 0 "register_operand" "=y") ++ [(set (match_operand:SI 0 "register_operand" "=y,y") + (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG))) + (clobber (reg:SI T_REG)) + (clobber (reg:SI PR_REG)) +@@ -2680,10 +2689,13 @@ (define_insn "udivsi3_i4_single" + (clobber (reg:SI R1_REG)) + (clobber (reg:SI R4_REG)) + (clobber (reg:SI R5_REG)) +- (use (match_operand:SI 1 "arith_reg_operand" "r"))] ++ (use (match_operand:SI 1 "arith_reg_operand" "r,r")) ++ (use (match_operand 2 "" "Z,Ccl"))] + "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT) + && TARGET_FPU_SINGLE" +- "jsr @%1%#" ++ "@ ++ jsr @%1%# ++ bsrf %1\n%O2:%#" + [(set_attr "type" "sfunc") + (set_attr "needs_delay_slot" "yes")]) + +@@ -2742,11 +2754,11 @@ (define_expand "udivsi3" + } + else if (TARGET_DIVIDE_CALL_FP) + { +- function_symbol (operands[3], "__udivsi3_i4", SFUNC_STATIC); ++ rtx lab = function_symbol (operands[3], "__udivsi3_i4", SFUNC_STATIC).lab; + if (TARGET_FPU_SINGLE) +- last = gen_udivsi3_i4_single (operands[0], operands[3]); ++ last = gen_udivsi3_i4_single (operands[0], operands[3], lab); + else +- last = gen_udivsi3_i4 (operands[0], operands[3]); ++ last = gen_udivsi3_i4 (operands[0], operands[3], lab); + } + else if (TARGET_SHMEDIA_FPU) + { +@@ -2771,14 +2783,14 @@ (define_expand "udivsi3" + if (TARGET_SHMEDIA) + last = gen_udivsi3_i1_media (operands[0], operands[3]); + else if (TARGET_FPU_ANY) +- last = gen_udivsi3_i4_single (operands[0], operands[3]); ++ last = gen_udivsi3_i4_single (operands[0], operands[3], const0_rtx); + else +- last = gen_udivsi3_i1 (operands[0], operands[3]); ++ last = gen_udivsi3_i1 (operands[0], operands[3], const0_rtx); + } + else + { +- function_symbol (operands[3], "__udivsi3", SFUNC_STATIC); +- last = gen_udivsi3_i1 (operands[0], operands[3]); ++ rtx lab = function_symbol (operands[3], "__udivsi3", SFUNC_STATIC).lab; ++ last = gen_udivsi3_i1 (operands[0], operands[3], lab); + } + emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]); + emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]); +@@ -2906,7 +2918,7 @@ (define_insn_and_split "*divsi_inv_call_combine" + emit_move_insn (gen_rtx_REG (DImode, R20_REG), x); + break; + } +- sym = function_symbol (NULL, name, kind); ++ sym = function_symbol (NULL, name, kind).sym; + emit_insn (gen_divsi3_media_2 (operands[0], sym)); + DONE; + } +@@ -2926,31 +2938,37 @@ (define_expand "divsi3_i4_media" + }) + + (define_insn "divsi3_i4" +- [(set (match_operand:SI 0 "register_operand" "=y") ++ [(set (match_operand:SI 0 "register_operand" "=y,y") + (div:SI (reg:SI R4_REG) (reg:SI R5_REG))) + (clobber (reg:SI PR_REG)) + (clobber (reg:DF DR0_REG)) + (clobber (reg:DF DR2_REG)) + (clobber (reg:SI FPSCR_STAT_REG)) +- (use (match_operand:SI 1 "arith_reg_operand" "r")) ++ (use (match_operand:SI 1 "arith_reg_operand" "r,r")) ++ (use (match_operand 2 "" "Z,Ccl")) + (use (reg:SI FPSCR_MODES_REG))] + "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE" +- "jsr @%1%#" ++ "@ ++ jsr @%1%# ++ bsrf %1\n%O2:%#" + [(set_attr "type" "sfunc") + (set_attr "fp_mode" "double") + (set_attr "needs_delay_slot" "yes")]) + + (define_insn "divsi3_i4_single" +- [(set (match_operand:SI 0 "register_operand" "=y") ++ [(set (match_operand:SI 0 "register_operand" "=y,y") + (div:SI (reg:SI R4_REG) (reg:SI R5_REG))) + (clobber (reg:SI PR_REG)) + (clobber (reg:DF DR0_REG)) + (clobber (reg:DF DR2_REG)) + (clobber (reg:SI R2_REG)) +- (use (match_operand:SI 1 "arith_reg_operand" "r"))] ++ (use (match_operand:SI 1 "arith_reg_operand" "r,r")) ++ (use (match_operand 2 "" "Z,Ccl"))] + "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT) + && TARGET_FPU_SINGLE" +- "jsr @%1%#" ++ "@ ++ jsr @%1%# ++ bsrf %1\n%O2:%#" + [(set_attr "type" "sfunc") + (set_attr "needs_delay_slot" "yes")]) + +@@ -2994,11 +3012,12 @@ (define_expand "divsi3" + } + else if (TARGET_DIVIDE_CALL_FP) + { +- function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC); ++ rtx lab = function_symbol (operands[3], sh_divsi3_libfunc, ++ SFUNC_STATIC).lab; + if (TARGET_FPU_SINGLE) +- last = gen_divsi3_i4_single (operands[0], operands[3]); ++ last = gen_divsi3_i4_single (operands[0], operands[3], lab); + else +- last = gen_divsi3_i4 (operands[0], operands[3]); ++ last = gen_divsi3_i4 (operands[0], operands[3], lab); + } + else if (TARGET_SH2A) + { +@@ -3113,7 +3132,7 @@ (define_expand "divsi3" + last = ((TARGET_DIVIDE_CALL2 ? gen_divsi3_media_2 : gen_divsi3_i1_media) + (operands[0], operands[3])); + else if (TARGET_FPU_ANY) +- last = gen_divsi3_i4_single (operands[0], operands[3]); ++ last = gen_divsi3_i4_single (operands[0], operands[3], const0_rtx); + else + last = gen_divsi3_i1 (operands[0], operands[3]); + } +@@ -3713,7 +3732,7 @@ (define_expand "mulsi3" + { + /* The address must be set outside the libcall, + since it goes into a pseudo. */ +- rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC); ++ rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC).sym; + rtx addr = force_reg (SImode, sym); + rtx insns = gen_mulsi3_call (operands[0], operands[1], + operands[2], addr); +@@ -4970,8 +4989,8 @@ (define_expand "ashlsi3" + { + emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]); + rtx funcaddr = gen_reg_rtx (Pmode); +- function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC); +- emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr)); ++ rtx lab = function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC).lab; ++ emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr, lab)); + + DONE; + } +@@ -5024,15 +5043,18 @@ (define_insn_and_split "ashlsi3_d" + ;; In order to make combine understand the truncation of the shift amount + ;; operand we have to allow it to use pseudo regs for the shift operands. + (define_insn "ashlsi3_d_call" +- [(set (match_operand:SI 0 "arith_reg_dest" "=z") ++ [(set (match_operand:SI 0 "arith_reg_dest" "=z,z") + (ashift:SI (reg:SI R4_REG) +- (and:SI (match_operand:SI 1 "arith_reg_operand" "z") ++ (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z") + (const_int 31)))) +- (use (match_operand:SI 2 "arith_reg_operand" "r")) ++ (use (match_operand:SI 2 "arith_reg_operand" "r,r")) ++ (use (match_operand 3 "" "Z,Ccl")) + (clobber (reg:SI T_REG)) + (clobber (reg:SI PR_REG))] + "TARGET_SH1 && !TARGET_DYNSHIFT" +- "jsr @%2%#" ++ "@ ++ jsr @%2%# ++ bsrf %2\n%O3:%#" + [(set_attr "type" "sfunc") + (set_attr "needs_delay_slot" "yes")]) + +@@ -5374,12 +5396,15 @@ (define_insn "ashrsi3_d" + (define_insn "ashrsi3_n" + [(set (reg:SI R4_REG) + (ashiftrt:SI (reg:SI R4_REG) +- (match_operand:SI 0 "const_int_operand" "i"))) ++ (match_operand:SI 0 "const_int_operand" "i,i"))) + (clobber (reg:SI T_REG)) + (clobber (reg:SI PR_REG)) +- (use (match_operand:SI 1 "arith_reg_operand" "r"))] ++ (use (match_operand:SI 1 "arith_reg_operand" "r,r")) ++ (use (match_operand 2 "" "Z,Ccl"))] + "TARGET_SH1" +- "jsr @%1%#" ++ "@ ++ jsr @%1%# ++ bsrf %1\n%O2:%#" + [(set_attr "type" "sfunc") + (set_attr "needs_delay_slot" "yes")]) + +@@ -5532,8 +5557,8 @@ (define_expand "lshrsi3" + { + emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]); + rtx funcaddr = gen_reg_rtx (Pmode); +- function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC); +- emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr)); ++ rtx lab = function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC).lab; ++ emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr, lab)); + DONE; + } + }) +@@ -5585,15 +5610,18 @@ (define_insn_and_split "lshrsi3_d" + ;; In order to make combine understand the truncation of the shift amount + ;; operand we have to allow it to use pseudo regs for the shift operands. + (define_insn "lshrsi3_d_call" +- [(set (match_operand:SI 0 "arith_reg_dest" "=z") ++ [(set (match_operand:SI 0 "arith_reg_dest" "=z,z") + (lshiftrt:SI (reg:SI R4_REG) +- (and:SI (match_operand:SI 1 "arith_reg_operand" "z") ++ (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z") + (const_int 31)))) +- (use (match_operand:SI 2 "arith_reg_operand" "r")) ++ (use (match_operand:SI 2 "arith_reg_operand" "r,r")) ++ (use (match_operand 3 "" "Z,Ccl")) + (clobber (reg:SI T_REG)) + (clobber (reg:SI PR_REG))] + "TARGET_SH1 && !TARGET_DYNSHIFT" +- "jsr @%2%#" ++ "@ ++ jsr @%2%# ++ bsrf %2\n%O3:%#" + [(set_attr "type" "sfunc") + (set_attr "needs_delay_slot" "yes")]) + +@@ -7315,7 +7343,7 @@ (define_expand "ic_invalidate_line" + } + else if (TARGET_SHCOMPACT) + { +- operands[1] = function_symbol (NULL, "__ic_invalidate", SFUNC_STATIC); ++ operands[1] = function_symbol (NULL, "__ic_invalidate", SFUNC_STATIC).sym; + operands[1] = force_reg (Pmode, operands[1]); + emit_insn (gen_ic_invalidate_line_compact (operands[0], operands[1])); + DONE; +@@ -7397,7 +7425,7 @@ (define_expand "initialize_trampoline" + + tramp = force_reg (Pmode, operands[0]); + sfun = force_reg (Pmode, function_symbol (NULL, "__init_trampoline", +- SFUNC_STATIC)); ++ SFUNC_STATIC).sym); + emit_move_insn (gen_rtx_REG (SImode, R2_REG), operands[1]); + emit_move_insn (gen_rtx_REG (SImode, R3_REG), operands[2]); + +@@ -9459,9 +9487,29 @@ (define_insn "calli" + (match_operand 1 "" "")) + (use (reg:SI FPSCR_MODES_REG)) + (clobber (reg:SI PR_REG))] +- "TARGET_SH1" ++ "TARGET_SH1 && !TARGET_FDPIC" + { +- if (TARGET_SH2A && (dbr_sequence_length () == 0)) ++ if (TARGET_SH2A && dbr_sequence_length () == 0) ++ return "jsr/n @%0"; ++ else ++ return "jsr @%0%#"; ++} ++ [(set_attr "type" "call") ++ (set (attr "fp_mode") ++ (if_then_else (eq_attr "fpu_single" "yes") ++ (const_string "single") (const_string "double"))) ++ (set_attr "needs_delay_slot" "yes") ++ (set_attr "fp_set" "unknown")]) ++ ++(define_insn "calli_fdpic" ++ [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r")) ++ (match_operand 1)) ++ (use (reg:SI FPSCR_MODES_REG)) ++ (use (reg:SI PIC_REG)) ++ (clobber (reg:SI PR_REG))] ++ "TARGET_FDPIC" ++{ ++ if (TARGET_SH2A && dbr_sequence_length () == 0) + return "jsr/n @%0"; + else + return "jsr @%0%#"; +@@ -9588,9 +9636,30 @@ (define_insn "call_valuei" + (match_operand 2 "" ""))) + (use (reg:SI FPSCR_MODES_REG)) + (clobber (reg:SI PR_REG))] +- "TARGET_SH1" ++ "TARGET_SH1 && !TARGET_FDPIC" ++{ ++ if (TARGET_SH2A && dbr_sequence_length () == 0) ++ return "jsr/n @%1"; ++ else ++ return "jsr @%1%#"; ++} ++ [(set_attr "type" "call") ++ (set (attr "fp_mode") ++ (if_then_else (eq_attr "fpu_single" "yes") ++ (const_string "single") (const_string "double"))) ++ (set_attr "needs_delay_slot" "yes") ++ (set_attr "fp_set" "unknown")]) ++ ++(define_insn "call_valuei_fdpic" ++ [(set (match_operand 0 "" "=rf") ++ (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r")) ++ (match_operand 2))) ++ (use (reg:SI FPSCR_REG)) ++ (use (reg:SI PIC_REG)) ++ (clobber (reg:SI PR_REG))] ++ "TARGET_FDPIC" + { +- if (TARGET_SH2A && (dbr_sequence_length () == 0)) ++ if (TARGET_SH2A && dbr_sequence_length () == 0) + return "jsr/n @%1"; + else + return "jsr @%1%#"; +@@ -9725,6 +9794,12 @@ (define_expand "call" + (clobber (reg:SI PR_REG))])] + "" + { ++ if (TARGET_FDPIC) ++ { ++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG); ++ emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ()); ++ } ++ + if (TARGET_SHMEDIA) + { + operands[0] = shmedia_prepare_call_address (operands[0], 0); +@@ -9759,8 +9834,8 @@ (define_expand "call" + run out of registers when adjusting fpscr for the call. */ + emit_insn (gen_force_mode_for_call ()); + +- operands[0] +- = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT); ++ operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline", ++ SFUNC_GOT).sym; + operands[0] = force_reg (SImode, operands[0]); + + emit_move_insn (r0, func); +@@ -9808,7 +9883,13 @@ (define_expand "call" + operands[1] = operands[2]; + } + +- emit_call_insn (gen_calli (operands[0], operands[1])); ++ if (TARGET_FDPIC) ++ { ++ operands[0] = sh_load_function_descriptor (operands[0]); ++ emit_call_insn (gen_calli_fdpic (operands[0], operands[1])); ++ } ++ else ++ emit_call_insn (gen_calli (operands[0], operands[1])); + DONE; + }) + +@@ -9888,7 +9969,7 @@ (define_expand "call_pop" + emit_insn (gen_force_mode_for_call ()); + + operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline", +- SFUNC_GOT); ++ SFUNC_GOT).sym; + operands[0] = force_reg (SImode, operands[0]); + + emit_move_insn (r0, func); +@@ -9913,6 +9994,12 @@ (define_expand "call_value" + (clobber (reg:SI PR_REG))])] + "" + { ++ if (TARGET_FDPIC) ++ { ++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG); ++ emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ()); ++ } ++ + if (TARGET_SHMEDIA) + { + operands[1] = shmedia_prepare_call_address (operands[1], 0); +@@ -9948,8 +10035,8 @@ (define_expand "call_value" + run out of registers when adjusting fpscr for the call. */ + emit_insn (gen_force_mode_for_call ()); + +- operands[1] +- = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT); ++ operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline", ++ SFUNC_GOT).sym; + operands[1] = force_reg (SImode, operands[1]); + + emit_move_insn (r0, func); +@@ -9997,7 +10084,14 @@ (define_expand "call_value" + else + operands[1] = force_reg (SImode, XEXP (operands[1], 0)); + +- emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2])); ++ if (TARGET_FDPIC) ++ { ++ operands[1] = sh_load_function_descriptor (operands[1]); ++ emit_call_insn (gen_call_valuei_fdpic (operands[0], operands[1], ++ operands[2])); ++ } ++ else ++ emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2])); + DONE; + }) + +@@ -10006,7 +10100,21 @@ (define_insn "sibcalli" + (match_operand 1 "" "")) + (use (reg:SI FPSCR_MODES_REG)) + (return)] +- "TARGET_SH1" ++ "TARGET_SH1 && !TARGET_FDPIC" ++ "jmp @%0%#" ++ [(set_attr "needs_delay_slot" "yes") ++ (set (attr "fp_mode") ++ (if_then_else (eq_attr "fpu_single" "yes") ++ (const_string "single") (const_string "double"))) ++ (set_attr "type" "jump_ind")]) ++ ++(define_insn "sibcalli_fdpic" ++ [(call (mem:SI (match_operand:SI 0 "register_operand" "k")) ++ (match_operand 1)) ++ (use (reg:SI FPSCR_MODES_REG)) ++ (use (reg:SI PIC_REG)) ++ (return)] ++ "TARGET_FDPIC" + "jmp @%0%#" + [(set_attr "needs_delay_slot" "yes") + (set (attr "fp_mode") +@@ -10020,7 +10128,25 @@ (define_insn "sibcalli_pcrel" + (use (match_operand 2 "" "")) + (use (reg:SI FPSCR_MODES_REG)) + (return)] +- "TARGET_SH2" ++ "TARGET_SH2 && !TARGET_FDPIC" ++{ ++ return "braf %0" "\n" ++ "%O2:%#"; ++} ++ [(set_attr "needs_delay_slot" "yes") ++ (set (attr "fp_mode") ++ (if_then_else (eq_attr "fpu_single" "yes") ++ (const_string "single") (const_string "double"))) ++ (set_attr "type" "jump_ind")]) ++ ++(define_insn "sibcalli_pcrel_fdpic" ++ [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k")) ++ (match_operand 1)) ++ (use (match_operand 2)) ++ (use (reg:SI FPSCR_MODES_REG)) ++ (use (reg:SI PIC_REG)) ++ (return)] ++ "TARGET_SH2 && TARGET_FDPIC" + { + return "braf %0" "\n" + "%O2:%#"; +@@ -10053,7 +10179,7 @@ (define_insn_and_split "sibcall_pcrel" + (use (reg:SI FPSCR_MODES_REG)) + (clobber (match_scratch:SI 2 "=&k")) + (return)] +- "TARGET_SH2" ++ "TARGET_SH2 && !TARGET_FDPIC" + "#" + "reload_completed" + [(const_int 0)] +@@ -10073,6 +10199,32 @@ (define_insn_and_split "sibcall_pcrel" + (const_string "single") (const_string "double"))) + (set_attr "type" "jump_ind")]) + ++(define_insn_and_split "sibcall_pcrel_fdpic" ++ [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand")) ++ (match_operand 1)) ++ (use (reg:SI FPSCR_MODES_REG)) ++ (use (reg:SI PIC_REG)) ++ (clobber (match_scratch:SI 2 "=k")) ++ (return)] ++ "TARGET_SH2 && TARGET_FDPIC" ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++{ ++ rtx lab = PATTERN (gen_call_site ()); ++ ++ sh_expand_sym_label2reg (operands[2], operands[0], lab, true); ++ rtx i = emit_call_insn (gen_sibcalli_pcrel_fdpic (operands[2], operands[1], ++ copy_rtx (lab))); ++ SIBLING_CALL_P (i) = 1; ++ DONE; ++} ++ [(set_attr "needs_delay_slot" "yes") ++ (set (attr "fp_mode") ++ (if_then_else (eq_attr "fpu_single" "yes") ++ (const_string "single") (const_string "double"))) ++ (set_attr "type" "jump_ind")]) ++ + (define_insn "sibcall_compact" + [(call (mem:SI (match_operand:SI 0 "register_operand" "k,k")) + (match_operand 1 "" "")) +@@ -10117,6 +10269,12 @@ (define_expand "sibcall" + (return)])] + "" + { ++ if (TARGET_FDPIC) ++ { ++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG); ++ emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ()); ++ } ++ + if (TARGET_SHMEDIA) + { + operands[0] = shmedia_prepare_call_address (operands[0], 1); +@@ -10161,8 +10319,8 @@ (define_expand "sibcall" + run out of registers when adjusting fpscr for the call. */ + emit_insn (gen_force_mode_for_call ()); + +- operands[0] +- = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT); ++ operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline", ++ SFUNC_GOT).sym; + operands[0] = force_reg (SImode, operands[0]); + + /* We don't need a return trampoline, since the callee will +@@ -10196,13 +10354,23 @@ (define_expand "sibcall" + static functions. */ + && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0))) + { +- emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1])); ++ if (TARGET_FDPIC) ++ emit_call_insn (gen_sibcall_pcrel_fdpic (XEXP (operands[0], 0), ++ operands[1])); ++ else ++ emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1])); + DONE; + } + else + operands[0] = force_reg (SImode, XEXP (operands[0], 0)); + +- emit_call_insn (gen_sibcalli (operands[0], operands[1])); ++ if (TARGET_FDPIC) ++ { ++ operands[0] = sh_load_function_descriptor (operands[0]); ++ emit_call_insn (gen_sibcalli_fdpic (operands[0], operands[1])); ++ } ++ else ++ emit_call_insn (gen_sibcalli (operands[0], operands[1])); + DONE; + }) + +@@ -10212,7 +10380,22 @@ (define_insn "sibcall_valuei" + (match_operand 2 "" ""))) + (use (reg:SI FPSCR_MODES_REG)) + (return)] +- "TARGET_SH1" ++ "TARGET_SH1 && !TARGET_FDPIC" ++ "jmp @%1%#" ++ [(set_attr "needs_delay_slot" "yes") ++ (set (attr "fp_mode") ++ (if_then_else (eq_attr "fpu_single" "yes") ++ (const_string "single") (const_string "double"))) ++ (set_attr "type" "jump_ind")]) ++ ++(define_insn "sibcall_valuei_fdpic" ++ [(set (match_operand 0 "" "=rf") ++ (call (mem:SI (match_operand:SI 1 "register_operand" "k")) ++ (match_operand 2))) ++ (use (reg:SI FPSCR_MODES_REG)) ++ (use (reg:SI PIC_REG)) ++ (return)] ++ "TARGET_FDPIC" + "jmp @%1%#" + [(set_attr "needs_delay_slot" "yes") + (set (attr "fp_mode") +@@ -10227,7 +10410,26 @@ (define_insn "sibcall_valuei_pcrel" + (use (match_operand 3 "" "")) + (use (reg:SI FPSCR_MODES_REG)) + (return)] +- "TARGET_SH2" ++ "TARGET_SH2 && !TARGET_FDPIC" ++{ ++ return "braf %1" "\n" ++ "%O3:%#"; ++} ++ [(set_attr "needs_delay_slot" "yes") ++ (set (attr "fp_mode") ++ (if_then_else (eq_attr "fpu_single" "yes") ++ (const_string "single") (const_string "double"))) ++ (set_attr "type" "jump_ind")]) ++ ++(define_insn "sibcall_valuei_pcrel_fdpic" ++ [(set (match_operand 0 "" "=rf") ++ (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k")) ++ (match_operand 2))) ++ (use (match_operand 3)) ++ (use (reg:SI FPSCR_MODES_REG)) ++ (use (reg:SI PIC_REG)) ++ (return)] ++ "TARGET_SH2 && TARGET_FDPIC" + { + return "braf %1" "\n" + "%O3:%#"; +@@ -10245,7 +10447,7 @@ (define_insn_and_split "sibcall_value_pcrel" + (use (reg:SI FPSCR_MODES_REG)) + (clobber (match_scratch:SI 3 "=&k")) + (return)] +- "TARGET_SH2" ++ "TARGET_SH2 && !TARGET_FDPIC" + "#" + "reload_completed" + [(const_int 0)] +@@ -10267,6 +10469,35 @@ (define_insn_and_split "sibcall_value_pcrel" + (const_string "single") (const_string "double"))) + (set_attr "type" "jump_ind")]) + ++(define_insn_and_split "sibcall_value_pcrel_fdpic" ++ [(set (match_operand 0 "" "=rf") ++ (call (mem:SI (match_operand:SI 1 "symbol_ref_operand")) ++ (match_operand 2))) ++ (use (reg:SI FPSCR_MODES_REG)) ++ (use (reg:SI PIC_REG)) ++ (clobber (match_scratch:SI 3 "=k")) ++ (return)] ++ "TARGET_SH2 && TARGET_FDPIC" ++ "#" ++ "&& reload_completed" ++ [(const_int 0)] ++{ ++ rtx lab = PATTERN (gen_call_site ()); ++ ++ sh_expand_sym_label2reg (operands[3], operands[1], lab, true); ++ rtx i = emit_call_insn (gen_sibcall_valuei_pcrel_fdpic (operands[0], ++ operands[3], ++ operands[2], ++ copy_rtx (lab))); ++ SIBLING_CALL_P (i) = 1; ++ DONE; ++} ++ [(set_attr "needs_delay_slot" "yes") ++ (set (attr "fp_mode") ++ (if_then_else (eq_attr "fpu_single" "yes") ++ (const_string "single") (const_string "double"))) ++ (set_attr "type" "jump_ind")]) ++ + (define_insn "sibcall_value_compact" + [(set (match_operand 0 "" "=rf,rf") + (call (mem:SI (match_operand:SI 1 "register_operand" "k,k")) +@@ -10314,6 +10545,12 @@ (define_expand "sibcall_value" + (return)])] + "" + { ++ if (TARGET_FDPIC) ++ { ++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG); ++ emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ()); ++ } ++ + if (TARGET_SHMEDIA) + { + operands[1] = shmedia_prepare_call_address (operands[1], 1); +@@ -10359,8 +10596,8 @@ (define_expand "sibcall_value" + run out of registers when adjusting fpscr for the call. */ + emit_insn (gen_force_mode_for_call ()); + +- operands[1] +- = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT); ++ operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline", ++ SFUNC_GOT).sym; + operands[1] = force_reg (SImode, operands[1]); + + /* We don't need a return trampoline, since the callee will +@@ -10395,15 +10632,27 @@ (define_expand "sibcall_value" + static functions. */ + && SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0))) + { +- emit_call_insn (gen_sibcall_value_pcrel (operands[0], +- XEXP (operands[1], 0), +- operands[2])); ++ if (TARGET_FDPIC) ++ emit_call_insn (gen_sibcall_value_pcrel_fdpic (operands[0], ++ XEXP (operands[1], 0), ++ operands[2])); ++ else ++ emit_call_insn (gen_sibcall_value_pcrel (operands[0], ++ XEXP (operands[1], 0), ++ operands[2])); + DONE; + } + else + operands[1] = force_reg (SImode, XEXP (operands[1], 0)); + +- emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2])); ++ if (TARGET_FDPIC) ++ { ++ operands[1] = sh_load_function_descriptor (operands[1]); ++ emit_call_insn (gen_sibcall_valuei_fdpic (operands[0], operands[1], ++ operands[2])); ++ } ++ else ++ emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2])); + DONE; + }) + +@@ -10487,7 +10736,7 @@ (define_expand "call_value_pop" + emit_insn (gen_force_mode_for_call ()); + + operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline", +- SFUNC_GOT); ++ SFUNC_GOT).sym; + operands[1] = force_reg (SImode, operands[1]); + + emit_move_insn (r0, func); +@@ -10685,6 +10934,13 @@ (define_expand "GOTaddr2picreg" + DONE; + } + ++ if (TARGET_FDPIC) ++ { ++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG); ++ emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ()); ++ DONE; ++ } ++ + operands[1] = gen_rtx_REG (Pmode, PIC_REG); + operands[2] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME); + +@@ -10820,10 +11076,13 @@ (define_expand "symGOT_load" + rtx mem; + bool stack_chk_guard_p = false; + ++ rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val () ++ : gen_rtx_REG (Pmode, PIC_REG); ++ + operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); + operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); + +- if (!TARGET_SHMEDIA ++ if (!TARGET_SHMEDIA && !TARGET_FDPIC + && flag_stack_protect + && GET_CODE (operands[1]) == CONST + && GET_CODE (XEXP (operands[1], 0)) == UNSPEC +@@ -10862,8 +11121,7 @@ (define_expand "symGOT_load" + if (stack_chk_guard_p) + emit_insn (gen_chk_guard_add (operands[3], operands[2])); + else +- emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2], +- gen_rtx_REG (Pmode, PIC_REG))); ++ emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2], picreg)); + + /* N.B. This is not constant for a GOTPLT relocation. */ + mem = gen_rtx_MEM (Pmode, operands[3]); +@@ -10894,6 +11152,23 @@ (define_expand "symGOT2reg" + DONE; + }) + ++(define_expand "sym2GOTFUNCDESC" ++ [(const (unspec [(match_operand 0)] UNSPEC_GOTFUNCDESC))] ++ "TARGET_FDPIC") ++ ++(define_expand "symGOTFUNCDESC2reg" ++ [(match_operand 0) (match_operand 1)] ++ "TARGET_FDPIC" ++{ ++ rtx gotsym = gen_sym2GOTFUNCDESC (operands[1]); ++ PUT_MODE (gotsym, Pmode); ++ rtx insn = emit_insn (gen_symGOT_load (operands[0], gotsym)); ++ ++ MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1; ++ ++ DONE; ++}) ++ + (define_expand "symGOTPLT2reg" + [(match_operand 0 "" "") (match_operand 1 "" "")] + "" +@@ -10920,18 +11195,39 @@ (define_expand "symGOTOFF2reg" + ? operands[0] + : gen_reg_rtx (GET_MODE (operands[0]))); + ++ rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val () ++ : gen_rtx_REG (Pmode, PIC_REG); ++ + gotoffsym = gen_sym2GOTOFF (operands[1]); + PUT_MODE (gotoffsym, Pmode); + emit_move_insn (t, gotoffsym); +- insn = emit_move_insn (operands[0], +- gen_rtx_PLUS (Pmode, t, +- gen_rtx_REG (Pmode, PIC_REG))); ++ insn = emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg)); + + set_unique_reg_note (insn, REG_EQUAL, operands[1]); + + DONE; + }) + ++(define_expand "sym2GOTOFFFUNCDESC" ++ [(const (unspec [(match_operand 0)] UNSPEC_GOTOFFFUNCDESC))] ++ "TARGET_FDPIC") ++ ++(define_expand "symGOTOFFFUNCDESC2reg" ++ [(match_operand 0) (match_operand 1)] ++ "TARGET_FDPIC" ++{ ++ rtx picreg = sh_get_fdpic_reg_initial_val (); ++ rtx t = !can_create_pseudo_p () ++ ? operands[0] ++ : gen_reg_rtx (GET_MODE (operands[0])); ++ ++ rtx gotoffsym = gen_sym2GOTOFFFUNCDESC (operands[1]); ++ PUT_MODE (gotoffsym, Pmode); ++ emit_move_insn (t, gotoffsym); ++ emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg)); ++ DONE; ++}) ++ + (define_expand "symPLT_label2reg" + [(set (match_operand:SI 0 "" "") + (const:SI +@@ -12688,18 +12984,22 @@ (define_expand "movmemsi" + (define_insn "block_move_real" + [(parallel [(set (mem:BLK (reg:SI R4_REG)) + (mem:BLK (reg:SI R5_REG))) +- (use (match_operand:SI 0 "arith_reg_operand" "r")) ++ (use (match_operand:SI 0 "arith_reg_operand" "r,r")) ++ (use (match_operand 1 "" "Z,Ccl")) + (clobber (reg:SI PR_REG)) + (clobber (reg:SI R0_REG))])] + "TARGET_SH1 && ! TARGET_HARD_SH4" +- "jsr @%0%#" ++ "@ ++ jsr @%0%# ++ bsrf %0\n%O1:%#" + [(set_attr "type" "sfunc") + (set_attr "needs_delay_slot" "yes")]) + + (define_insn "block_lump_real" + [(parallel [(set (mem:BLK (reg:SI R4_REG)) + (mem:BLK (reg:SI R5_REG))) +- (use (match_operand:SI 0 "arith_reg_operand" "r")) ++ (use (match_operand:SI 0 "arith_reg_operand" "r,r")) ++ (use (match_operand 1 "" "Z,Ccl")) + (use (reg:SI R6_REG)) + (clobber (reg:SI PR_REG)) + (clobber (reg:SI T_REG)) +@@ -12708,27 +13008,33 @@ (define_insn "block_lump_real" + (clobber (reg:SI R6_REG)) + (clobber (reg:SI R0_REG))])] + "TARGET_SH1 && ! TARGET_HARD_SH4" +- "jsr @%0%#" ++ "@ ++ jsr @%0%# ++ bsrf %0\n%O1:%#" + [(set_attr "type" "sfunc") + (set_attr "needs_delay_slot" "yes")]) + + (define_insn "block_move_real_i4" + [(parallel [(set (mem:BLK (reg:SI R4_REG)) + (mem:BLK (reg:SI R5_REG))) +- (use (match_operand:SI 0 "arith_reg_operand" "r")) ++ (use (match_operand:SI 0 "arith_reg_operand" "r,r")) ++ (use (match_operand 1 "" "Z,Ccl")) + (clobber (reg:SI PR_REG)) + (clobber (reg:SI R0_REG)) + (clobber (reg:SI R1_REG)) + (clobber (reg:SI R2_REG))])] + "TARGET_HARD_SH4" +- "jsr @%0%#" ++ "@ ++ jsr @%0%# ++ bsrf %0\n%O1:%#" + [(set_attr "type" "sfunc") + (set_attr "needs_delay_slot" "yes")]) + + (define_insn "block_lump_real_i4" + [(parallel [(set (mem:BLK (reg:SI R4_REG)) + (mem:BLK (reg:SI R5_REG))) +- (use (match_operand:SI 0 "arith_reg_operand" "r")) ++ (use (match_operand:SI 0 "arith_reg_operand" "r,r")) ++ (use (match_operand 1 "" "Z,Ccl")) + (use (reg:SI R6_REG)) + (clobber (reg:SI PR_REG)) + (clobber (reg:SI T_REG)) +@@ -12740,7 +13046,9 @@ (define_insn "block_lump_real_i4" + (clobber (reg:SI R2_REG)) + (clobber (reg:SI R3_REG))])] + "TARGET_HARD_SH4" +- "jsr @%0%#" ++ "@ ++ jsr @%0%# ++ bsrf %0\n%O1:%#" + [(set_attr "type" "sfunc") + (set_attr "needs_delay_slot" "yes")]) + +diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt +index 8875b5d..c2e8aca 100644 +--- a/gcc/config/sh/sh.opt ++++ b/gcc/config/sh/sh.opt +@@ -264,6 +264,10 @@ mdivsi3_libfunc= + Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("") + Specify name for 32 bit signed division function + ++mfdpic ++Target Report Var(TARGET_FDPIC) Init(0) ++Generate ELF FDPIC code ++ + mfmovd + Target RejectNegative Mask(FMOVD) + Enable the use of 64-bit floating point registers in fmov instructions. See -mdalign if 64-bit alignment is required. +diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi +index 1fd773e..fe57b97 100644 +--- a/gcc/doc/install.texi ++++ b/gcc/doc/install.texi +@@ -1810,6 +1810,9 @@ When neither of these configure options are used, the default will be + 128-bit @code{long double} when built against GNU C Library 2.4 and later, + 64-bit @code{long double} otherwise. + ++@item --enable-fdpic ++On SH Linux systems, generate ELF FDPIC code. ++ + @item --with-gmp=@var{pathname} + @itemx --with-gmp-include=@var{pathname} + @itemx --with-gmp-lib=@var{pathname} +diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi +index ebfaaa1..8b26eac 100644 +--- a/gcc/doc/invoke.texi ++++ b/gcc/doc/invoke.texi +@@ -21178,6 +21178,10 @@ in effect. + Prefer zero-displacement conditional branches for conditional move instruction + patterns. This can result in faster code on the SH4 processor. + ++@item -mfdpic ++@opindex fdpic ++Generate code using the FDPIC ABI. ++ + @end table + + @node Solaris 2 Options +diff --git a/include/longlong.h b/include/longlong.h +index a0b2ce1..d7ef671 100644 +--- a/include/longlong.h ++++ b/include/longlong.h +@@ -1102,6 +1102,33 @@ extern UDItype __umulsidi3 (USItype, USItype); + /* This is the same algorithm as __udiv_qrnnd_c. */ + #define UDIV_NEEDS_NORMALIZATION 1 + ++#ifdef __FDPIC__ ++/* FDPIC needs a special version of the asm fragment to extract the ++ code address from the function descriptor. __udiv_qrnnd_16 is ++ assumed to be local and not to use the GOT, so loading r12 is ++ not needed. */ ++#define udiv_qrnnd(q, r, n1, n0, d) \ ++ do { \ ++ extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \ ++ __attribute__ ((visibility ("hidden"))); \ ++ /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \ ++ __asm__ ( \ ++ "mov%M4 %4,r5\n" \ ++" swap.w %3,r4\n" \ ++" swap.w r5,r6\n" \ ++" mov.l @%5,r2\n" \ ++" jsr @r2\n" \ ++" shll16 r6\n" \ ++" swap.w r4,r4\n" \ ++" mov.l @%5,r2\n" \ ++" jsr @r2\n" \ ++" swap.w r1,%0\n" \ ++" or r1,%0" \ ++ : "=r" (q), "=&z" (r) \ ++ : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \ ++ : "r1", "r2", "r4", "r5", "r6", "pr", "t"); \ ++ } while (0) ++#else + #define udiv_qrnnd(q, r, n1, n0, d) \ + do { \ + extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \ +@@ -1121,6 +1148,7 @@ extern UDItype __umulsidi3 (USItype, USItype); + : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \ + : "r1", "r2", "r4", "r5", "r6", "pr", "t"); \ + } while (0) ++#endif /* __FDPIC__ */ + + #define UDIV_TIME 80 + +diff --git a/libitm/config/sh/sjlj.S b/libitm/config/sh/sjlj.S +index 410cef6..8c83fce 100644 +--- a/libitm/config/sh/sjlj.S ++++ b/libitm/config/sh/sjlj.S +@@ -58,9 +58,6 @@ _ITM_beginTransaction: + jsr @r1 + mov r15, r5 + #else +- mova .Lgot, r0 +- mov.l .Lgot, r12 +- add r0, r12 + mov.l .Lbegin, r1 + bsrf r1 + mov r15, r5 +@@ -79,14 +76,12 @@ _ITM_beginTransaction: + nop + cfi_endproc + +- .align 2 +-.Lgot: +- .long _GLOBAL_OFFSET_TABLE_ ++ .align 2 + .Lbegin: + #if defined HAVE_ATTRIBUTE_VISIBILITY || !defined __PIC__ + .long GTM_begin_transaction + #else +- .long GTM_begin_transaction@PLT-(.Lbegin0-.) ++ .long GTM_begin_transaction@PCREL-(.Lbegin0-.) + #endif + .size _ITM_beginTransaction, . - _ITM_beginTransaction + diff --git a/patches/gcc-5.3.0/0008-shsibcall.diff b/patches/gcc-5.3.0/0008-shsibcall.diff new file mode 100644 index 0000000..85df33f --- /dev/null +++ b/patches/gcc-5.3.0/0008-shsibcall.diff @@ -0,0 +1,39 @@ +--- a/gcc/config/sh/sh.md ++++ b/gcc/config/sh/sh.md +@@ -10476,7 +10476,7 @@ + (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "")) + (match_operand 2 "" ""))) + (use (reg:SI FPSCR_MODES_REG)) +- (clobber (match_scratch:SI 3 "=&k")) ++ (clobber (reg:SI R1_REG)) + (return)] + "TARGET_SH2 && !TARGET_FDPIC" + "#" +@@ -10491,6 +10495,8 @@ + rtx lab = PATTERN (gen_call_site ()); + rtx call_insn; + ++ operands[3] = gen_rtx_REG (SImode, R1_REG); ++ + sh_expand_sym_label2reg (operands[3], operands[1], lab, true); + call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0], + operands[3], +@@ -10511,7 +10519,7 @@ + (match_operand 2))) + (use (reg:SI FPSCR_MODES_REG)) + (use (reg:SI PIC_REG)) +- (clobber (match_scratch:SI 3 "=k")) ++ (clobber (reg:SI R1_REG)) + (return)] + "TARGET_SH2 && TARGET_FDPIC" + "#" +@@ -10520,6 +10528,8 @@ + { + rtx lab = PATTERN (gen_call_site ()); + ++ operands[3] = gen_rtx_REG (SImode, R1_REG); ++ + sh_expand_sym_label2reg (operands[3], operands[1], lab, true); + rtx i = emit_call_insn (gen_sibcall_valuei_pcrel_fdpic (operands[0], + operands[3], + diff --git a/patches/gcc-5.3.0/0009-mipsdw.diff b/patches/gcc-5.3.0/0009-mipsdw.diff new file mode 100644 index 0000000..de1144a --- /dev/null +++ b/patches/gcc-5.3.0/0009-mipsdw.diff @@ -0,0 +1,11 @@ +--- a/libgcc/config/mips/linux-unwind.h 2016-04-07 23:08:58.088577977 +0000 ++++ b/libgcc/config/mips/linux-unwind.h 2016-04-07 23:04:34.016523639 +0000 +@@ -27,7 +27,7 @@ + state data appropriately. See unwind-dw2.c for the structs. */ + + #include +-#include ++#include + + /* The third parameter to the signal handler points to something with + * this structure defined in asm/ucontext.h, but the name clashes with diff --git a/patches/gcc-5.3.0/0010-cfns-inline-fix.diff b/patches/gcc-5.3.0/0010-cfns-inline-fix.diff new file mode 100644 index 0000000..8f21223 --- /dev/null +++ b/patches/gcc-5.3.0/0010-cfns-inline-fix.diff @@ -0,0 +1,24 @@ +diff --git a/gcc/cp/cfns.h b/gcc/cp/cfns.h +index 1c6665d..69699c4 100644 +--- a/gcc/cp/cfns.h ++++ b/gcc/cp/cfns.h +@@ -54,6 +54,7 @@ static unsigned int hash (const char *, unsigned int); + #ifdef __GNUC__ + __inline + #endif ++static + const char * libc_name_p (const char *, unsigned int); + /* maximum key range = 391, duplicates = 0 */ + +@@ -124,10 +125,8 @@ hash (register const char *str, register unsigned int len) + + #ifdef __GNUC__ + __inline +-#ifdef __GNUC_STDC_INLINE__ +-__attribute__ ((__gnu_inline__)) +-#endif + #endif ++static + const char * + libc_name_p (register const char *str, register unsigned int len) + { diff --git a/patches/gcc-5.3.0/0011-m68k.diff b/patches/gcc-5.3.0/0011-m68k.diff new file mode 100644 index 0000000..b3765bf --- /dev/null +++ b/patches/gcc-5.3.0/0011-m68k.diff @@ -0,0 +1,36 @@ +diff -ur gcc-6.4.0/gcc/config/m68k/linux.h gcc-6.4.0.new/gcc/config/m68k/linux.h +--- gcc-6.4.0/gcc/config/m68k/linux.h 2016-01-04 09:30:50.000000000 -0500 ++++ gcc-6.4.0.new/gcc/config/m68k/linux.h 2018-06-12 20:03:47.047502695 -0400 +@@ -73,6 +73,9 @@ + + #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" + ++#undef MUSL_DYNAMIC_LINKER ++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-m68k.so.1" ++ + #undef LINK_SPEC + #define LINK_SPEC "-m m68kelf %{shared} \ + %{!shared: \ +diff -ur gcc-6.4.0/libgcc/config/m68k/linux-atomic.c gcc-6.4.0.new/libgcc/config/m68k/linux-atomic.c +--- gcc-6.4.0/libgcc/config/m68k/linux-atomic.c 2016-01-04 09:30:50.000000000 -0500 ++++ gcc-6.4.0.new/libgcc/config/m68k/linux-atomic.c 2018-06-07 16:15:11.610163418 -0400 +@@ -33,7 +33,6 @@ + using the kernel helper defined below. There is no support for + 64-bit operations yet. */ + +-#include + #include + + #ifndef __NR_atomic_cmpxchg_32 +diff -ur gcc-6.4.0/libgcc/config/m68k/linux-unwind.h gcc-6.4.0.new/libgcc/config/m68k/linux-unwind.h +--- gcc-6.4.0/libgcc/config/m68k/linux-unwind.h 2016-01-04 09:30:50.000000000 -0500 ++++ gcc-6.4.0.new/libgcc/config/m68k/linux-unwind.h 2018-06-07 16:17:16.964591108 -0400 +@@ -37,7 +37,7 @@ + stack_t uc_stack; + mcontext_t uc_mcontext; + unsigned long uc_filler[80]; +- __sigset_t uc_sigmask; ++ sigset_t uc_sigmask; + }; + + #define MD_FALLBACK_FRAME_STATE_FOR m68k_fallback_frame_state diff --git a/patches/gcc-5.3.0/0016-invalid_tls_model.diff b/patches/gcc-5.3.0/0016-invalid_tls_model.diff new file mode 100644 index 0000000..d3b2b8e --- /dev/null +++ b/patches/gcc-5.3.0/0016-invalid_tls_model.diff @@ -0,0 +1,51 @@ +--- gcc-7.3.0/libgomp/configure.tgt.orig 2018-09-25 13:44:16.654561098 -0400 ++++ gcc-7.3.0/libgomp/configure.tgt 2018-09-25 13:44:50.452688100 -0400 +@@ -10,23 +10,6 @@ + # XCFLAGS Add extra compile flags to use. + # XLDFLAGS Add extra link flags to use. + +-# Optimize TLS usage by avoiding the overhead of dynamic allocation. +-if test $gcc_cv_have_tls = yes ; then +- case "${target}" in +- +- *-*-k*bsd*-gnu*) +- ;; +- +- *-*-linux* | *-*-gnu*) +- XCFLAGS="${XCFLAGS} -ftls-model=initial-exec" +- ;; +- +- *-*-rtems*) +- XCFLAGS="${XCFLAGS} -ftls-model=local-exec" +- ;; +- esac +-fi +- + # Since we require POSIX threads, assume a POSIX system by default. + config_path="posix" + +--- gcc-7.3.0/libitm/configure.tgt.orig 2018-09-25 13:47:31.019296903 -0400 ++++ gcc-7.3.0/libitm/configure.tgt 2018-09-25 13:47:37.676322335 -0400 +@@ -27,22 +27,6 @@ + # XCFLAGS Add extra compile flags to use. + # XLDFLAGS Add extra link flags to use. + +-# Optimize TLS usage by avoiding the overhead of dynamic allocation. +-if test "$gcc_cv_have_tls" = yes ; then +- case "${target}" in +- +- # For x86, we use slots in the TCB head for most of our TLS. +- # The setup of those slots in beginTransaction can afford to +- # use the global-dynamic model. +- i[456]86-*-linux* | x86_64-*-linux*) +- ;; +- +- *-*-linux*) +- XCFLAGS="${XCFLAGS} -ftls-model=initial-exec" +- ;; +- esac +-fi +- + # Map the target cpu to an ARCH sub-directory. At the same time, + # work out any special compilation flags as necessary. + case "${target_cpu}" in diff --git a/patches/gcc-5.3.0/0017-fix-gthr-weak-refs-for-libgcc.patch b/patches/gcc-5.3.0/0017-fix-gthr-weak-refs-for-libgcc.patch new file mode 100644 index 0000000..56291a2 --- /dev/null +++ b/patches/gcc-5.3.0/0017-fix-gthr-weak-refs-for-libgcc.patch @@ -0,0 +1,51 @@ +From 51a354a0fb54165d505bfed9819c0440027312d9 Mon Sep 17 00:00:00 2001 +From: Szabolcs Nagy +Date: Sun, 22 Sep 2019 23:04:48 +0000 +Subject: [PATCH] fix gthr weak refs for libgcc + +ideally gthr-posix.h should be fixed not to use weak refs for +single thread detection by default since that's unsafe. + +currently we have to opt out explicitly from the unsafe behaviour +in the configure machinery of each target lib that uses gthr and +musl missed libgcc previously. + +related bugs and discussions +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78017 +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87189 +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91737 +https://sourceware.org/bugzilla/show_bug.cgi?id=5784 +https://sourceware.org/ml/libc-alpha/2012-09/msg00192.html +https://sourceware.org/ml/libc-alpha/2019-08/msg00438.html +--- + libgcc/config.host | 7 +++++++ + libgcc/config/t-gthr-noweak | 2 ++ + 2 files changed, 9 insertions(+) + create mode 100644 libgcc/config/t-gthr-noweak + +diff --git a/libgcc/config.host b/libgcc/config.host +index 122113fc519..fe1b9ab93d5 100644 +--- a/libgcc/config.host ++++ b/libgcc/config.host +@@ -1500,3 +1500,10 @@ aarch64*-*-*) + tm_file="${tm_file} aarch64/value-unwind.h" + ;; + esac ++ ++case ${host} in ++*-*-musl*) ++ # The gthr weak references are unsafe with static linking ++ tmake_file="$tmake_file t-gthr-noweak" ++ ;; ++esac +diff --git a/libgcc/config/t-gthr-noweak b/libgcc/config/t-gthr-noweak +new file mode 100644 +index 00000000000..45a21e9361d +--- /dev/null ++++ b/libgcc/config/t-gthr-noweak +@@ -0,0 +1,2 @@ ++# Don't use weak references for single-thread detection ++HOST_LIBGCC2_CFLAGS += -DGTHREAD_USE_WEAK=0 +-- +2.17.1 + diff --git a/patches/gcc-5.3.0/0018-libstdc++-futex-time64.diff b/patches/gcc-5.3.0/0018-libstdc++-futex-time64.diff new file mode 100644 index 0000000..08f6261 --- /dev/null +++ b/patches/gcc-5.3.0/0018-libstdc++-futex-time64.diff @@ -0,0 +1,18 @@ +--- gcc-9.2.0/libstdc++-v3/src/c++11/futex.cc.orig 2020-01-20 14:55:05.507548334 -0500 ++++ gcc-9.2.0/libstdc++-v3/src/c++11/futex.cc 2020-01-20 14:56:52.458268068 -0500 +@@ -61,7 +61,15 @@ + struct timeval tv; + gettimeofday (&tv, NULL); + // Convert the absolute timeout value to a relative timeout ++#if defined(SYS_futex_time64) && SYS_futex_time64 != SYS_futex ++ struct ++ { ++ long tv_sec; ++ long tv_nsec; ++ } rt; ++#else + struct timespec rt; ++#endif + rt.tv_sec = __s.count() - tv.tv_sec; + rt.tv_nsec = __ns.count() - tv.tv_usec * 1000; + if (rt.tv_nsec < 0) diff --git a/patches/gcc-5.3.0/0019-m68k-sqrt.diff b/patches/gcc-5.3.0/0019-m68k-sqrt.diff new file mode 100644 index 0000000..5d46272 --- /dev/null +++ b/patches/gcc-5.3.0/0019-m68k-sqrt.diff @@ -0,0 +1,18 @@ +--- gcc-9.2.0.orig/gcc/config/m68k/m68k.md 2019-01-01 07:31:55.000000000 -0500 ++++ gcc-9.2.0/gcc/config/m68k/m68k.md 2020-07-01 15:57:20.528408009 -0400 +@@ -4126,13 +4126,13 @@ + (define_expand "sqrt2" + [(set (match_operand:FP 0 "nonimmediate_operand" "") + (sqrt:FP (match_operand:FP 1 "general_operand" "")))] +- "TARGET_HARD_FLOAT" ++ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU" + "") + + (define_insn "sqrt2_68881" + [(set (match_operand:FP 0 "nonimmediate_operand" "=f") + (sqrt:FP (match_operand:FP 1 "general_operand" "fm")))] +- "TARGET_68881" ++ "TARGET_68881 && TARGET_68040" + { + if (FP_REG_P (operands[1])) + return "fsqrt%.x %1,%0"; diff --git a/patches/gcc-5.3.0/0020-powerpcspe-musl-ldsoname.diff b/patches/gcc-5.3.0/0020-powerpcspe-musl-ldsoname.diff new file mode 100644 index 0000000..f88fd85 --- /dev/null +++ b/patches/gcc-5.3.0/0020-powerpcspe-musl-ldsoname.diff @@ -0,0 +1,22 @@ +--- gcc-8.5.0/gcc/config/rs6000/sysv4.h.orig 2021-07-05 12:56:18.398813835 -0400 ++++ gcc-8.5.0/gcc/config/rs6000/sysv4.h 2021-06-23 21:49:57.592408186 -0400 +@@ -793,7 +793,7 @@ + #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" + #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0" + #define MUSL_DYNAMIC_LINKER \ +- "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" ++ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float|mcpu=854*|mspe:-sf}.so.1" + #if DEFAULT_LIBC == LIBC_UCLIBC + #define CHOOSE_DYNAMIC_LINKER(G, U, M) \ + "%{mglibc:" G ";:%{mmusl:" M ";:" U "}}" +--- gcc-8.5.0/gcc/config/rs6000/linux64.h.orig 2021-07-05 12:54:24.704854044 -0400 ++++ gcc-8.5.0/gcc/config/rs6000/linux64.h 2021-07-05 12:56:50.010806923 -0400 +@@ -426,7 +426,7 @@ + #endif + + #define MUSL_DYNAMIC_LINKER32 \ +- "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" ++ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float|mcpu=854*|mspe:-sf}.so.1" + #define MUSL_DYNAMIC_LINKER64 \ + "/lib/ld-musl-powerpc64" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" + diff --git a/patches/gcc-6.5.0/0001-linux_libc_has_function.diff b/patches/gcc-6.5.0/0001-linux_libc_has_function.diff new file mode 100644 index 0000000..f7e2c06 --- /dev/null +++ b/patches/gcc-6.5.0/0001-linux_libc_has_function.diff @@ -0,0 +1,13 @@ +diff --git a/gcc/config/linux.c b/gcc/config/linux.c +index 250296b..16c3768 100644 +--- a/gcc/config/linux.c ++++ b/gcc/config/linux.c +@@ -26,7 +26,7 @@ along with GCC; see the file COPYING3. If not see + bool + linux_libc_has_function (enum function_class fn_class) + { +- if (OPTION_GLIBC) ++ if (OPTION_GLIBC || OPTION_MUSL) + return true; + if (OPTION_BIONIC) + if (fn_class == function_c94 diff --git a/patches/gcc-6.5.0/0002-ssp_nonshared.diff b/patches/gcc-6.5.0/0002-ssp_nonshared.diff new file mode 100644 index 0000000..8b8bcfa --- /dev/null +++ b/patches/gcc-6.5.0/0002-ssp_nonshared.diff @@ -0,0 +1,14 @@ +diff --git a/gcc/gcc.c b/gcc/gcc.c +index 0f042b0..0576ea7 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -860,7 +860,8 @@ proper position among the other output files. */ + #ifndef LINK_SSP_SPEC + #ifdef TARGET_LIBC_PROVIDES_SSP + #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ +- "|fstack-protector-strong|fstack-protector-explicit:}" ++ "|fstack-protector-strong|fstack-protector-explicit" \ ++ ":-lssp_nonshared}" + #else + #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ + "|fstack-protector-strong|fstack-protector-explicit" \ diff --git a/patches/gcc-6.5.0/0003-mips-unwind.diff b/patches/gcc-6.5.0/0003-mips-unwind.diff new file mode 100644 index 0000000..fe02ef1 --- /dev/null +++ b/patches/gcc-6.5.0/0003-mips-unwind.diff @@ -0,0 +1,13 @@ +diff --git a/libgcc/config/mips/linux-unwind.h b/libgcc/config/mips/linux-unwind.h +index bf12de5..4035c121 100644 +--- a/libgcc/config/mips/linux-unwind.h ++++ b/libgcc/config/mips/linux-unwind.h +@@ -27,7 +27,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + state data appropriately. See unwind-dw2.c for the structs. */ + + #include +-#include ++#include + + /* The third parameter to the signal handler points to something with + * this structure defined in asm/ucontext.h, but the name clashes with diff --git a/patches/gcc-6.5.0/0004-posix_memalign.diff b/patches/gcc-6.5.0/0004-posix_memalign.diff new file mode 100644 index 0000000..16fefa3 --- /dev/null +++ b/patches/gcc-6.5.0/0004-posix_memalign.diff @@ -0,0 +1,30 @@ +diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h +index a9c2be4..2596a90 100644 +--- a/gcc/config/i386/pmm_malloc.h ++++ b/gcc/config/i386/pmm_malloc.h +@@ -27,12 +27,13 @@ + #include + + /* We can't depend on since the prototype of posix_memalign +- may not be visible. */ ++ may not be visible and we can't pollute the namespace either. */ + #ifndef __cplusplus +-extern int posix_memalign (void **, size_t, size_t); ++extern int _mm_posix_memalign (void **, size_t, size_t) + #else +-extern "C" int posix_memalign (void **, size_t, size_t) throw (); ++extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw () + #endif ++__asm__("posix_memalign"); + + static __inline void * + _mm_malloc (size_t __size, size_t __alignment) +@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment) + return malloc (__size); + if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4)) + __alignment = sizeof (void *); +- if (posix_memalign (&__ptr, __alignment, __size) == 0) ++ if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0) + return __ptr; + else + return NULL; diff --git a/patches/gcc-6.5.0/0005-cilkrts.diff b/patches/gcc-6.5.0/0005-cilkrts.diff new file mode 100644 index 0000000..2f42b44 --- /dev/null +++ b/patches/gcc-6.5.0/0005-cilkrts.diff @@ -0,0 +1,47 @@ +diff --git a/libcilkrts/runtime/os-unix.c b/libcilkrts/runtime/os-unix.c +index cb582dd..e43d7d5 100644 +--- a/libcilkrts/runtime/os-unix.c ++++ b/libcilkrts/runtime/os-unix.c +@@ -51,6 +51,7 @@ + #if defined __linux__ + # include + # include ++# include + #elif defined __APPLE__ + # include + // Uses sysconf(_SC_NPROCESSORS_ONLN) in verbose output +@@ -400,28 +401,19 @@ COMMON_SYSDEP void __cilkrts_sleep(void) + + COMMON_SYSDEP void __cilkrts_yield(void) + { +-#if __APPLE__ || __FreeBSD__ || __VXWORKS__ +- // On MacOS, call sched_yield to yield quantum. I'm not sure why we +- // don't do this on Linux also. +- sched_yield(); +-#elif defined(__DragonFly__) +- // On DragonFly BSD, call sched_yield to yield quantum. +- sched_yield(); +-#elif defined(__MIC__) ++#if defined(__MIC__) + // On MIC, pthread_yield() really trashes things. Arch's measurements + // showed that calling _mm_delay_32() (or doing nothing) was a better + // option. Delaying 1024 clock cycles is a reasonable compromise between + // giving up the processor and latency starting up when work becomes + // available + _mm_delay_32(1024); +-#elif defined(__ANDROID__) || (defined(__sun__) && defined(__svr4__)) +- // On Android and Solaris, call sched_yield to yield quantum. I'm not +- // sure why we don't do this on Linux also. +- sched_yield(); +-#else +- // On Linux, call pthread_yield (which in turn will call sched_yield) +- // to yield quantum. ++#elif defined(__sun__) && !defined(__svr4__) ++ // On old SunOS call pthread_yield to yield a quantum. + pthread_yield(); ++#else ++ // On other platforms call sched_yield to yield a quantum. ++ sched_yield(); + #endif + } + diff --git a/patches/gcc-6.5.0/0006-libatomic-test-fix.diff b/patches/gcc-6.5.0/0006-libatomic-test-fix.diff new file mode 100644 index 0000000..2b159dc --- /dev/null +++ b/patches/gcc-6.5.0/0006-libatomic-test-fix.diff @@ -0,0 +1,58 @@ +diff --git a/libatomic/testsuite/Makefile.am b/libatomic/testsuite/Makefile.am +index 561b7e2..2548a1b 100644 +--- a/libatomic/testsuite/Makefile.am ++++ b/libatomic/testsuite/Makefile.am +@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \ + _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++ ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ +diff --git a/libatomic/testsuite/Makefile.in b/libatomic/testsuite/Makefile.in +index 34f83e0..4af67ad 100644 +--- a/libatomic/testsuite/Makefile.in ++++ b/libatomic/testsuite/Makefile.in +@@ -222,6 +222,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -428,6 +429,10 @@ uninstall-am: + uninstall uninstall-am + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Tell versions [3.59,3.63) of GNU make to not export all variables. + # Otherwise a system limit (for SysV at least) may be exceeded. + .NOEXPORT: +diff --git a/libatomic/testsuite/lib/libatomic.exp b/libatomic/testsuite/lib/libatomic.exp +index cafab54..dd2e1a4 100644 +--- a/libatomic/testsuite/lib/libatomic.exp ++++ b/libatomic/testsuite/lib/libatomic.exp +@@ -74,6 +74,7 @@ proc libatomic_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -89,6 +90,8 @@ proc libatomic_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-6.5.0/0007-libgomp-test-fix.diff b/patches/gcc-6.5.0/0007-libgomp-test-fix.diff new file mode 100644 index 0000000..2916766 --- /dev/null +++ b/patches/gcc-6.5.0/0007-libgomp-test-fix.diff @@ -0,0 +1,60 @@ +diff --git a/libgomp/testsuite/Makefile.am b/libgomp/testsuite/Makefile.am +index 66a9d94..83d3f67 100644 +--- a/libgomp/testsuite/Makefile.am ++++ b/libgomp/testsuite/Makefile.am +@@ -12,6 +12,11 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" + ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ + + # Instead of directly in ../testsuite/libgomp-test-support.exp.in, the + # following variables have to be "routed through" this Makefile, for expansion +diff --git a/libgomp/testsuite/Makefile.in b/libgomp/testsuite/Makefile.in +index 4dbb406..001a163 100644 +--- a/libgomp/testsuite/Makefile.in ++++ b/libgomp/testsuite/Makefile.in +@@ -254,6 +254,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -462,6 +463,10 @@ uninstall-am: + ps ps-am uninstall uninstall-am + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Instead of directly in ../testsuite/libgomp-test-support.exp.in, the + # following variables have to be "routed through" this Makefile, for expansion + # of the several (Makefile) variables used therein. +diff --git a/libgomp/testsuite/lib/libgomp.exp b/libgomp/testsuite/lib/libgomp.exp +index 1cb4991..398ba1f 100644 +--- a/libgomp/testsuite/lib/libgomp.exp ++++ b/libgomp/testsuite/lib/libgomp.exp +@@ -85,6 +85,7 @@ proc libgomp_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -107,6 +108,8 @@ proc libgomp_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-6.5.0/0008-libitm-test-fix.diff b/patches/gcc-6.5.0/0008-libitm-test-fix.diff new file mode 100644 index 0000000..857bd64 --- /dev/null +++ b/patches/gcc-6.5.0/0008-libitm-test-fix.diff @@ -0,0 +1,58 @@ +diff --git a/libitm/testsuite/Makefile.am b/libitm/testsuite/Makefile.am +index 561b7e2..2548a1b 100644 +--- a/libitm/testsuite/Makefile.am ++++ b/libitm/testsuite/Makefile.am +@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \ + _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++ ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ +diff --git a/libitm/testsuite/Makefile.in b/libitm/testsuite/Makefile.in +index 4d79781..46cdc8b 100644 +--- a/libitm/testsuite/Makefile.in ++++ b/libitm/testsuite/Makefile.in +@@ -232,6 +232,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -438,6 +439,10 @@ uninstall-am: + uninstall uninstall-am + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Tell versions [3.59,3.63) of GNU make to not export all variables. + # Otherwise a system limit (for SysV at least) may be exceeded. + .NOEXPORT: +diff --git a/libitm/testsuite/lib/libitm.exp b/libitm/testsuite/lib/libitm.exp +index 0416296..748f492 100644 +--- a/libitm/testsuite/lib/libitm.exp ++++ b/libitm/testsuite/lib/libitm.exp +@@ -74,6 +74,7 @@ proc libitm_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -89,6 +90,8 @@ proc libitm_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-6.5.0/0009-libvtv-test-fix.diff b/patches/gcc-6.5.0/0009-libvtv-test-fix.diff new file mode 100644 index 0000000..5364944 --- /dev/null +++ b/patches/gcc-6.5.0/0009-libvtv-test-fix.diff @@ -0,0 +1,58 @@ +diff --git a/libvtv/testsuite/Makefile.am b/libvtv/testsuite/Makefile.am +index 561b7e2..2548a1b 100644 +--- a/libvtv/testsuite/Makefile.am ++++ b/libvtv/testsuite/Makefile.am +@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \ + _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++ ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ +diff --git a/libvtv/testsuite/Makefile.in b/libvtv/testsuite/Makefile.in +index e19e13e..6528f38 100644 +--- a/libvtv/testsuite/Makefile.in ++++ b/libvtv/testsuite/Makefile.in +@@ -227,6 +227,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -433,6 +434,10 @@ uninstall-am: + uninstall uninstall-am + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Tell versions [3.59,3.63) of GNU make to not export all variables. + # Otherwise a system limit (for SysV at least) may be exceeded. + .NOEXPORT: +diff --git a/libvtv/testsuite/lib/libvtv.exp b/libvtv/testsuite/lib/libvtv.exp +index edf5fdd..a596091 100644 +--- a/libvtv/testsuite/lib/libvtv.exp ++++ b/libvtv/testsuite/lib/libvtv.exp +@@ -74,6 +74,7 @@ proc libvtv_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -89,6 +90,8 @@ proc libvtv_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-6.5.0/0011-j2.diff b/patches/gcc-6.5.0/0011-j2.diff new file mode 100644 index 0000000..937254d --- /dev/null +++ b/patches/gcc-6.5.0/0011-j2.diff @@ -0,0 +1,349 @@ +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 1d5b23f..ef0a6ab 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -471,7 +471,7 @@ s390*-*-*) + extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h" + ;; + # Note the 'l'; we need to be able to match e.g. "shle" or "shl". +-sh[123456789lbe]*-*-* | sh-*-*) ++sh[123456789lbej]*-*-* | sh-*-*) + cpu_type=sh + extra_options="${extra_options} fused-madd.opt" + extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o" +@@ -2624,19 +2624,19 @@ s390x-ibm-tpf*) + extra_options="${extra_options} s390/tpf.opt" + tmake_file="${tmake_file} s390/t-s390" + ;; +-sh-*-elf* | sh[12346l]*-*-elf* | \ +- sh-*-linux* | sh[2346lbe]*-*-linux* | \ ++sh-*-elf* | sh[12346lj]*-*-elf* | \ ++ sh-*-linux* | sh[2346lbej]*-*-linux* | \ + sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \ + sh64-*-netbsd* | sh64l*-*-netbsd*) + tmake_file="${tmake_file} sh/t-sh sh/t-elf" + if test x${with_endian} = x; then + case ${target} in +- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;; ++ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;; + shbe-*-* | sheb-*-*) with_endian=big,little ;; + sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;; + shl* | sh64l* | sh*-*-linux* | \ + sh5l* | sh-superh-elf) with_endian=little,big ;; +- sh[1234]*-*-*) with_endian=big ;; ++ sh[j1234]*-*-*) with_endian=big ;; + *) with_endian=big,little ;; + esac + fi +@@ -2726,6 +2726,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;; + sh2a*) sh_cpu_target=sh2a ;; + sh2e*) sh_cpu_target=sh2e ;; ++ shj2*) sh_cpu_target=shj2;; + sh2*) sh_cpu_target=sh2 ;; + *) sh_cpu_target=sh1 ;; + esac +@@ -2750,7 +2751,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \ + sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \ + sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \ +- sh3e | sh3 | sh2e | sh2 | sh1) ;; ++ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;; + "") sh_cpu_default=${sh_cpu_target} ;; + *) echo "with_cpu=$with_cpu not supported"; exit 1 ;; + esac +@@ -2761,9 +2762,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh[1234]*) sh_multilibs=${sh_cpu_target} ;; + sh64* | sh5*) sh_multilibs=m5-32media,m5-32media-nofpu,m5-compact,m5-compact-nofpu,m5-64media,m5-64media-nofpu ;; + sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;; +- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;; ++ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;; + sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;; +- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;; ++ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;; + esac + if test x$with_fp = xno; then + sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`" +@@ -2781,7 +2782,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + m2a | m2a-single | m2a-single-only | m2a-nofpu | \ + m5-64media | m5-64media-nofpu | \ + m5-32media | m5-32media-nofpu | \ +- m5-compact | m5-compact-nofpu) ++ m5-compact | m5-compact-nofpu | \ ++ mj2) + # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition + # It is passed to MULTIILIB_OPTIONS verbatim. + TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}" +@@ -2798,7 +2800,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + done + TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'` + if test x${enable_incomplete_targets} = xyes ; then +- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1" ++ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1 SUPPORT_SHJ2=1" + fi + tm_file="$tm_file ./sysroot-suffix.h" + tmake_file="$tmake_file t-sysroot-suffix" +@@ -4269,6 +4271,8 @@ case "${target}" in + ;; + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al) + ;; ++ mj2) ++ ;; + *) + echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2 + echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2 +@@ -4478,7 +4482,7 @@ case ${target} in + tmake_file="rs6000/t-rs6000 ${tmake_file}" + ;; + +- sh[123456ble]*-*-* | sh-*-*) ++ sh[123456blej]*-*-* | sh-*-*) + c_target_objs="${c_target_objs} sh-c.o" + cxx_target_objs="${cxx_target_objs} sh-c.o" + ;; +diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h +index b08120d..63b77fa 100644 +--- a/gcc/config/sh/sh-protos.h ++++ b/gcc/config/sh/sh-protos.h +@@ -45,6 +45,7 @@ struct sh_atomic_model + hard_llcs, + soft_tcb, + soft_imask, ++ hard_cas, + + num_models + }; +@@ -88,6 +89,9 @@ extern const sh_atomic_model& selected_atomic_model (void); + #define TARGET_ATOMIC_SOFT_IMASK \ + (selected_atomic_model ().type == sh_atomic_model::soft_imask) + ++#define TARGET_ATOMIC_HARD_CAS \ ++ (selected_atomic_model ().type == sh_atomic_model::hard_cas) ++ + #ifdef RTX_CODE + extern rtx sh_fsca_sf2int (void); + extern rtx sh_fsca_int2sf (void); +diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c +index b18e59b..88520e8 100644 +--- a/gcc/config/sh/sh.c ++++ b/gcc/config/sh/sh.c +@@ -692,6 +692,7 @@ parse_validate_atomic_model_option (const char* str) + model_names[sh_atomic_model::hard_llcs] = "hard-llcs"; + model_names[sh_atomic_model::soft_tcb] = "soft-tcb"; + model_names[sh_atomic_model::soft_imask] = "soft-imask"; ++ model_names[sh_atomic_model::hard_cas] = "hard-cas"; + + const char* model_cdef_names[sh_atomic_model::num_models]; + model_cdef_names[sh_atomic_model::none] = "NONE"; +@@ -699,6 +700,7 @@ parse_validate_atomic_model_option (const char* str) + model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS"; + model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB"; + model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK"; ++ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS"; + + sh_atomic_model ret; + ret.type = sh_atomic_model::none; +@@ -780,6 +782,9 @@ got_mode_name:; + if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE) + err_ret ("cannot use atomic model %s in user mode", ret.name); + ++ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2) ++ err_ret ("atomic model %s is only available J2 targets", ret.name); ++ + return ret; + + #undef err_ret +@@ -845,6 +850,8 @@ sh_option_override (void) + sh_cpu = PROCESSOR_SH2E; + if (TARGET_SH2A) + sh_cpu = PROCESSOR_SH2A; ++ if (TARGET_SHJ2) ++ sh_cpu = PROCESSOR_SHJ2; + if (TARGET_SH3) + sh_cpu = PROCESSOR_SH3; + if (TARGET_SH3E) +diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h +index 7187c23..3bc2817 100644 +--- a/gcc/config/sh/sh.h ++++ b/gcc/config/sh/sh.h +@@ -106,6 +106,7 @@ extern int code_for_indirect_jump_scratch; + #define SUPPORT_SH4_SINGLE 1 + #define SUPPORT_SH2A 1 + #define SUPPORT_SH2A_SINGLE 1 ++#define SUPPORT_SHJ2 1 + #endif + + #define TARGET_DIVIDE_INV \ +@@ -157,6 +158,7 @@ extern int code_for_indirect_jump_scratch; + #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E) + #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E) + #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3) ++#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2) + + #if SUPPORT_SH1 + #define SUPPORT_SH2 1 +@@ -164,6 +166,7 @@ extern int code_for_indirect_jump_scratch; + #if SUPPORT_SH2 + #define SUPPORT_SH3 1 + #define SUPPORT_SH2A_NOFPU 1 ++#define SUPPORT_SHJ2 1 + #endif + #if SUPPORT_SH3 + #define SUPPORT_SH4_NOFPU 1 +@@ -211,7 +214,7 @@ extern int code_for_indirect_jump_scratch; + #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ + | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ + | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5 \ +- | MASK_FPU_SINGLE_ONLY) ++ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2) + + /* This defaults us to big-endian. */ + #ifndef TARGET_ENDIAN_DEFAULT +@@ -289,8 +292,8 @@ extern int code_for_indirect_jump_scratch; + %{m5-compact*:--isa=SHcompact} \ + %{m5-32media*:--isa=SHmedia --abi=32} \ + %{m5-64media*:--isa=SHmedia --abi=64} \ +-%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}" +- ++%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround} \ ++%{mj2:-isa=j2}" + #define ASM_SPEC SH_ASM_SPEC + + #ifndef SUBTARGET_ASM_ENDIAN_SPEC +@@ -1853,7 +1856,7 @@ struct sh_args { + + /* Nonzero if the target supports dynamic shift instructions + like shad and shld. */ +-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) ++#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2) + + /* The cost of using the dynamic shift insns (shad, shld) are the same + if they are available. If they are not available a library function will +@@ -2185,6 +2188,7 @@ enum processor_type { + PROCESSOR_SH2, + PROCESSOR_SH2E, + PROCESSOR_SH2A, ++ PROCESSOR_SHJ2, + PROCESSOR_SH3, + PROCESSOR_SH3E, + PROCESSOR_SH4, +diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt +index 1026c73..bac47ed 100644 +--- a/gcc/config/sh/sh.opt ++++ b/gcc/config/sh/sh.opt +@@ -71,6 +71,10 @@ m2e + Target RejectNegative Condition(SUPPORT_SH2E) + Generate SH2e code. + ++mj2 ++Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2) ++Generate J2 code. ++ + m3 + Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) + Generate SH3 code. +diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md +index 6f1337b..7cfd9ef 100644 +--- a/gcc/config/sh/sync.md ++++ b/gcc/config/sh/sync.md +@@ -240,6 +240,9 @@ + || (TARGET_SH4A && mode == SImode && !TARGET_ATOMIC_STRICT)) + atomic_insn = gen_atomic_compare_and_swap_hard (old_val, mem, + exp_val, new_val); ++ else if (TARGET_ATOMIC_HARD_CAS && mode == SImode) ++ atomic_insn = gen_atomic_compare_and_swap_cas (old_val, mem, ++ exp_val, new_val); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic_compare_and_swap_soft_gusa (old_val, mem, + exp_val, new_val); +@@ -306,6 +309,57 @@ + } + [(set_attr "length" "14")]) + ++(define_expand "atomic_compare_and_swapsi_cas" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "r")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{ ++ rtx mem = gen_rtx_REG (SImode, 0); ++ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0))); ++ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_insn "shj2_cas" ++ [(set (match_operand:SI 0 "register_operand" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "register_operand" "=r") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "0")] ++ UNSPECV_CMPXCHG_1)) ++ (set (reg:SI T_REG) ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))] ++ "TARGET_ATOMIC_HARD_CAS" ++ "cas.l %2,%0,@%1" ++ [(set_attr "length" "2")] ++) ++ ++(define_expand "atomic_compare_and_swapqi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ ++(define_expand "atomic_compare_and_swaphi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ + ;; The QIHImode llcs patterns modify the address register of the memory + ;; operand. In order to express that, we have to open code the memory + ;; operand. Initially the insn is expanded like every other atomic insn +diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh +index 348cc0b..8e6bdaf 100644 +--- a/gcc/config/sh/t-sh ++++ b/gcc/config/sh/t-sh +@@ -52,7 +52,7 @@ MULTILIB_MATCHES = $(shell \ + m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \ + m4,m4-100,m4-200,m4-300,m4a \ + m5-32media,m5-compact,m5-32media \ +- m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu; do \ ++ m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu,mj2; do \ + subst= ; \ + for lib in `echo $$abi|tr , ' '` ; do \ + if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \ +@@ -65,9 +65,9 @@ MULTILIB_MATCHES = $(shell \ + + # SH1 and SH2A support big endian only. + ifeq ($(DEFAULT_ENDIAN),ml) +-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + else +-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + endif + + MULTILIB_OSDIRNAMES = \ +@@ -96,6 +96,7 @@ MULTILIB_OSDIRNAMES = \ + m5-compact-nofpu=!m5-compact-nofpu $(OTHER_ENDIAN)/m5-compact-nofpu=!$(OTHER_ENDIAN)/m5-compact-nofpu \ + m5-64media=!m5-64media $(OTHER_ENDIAN)/m5-64media=!$(OTHER_ENDIAN)/m5-64media \ + m5-64media-nofpu=!m5-64media-nofpu $(OTHER_ENDIAN)/m5-64media-nofpu=!$(OTHER_ENDIAN)/m5-64media-nofpu ++ mj2=!j2 + + $(out_object_file): gt-sh.h + gt-sh.h : s-gtype ; @true diff --git a/patches/gcc-6.5.0/0012-s390x-muslldso.diff b/patches/gcc-6.5.0/0012-s390x-muslldso.diff new file mode 100644 index 0000000..62c306b --- /dev/null +++ b/patches/gcc-6.5.0/0012-s390x-muslldso.diff @@ -0,0 +1,14 @@ +diff --git a/gcc/config/s390/linux.h b/gcc/config/s390/linux.h +index 9b00af7..3aacde6 100644 +--- a/gcc/config/s390/linux.h ++++ b/gcc/config/s390/linux.h +@@ -63,6 +63,9 @@ along with GCC; see the file COPYING3. If not see + #define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1" + #define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1" + ++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-s390.so.1" ++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-s390x.so.1" ++ + #undef LINK_SPEC + #define LINK_SPEC \ + "%{m31:-m elf_s390}%{m64:-m elf64_s390} \ diff --git a/patches/gcc-6.5.0/0013-microblaze-pr65649.diff b/patches/gcc-6.5.0/0013-microblaze-pr65649.diff new file mode 100644 index 0000000..5604485 --- /dev/null +++ b/patches/gcc-6.5.0/0013-microblaze-pr65649.diff @@ -0,0 +1,20 @@ +--- gcc-6.3.0/gcc/config/microblaze/microblaze.c.orig 2017-01-02 15:07:18.924082703 -0500 ++++ gcc-6.3.0/gcc/config/microblaze/microblaze.c 2017-01-02 15:08:06.362438573 -0500 +@@ -2364,7 +2364,7 @@ + unsigned long value_long; + REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), + value_long); +- fprintf (file, HOST_WIDE_INT_PRINT_HEX, value_long); ++ fprintf (file, "0x%lx", value_long); + } + else + { +@@ -2423,7 +2423,7 @@ + print_operand_address (file, XEXP (op, 0)); + } + else if (letter == 'm') +- fprintf (file, HOST_WIDE_INT_PRINT_DEC, (1L << INTVAL (op))); ++ fprintf (file, "%ld", (1L << INTVAL (op))); + else + output_addr_const (file, op); + } diff --git a/patches/gcc-6.5.0/0014-m68k.diff b/patches/gcc-6.5.0/0014-m68k.diff new file mode 100644 index 0000000..b3765bf --- /dev/null +++ b/patches/gcc-6.5.0/0014-m68k.diff @@ -0,0 +1,36 @@ +diff -ur gcc-6.4.0/gcc/config/m68k/linux.h gcc-6.4.0.new/gcc/config/m68k/linux.h +--- gcc-6.4.0/gcc/config/m68k/linux.h 2016-01-04 09:30:50.000000000 -0500 ++++ gcc-6.4.0.new/gcc/config/m68k/linux.h 2018-06-12 20:03:47.047502695 -0400 +@@ -73,6 +73,9 @@ + + #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" + ++#undef MUSL_DYNAMIC_LINKER ++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-m68k.so.1" ++ + #undef LINK_SPEC + #define LINK_SPEC "-m m68kelf %{shared} \ + %{!shared: \ +diff -ur gcc-6.4.0/libgcc/config/m68k/linux-atomic.c gcc-6.4.0.new/libgcc/config/m68k/linux-atomic.c +--- gcc-6.4.0/libgcc/config/m68k/linux-atomic.c 2016-01-04 09:30:50.000000000 -0500 ++++ gcc-6.4.0.new/libgcc/config/m68k/linux-atomic.c 2018-06-07 16:15:11.610163418 -0400 +@@ -33,7 +33,6 @@ + using the kernel helper defined below. There is no support for + 64-bit operations yet. */ + +-#include + #include + + #ifndef __NR_atomic_cmpxchg_32 +diff -ur gcc-6.4.0/libgcc/config/m68k/linux-unwind.h gcc-6.4.0.new/libgcc/config/m68k/linux-unwind.h +--- gcc-6.4.0/libgcc/config/m68k/linux-unwind.h 2016-01-04 09:30:50.000000000 -0500 ++++ gcc-6.4.0.new/libgcc/config/m68k/linux-unwind.h 2018-06-07 16:17:16.964591108 -0400 +@@ -37,7 +37,7 @@ + stack_t uc_stack; + mcontext_t uc_mcontext; + unsigned long uc_filler[80]; +- __sigset_t uc_sigmask; ++ sigset_t uc_sigmask; + }; + + #define MD_FALLBACK_FRAME_STATE_FOR m68k_fallback_frame_state diff --git a/patches/gcc-6.5.0/0016-invalid_tls_model.diff b/patches/gcc-6.5.0/0016-invalid_tls_model.diff new file mode 100644 index 0000000..d3b2b8e --- /dev/null +++ b/patches/gcc-6.5.0/0016-invalid_tls_model.diff @@ -0,0 +1,51 @@ +--- gcc-7.3.0/libgomp/configure.tgt.orig 2018-09-25 13:44:16.654561098 -0400 ++++ gcc-7.3.0/libgomp/configure.tgt 2018-09-25 13:44:50.452688100 -0400 +@@ -10,23 +10,6 @@ + # XCFLAGS Add extra compile flags to use. + # XLDFLAGS Add extra link flags to use. + +-# Optimize TLS usage by avoiding the overhead of dynamic allocation. +-if test $gcc_cv_have_tls = yes ; then +- case "${target}" in +- +- *-*-k*bsd*-gnu*) +- ;; +- +- *-*-linux* | *-*-gnu*) +- XCFLAGS="${XCFLAGS} -ftls-model=initial-exec" +- ;; +- +- *-*-rtems*) +- XCFLAGS="${XCFLAGS} -ftls-model=local-exec" +- ;; +- esac +-fi +- + # Since we require POSIX threads, assume a POSIX system by default. + config_path="posix" + +--- gcc-7.3.0/libitm/configure.tgt.orig 2018-09-25 13:47:31.019296903 -0400 ++++ gcc-7.3.0/libitm/configure.tgt 2018-09-25 13:47:37.676322335 -0400 +@@ -27,22 +27,6 @@ + # XCFLAGS Add extra compile flags to use. + # XLDFLAGS Add extra link flags to use. + +-# Optimize TLS usage by avoiding the overhead of dynamic allocation. +-if test "$gcc_cv_have_tls" = yes ; then +- case "${target}" in +- +- # For x86, we use slots in the TCB head for most of our TLS. +- # The setup of those slots in beginTransaction can afford to +- # use the global-dynamic model. +- i[456]86-*-linux* | x86_64-*-linux*) +- ;; +- +- *-*-linux*) +- XCFLAGS="${XCFLAGS} -ftls-model=initial-exec" +- ;; +- esac +-fi +- + # Map the target cpu to an ARCH sub-directory. At the same time, + # work out any special compilation flags as necessary. + case "${target_cpu}" in diff --git a/patches/gcc-6.5.0/0017-c++-abi-break.diff b/patches/gcc-6.5.0/0017-c++-abi-break.diff new file mode 100644 index 0000000..ed5ede2 --- /dev/null +++ b/patches/gcc-6.5.0/0017-c++-abi-break.diff @@ -0,0 +1,43 @@ +From https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87822 +Author: Jonathan Wakely +Date: Wed Oct 31 13:03:25 2018 +0000 + + PR libstdc++/87822 fix layout change for nested std::pair + + The introduction of the empty __pair_base base class for PR 86751 + changed the layout of std::pair, ...>. The outer pair and + its first member both have a base class of the same type, which cannot + exist at the same address. This causes the first member to be at a + non-zero offset. + + The solution is to make the base class depend on the template + parameters, so that each pair type has a different base class type, + which allows the base classes of the outer pair and its first member to + have the same address. + + PR libstdc++/87822 + * include/bits/stl_pair.h (__pair_base): Change to class template. + (pair): Make base class type depend on template parameters. + +diff --git a/libstdc++-v3/include/bits/stl_pair.h b/libstdc++-v3/include/bits/stl_pair.h +index a30b630b4fd..5a4823ab018 100644 +--- a/libstdc++-v3/include/bits/stl_pair.h ++++ b/libstdc++-v3/include/bits/stl_pair.h +@@ -183,7 +183,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + }; + #endif // C++11 + +- class __pair_base ++ template class __pair_base + { + #if __cplusplus >= 201103L + template friend struct pair; +@@ -202,7 +202,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION + */ + template + struct pair +- : private __pair_base ++ : private __pair_base<_T1, _T2> + { + typedef _T1 first_type; /// @c first_type is the first bound type + typedef _T2 second_type; /// @c second_type is the second bound type diff --git a/patches/gcc-6.5.0/0018-Revert-PR-driver-81523-Make-static-override-pie.diff b/patches/gcc-6.5.0/0018-Revert-PR-driver-81523-Make-static-override-pie.diff new file mode 100644 index 0000000..baceb01 --- /dev/null +++ b/patches/gcc-6.5.0/0018-Revert-PR-driver-81523-Make-static-override-pie.diff @@ -0,0 +1,147 @@ +diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h +index de605b0c466..2787a3d16be 100644 +--- a/gcc/config/gnu-user.h ++++ b/gcc/config/gnu-user.h +@@ -50,28 +50,19 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + + #if defined HAVE_LD_PIE + #define GNU_USER_TARGET_STARTFILE_SPEC \ +- "%{shared:; \ +- pg|p|profile:gcrt1.o%s; \ +- static:crt1.o%s; \ +- " PIE_SPEC ":Scrt1.o%s; \ +- :crt1.o%s} \ +- crti.o%s \ +- %{static:crtbeginT.o%s; \ +- shared|" PIE_SPEC ":crtbeginS.o%s; \ +- :crtbegin.o%s} \ ++ "%{!shared: %{pg|p|profile:gcrt1.o%s;: \ ++ %{" PIE_SPEC ":Scrt1.o%s} %{" NO_PIE_SPEC ":crt1.o%s}}} \ ++ crti.o%s %{static:crtbeginT.o%s;: %{shared:crtbeginS.o%s} \ ++ %{" PIE_SPEC ":crtbeginS.o%s} \ ++ %{" NO_PIE_SPEC ":crtbegin.o%s}} \ + %{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_start_preinit.o%s; \ + fvtable-verify=std:vtv_start.o%s} \ + " CRTOFFLOADBEGIN + #else + #define GNU_USER_TARGET_STARTFILE_SPEC \ +- "%{shared:; \ +- pg|p|profile:gcrt1.o%s; \ +- :crt1.o%s} \ +- crti.o%s \ +- %{static:crtbeginT.o%s; \ +- shared|pie:crtbeginS.o%s; \ +- :crtbegin.o%s} \ ++ "%{!shared: %{pg|p|profile:gcrt1.o%s;:crt1.o%s}} \ ++ crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \ + %{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_start_preinit.o%s; \ + fvtable-verify=std:vtv_start.o%s} \ +@@ -91,20 +82,15 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + "%{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_end_preinit.o%s; \ + fvtable-verify=std:vtv_end.o%s} \ +- %{static:crtend.o%s; \ +- shared|" PIE_SPEC ":crtendS.o%s; \ +- :crtend.o%s} \ +- crtn.o%s \ ++ %{shared:crtendS.o%s;: %{" PIE_SPEC ":crtendS.o%s} \ ++ %{" NO_PIE_SPEC ":crtend.o%s}} crtn.o%s \ + " CRTOFFLOADEND + #else + #define GNU_USER_TARGET_ENDFILE_SPEC \ + "%{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_end_preinit.o%s; \ + fvtable-verify=std:vtv_end.o%s} \ +- %{static:crtend.o%s; \ +- shared|pie:crtendS.o%s; \ +- :crtend.o%s} \ +- crtn.o%s \ ++ %{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s \ + " CRTOFFLOADEND + #endif + #undef ENDFILE_SPEC +diff --git a/gcc/config/sol2.h b/gcc/config/sol2.h +index d522de03f4a..13b27873719 100644 +--- a/gcc/config/sol2.h ++++ b/gcc/config/sol2.h +@@ -174,9 +174,9 @@ along with GCC; see the file COPYING3. If not see + %{!ansi:values-Xa.o%s}" + + #if defined(HAVE_LD_PIE) && defined(HAVE_SOLARIS_CRTS) +-#define STARTFILE_CRTBEGIN_SPEC "%{static:crtbegin.o%s; \ +- shared|" PIE_SPEC ":crtbeginS.o%s; \ +- :crtbegin.o%s}" ++#define STARTFILE_CRTBEGIN_SPEC "%{shared:crtbeginS.o%s} \ ++ %{" PIE_SPEC ":crtbeginS.o%s} \ ++ %{" NO_PIE_SPEC ":crtbegin.o%s}" + #else + #define STARTFILE_CRTBEGIN_SPEC "crtbegin.o%s" + #endif +@@ -224,9 +224,9 @@ along with GCC; see the file COPYING3. If not see + #endif + + #if defined(HAVE_LD_PIE) && defined(HAVE_SOLARIS_CRTS) +-#define ENDFILE_CRTEND_SPEC "%{static:crtend.o%s; \ +- shared|" PIE_SPEC ":crtendS.o%s; \ +- :crtend.o%s}" ++#define ENDFILE_CRTEND_SPEC "%{shared:crtendS.o%s;: \ ++ %{" PIE_SPEC ":crtendS.o%s} \ ++ %{" NO_PIE_SPEC ":crtend.o%s}}" + #else + #define ENDFILE_CRTEND_SPEC "crtend.o%s" + #endif +diff --git a/gcc/gcc.c b/gcc/gcc.c +index e2fae4ef055..91eb0534722 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -873,7 +873,8 @@ proper position among the other output files. */ + #endif + + #ifdef ENABLE_DEFAULT_PIE +-#define PIE_SPEC "!no-pie" ++#define NO_PIE_SPEC "no-pie|static" ++#define PIE_SPEC NO_PIE_SPEC "|r|shared:;" + #define NO_FPIE1_SPEC "fno-pie" + #define FPIE1_SPEC NO_FPIE1_SPEC ":;" + #define NO_FPIE2_SPEC "fno-PIE" +@@ -894,6 +895,7 @@ proper position among the other output files. */ + #define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;" + #else + #define PIE_SPEC "pie" ++#define NO_PIE_SPEC PIE_SPEC "|r|shared:;" + #define FPIE1_SPEC "fpie" + #define NO_FPIE1_SPEC FPIE1_SPEC ":;" + #define FPIE2_SPEC "fPIE" +@@ -922,7 +924,7 @@ proper position among the other output files. */ + #else + #define LD_PIE_SPEC "" + #endif +-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} " ++#define LINK_PIE_SPEC "%{no-pie:} " "%{" PIE_SPEC ":" LD_PIE_SPEC "} " + #endif + + #ifndef LINK_BUILDID_SPEC +@@ -1010,10 +1012,8 @@ proper position among the other output files. */ + #endif + + /* -u* was put back because both BSD and SysV seem to support it. */ +-/* %{static|no-pie:} simply prevents an error message: +- 1. If the target machine doesn't handle -static. +- 2. If PIE isn't enabled by default. +- */ ++/* %{static:} simply prevents an error message if the target machine ++ doesn't handle -static. */ + /* We want %{T*} after %{L*} and %D so that it can be used to specify linker + scripts which exist in user specified directories, or in standard + directories. */ +@@ -1030,7 +1030,7 @@ proper position among the other output files. */ + "%{fuse-ld=*:-fuse-ld=%*} " LINK_COMPRESS_DEBUG_SPEC \ + "%X %{o*} %{e*} %{N} %{n} %{r}\ + %{s} %{t} %{u*} %{z} %{Z} %{!nostdlib:%{!nostartfiles:%S}} \ +- %{static|no-pie:} %{L*} %(mfwrap) %(link_libgcc) " \ ++ %{static:} %{L*} %(mfwrap) %(link_libgcc) " \ + VTABLE_VERIFICATION_SPEC " " SANITIZER_EARLY_SPEC " %o " CHKP_SPEC " \ + %{fopenacc|fopenmp|%:gt(%{ftree-parallelize-loops=*:%*} 1):\ + %:include(libgomp.spec)%(link_gomp)}\ diff --git a/patches/gcc-6.5.0/0019-Revert-RS6000-linux-startfile-endfile.diff b/patches/gcc-6.5.0/0019-Revert-RS6000-linux-startfile-endfile.diff new file mode 100644 index 0000000..c9c5ab0 --- /dev/null +++ b/patches/gcc-6.5.0/0019-Revert-RS6000-linux-startfile-endfile.diff @@ -0,0 +1,57 @@ +diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h +index cbee89140dd..de386291a51 100644 +--- a/gcc/config/rs6000/sysv4.h ++++ b/gcc/config/rs6000/sysv4.h +@@ -757,34 +757,24 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN) + #define CRTOFFLOADEND "" + #endif + +-/* STARTFILE_LINUX_SPEC should be the same as GNU_USER_TARGET_STARTFILE_SPEC +- but with the mnewlib ecrti.o%s selection substituted for crti.o%s. */ +-#define STARTFILE_LINUX_SPEC \ +- "%{shared:; \ +- pg|p|profile:gcrt1.o%s; \ +- static:crt1.o%s; \ +- " PIE_SPEC ":Scrt1.o%s; \ +- :crt1.o%s} \ +- %{mnewlib:ecrti.o%s;:crti.o%s} \ +- %{static:crtbeginT.o%s; \ +- shared|" PIE_SPEC ":crtbeginS.o%s; \ +- :crtbegin.o%s} \ +- %{fvtable-verify=none:%s; \ +- fvtable-verify=preinit:vtv_start_preinit.o%s; \ +- fvtable-verify=std:vtv_start.o%s} \ +- " CRTOFFLOADBEGIN +- +-/* ENDFILE_LINUX_SPEC should be the same as GNU_USER_TARGET_ENDFILE_SPEC +- but with the mnewlib ecrtn.o%s selection substituted for crtn.o%s. */ +-#define ENDFILE_LINUX_SPEC \ +- "%{fvtable-verify=none:%s; \ +- fvtable-verify=preinit:vtv_end_preinit.o%s; \ +- fvtable-verify=std:vtv_end.o%s} \ +- %{static:crtend.o%s; \ +- shared|" PIE_SPEC ":crtendS.o%s; \ +- :crtend.o%s} \ +- %{mnewlib:ecrtn.o%s;:crtn.o%s} \ +- " CRTOFFLOADEND ++#ifdef HAVE_LD_PIE ++#define STARTFILE_LINUX_SPEC "\ ++%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \ ++%{mnewlib:ecrti.o%s;:crti.o%s} \ ++%{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \ ++" CRTOFFLOADBEGIN ++#else ++#define STARTFILE_LINUX_SPEC "\ ++%{!shared: %{pg|p|profile:gcrt1.o%s;:crt1.o%s}} \ ++%{mnewlib:ecrti.o%s;:crti.o%s} \ ++%{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \ ++" CRTOFFLOADBEGIN ++#endif ++ ++#define ENDFILE_LINUX_SPEC "\ ++%{shared|pie:crtendS.o%s;:crtend.o%s} \ ++%{mnewlib:ecrtn.o%s;:crtn.o%s} \ ++" CRTOFFLOADEND + + #define LINK_START_LINUX_SPEC "" + diff --git a/patches/gcc-6.5.0/0020-static-pie-support.diff b/patches/gcc-6.5.0/0020-static-pie-support.diff new file mode 100644 index 0000000..e2a9b9c --- /dev/null +++ b/patches/gcc-6.5.0/0020-static-pie-support.diff @@ -0,0 +1,40 @@ +diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h +index b0bf40a..d4b56fe 100644 +--- a/gcc/config/gnu-user.h ++++ b/gcc/config/gnu-user.h +@@ -51,10 +51,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #if defined HAVE_LD_PIE + #define GNU_USER_TARGET_STARTFILE_SPEC \ + "%{!shared: %{pg|p|profile:gcrt1.o%s;: \ +- %{" PIE_SPEC ":Scrt1.o%s} %{" NO_PIE_SPEC ":crt1.o%s}}} \ +- crti.o%s %{static:crtbeginT.o%s;: %{shared:crtbeginS.o%s} \ ++ %{" PIE_SPEC ":%{static:rcrt1.o%s;:Scrt1.o%s}} %{" NO_PIE_SPEC ":crt1.o%s}}} \ ++ crti.o%s %{shared:crtbeginS.o%s;: \ + %{" PIE_SPEC ":crtbeginS.o%s} \ +- %{" NO_PIE_SPEC ":crtbegin.o%s}} \ ++ %{" NO_PIE_SPEC ":%{static:crtbeginT.o%s;:crtbegin.o%s}}} \ + %{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_start_preinit.o%s; \ + fvtable-verify=std:vtv_start.o%s} \ +diff --git a/gcc/gcc.c b/gcc/gcc.c +index 0576ea7..0a280e0 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -870,7 +870,7 @@ proper position among the other output files. */ + #endif + + #ifdef ENABLE_DEFAULT_PIE +-#define NO_PIE_SPEC "no-pie|static" ++#define NO_PIE_SPEC "no-pie" + #define PIE_SPEC NO_PIE_SPEC "|r|shared:;" + #define NO_FPIE1_SPEC "fno-pie" + #define FPIE1_SPEC NO_FPIE1_SPEC ":;" +@@ -916,7 +916,7 @@ proper position among the other output files. */ + #ifndef LINK_PIE_SPEC + #ifdef HAVE_LD_PIE + #ifndef LD_PIE_SPEC +-#define LD_PIE_SPEC "-pie" ++#define LD_PIE_SPEC "-pie %{static:--no-dynamic-linker -Bsymbolic}" + #endif + #else + #define LD_PIE_SPEC "" diff --git a/patches/gcc-6.5.0/0021-fix-gthr-weak-refs-for-libgcc.patch b/patches/gcc-6.5.0/0021-fix-gthr-weak-refs-for-libgcc.patch new file mode 100644 index 0000000..56291a2 --- /dev/null +++ b/patches/gcc-6.5.0/0021-fix-gthr-weak-refs-for-libgcc.patch @@ -0,0 +1,51 @@ +From 51a354a0fb54165d505bfed9819c0440027312d9 Mon Sep 17 00:00:00 2001 +From: Szabolcs Nagy +Date: Sun, 22 Sep 2019 23:04:48 +0000 +Subject: [PATCH] fix gthr weak refs for libgcc + +ideally gthr-posix.h should be fixed not to use weak refs for +single thread detection by default since that's unsafe. + +currently we have to opt out explicitly from the unsafe behaviour +in the configure machinery of each target lib that uses gthr and +musl missed libgcc previously. + +related bugs and discussions +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78017 +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87189 +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91737 +https://sourceware.org/bugzilla/show_bug.cgi?id=5784 +https://sourceware.org/ml/libc-alpha/2012-09/msg00192.html +https://sourceware.org/ml/libc-alpha/2019-08/msg00438.html +--- + libgcc/config.host | 7 +++++++ + libgcc/config/t-gthr-noweak | 2 ++ + 2 files changed, 9 insertions(+) + create mode 100644 libgcc/config/t-gthr-noweak + +diff --git a/libgcc/config.host b/libgcc/config.host +index 122113fc519..fe1b9ab93d5 100644 +--- a/libgcc/config.host ++++ b/libgcc/config.host +@@ -1500,3 +1500,10 @@ aarch64*-*-*) + tm_file="${tm_file} aarch64/value-unwind.h" + ;; + esac ++ ++case ${host} in ++*-*-musl*) ++ # The gthr weak references are unsafe with static linking ++ tmake_file="$tmake_file t-gthr-noweak" ++ ;; ++esac +diff --git a/libgcc/config/t-gthr-noweak b/libgcc/config/t-gthr-noweak +new file mode 100644 +index 00000000000..45a21e9361d +--- /dev/null ++++ b/libgcc/config/t-gthr-noweak +@@ -0,0 +1,2 @@ ++# Don't use weak references for single-thread detection ++HOST_LIBGCC2_CFLAGS += -DGTHREAD_USE_WEAK=0 +-- +2.17.1 + diff --git a/patches/gcc-6.5.0/0022-libstdc++-futex-time64.diff b/patches/gcc-6.5.0/0022-libstdc++-futex-time64.diff new file mode 100644 index 0000000..08f6261 --- /dev/null +++ b/patches/gcc-6.5.0/0022-libstdc++-futex-time64.diff @@ -0,0 +1,18 @@ +--- gcc-9.2.0/libstdc++-v3/src/c++11/futex.cc.orig 2020-01-20 14:55:05.507548334 -0500 ++++ gcc-9.2.0/libstdc++-v3/src/c++11/futex.cc 2020-01-20 14:56:52.458268068 -0500 +@@ -61,7 +61,15 @@ + struct timeval tv; + gettimeofday (&tv, NULL); + // Convert the absolute timeout value to a relative timeout ++#if defined(SYS_futex_time64) && SYS_futex_time64 != SYS_futex ++ struct ++ { ++ long tv_sec; ++ long tv_nsec; ++ } rt; ++#else + struct timespec rt; ++#endif + rt.tv_sec = __s.count() - tv.tv_sec; + rt.tv_nsec = __ns.count() - tv.tv_usec * 1000; + if (rt.tv_nsec < 0) diff --git a/patches/gcc-6.5.0/0023-pr93402.diff b/patches/gcc-6.5.0/0023-pr93402.diff new file mode 100644 index 0000000..c985fb6 --- /dev/null +++ b/patches/gcc-6.5.0/0023-pr93402.diff @@ -0,0 +1,45 @@ +2020-01-23 Jakub Jelinek + + PR rtl-optimization/93402 + * postreload.c (reload_combine_recognize_pattern): Don't try to adjust + USE insns. + + * gcc.c-torture/execute/pr93402.c: New test. + +--- a/gcc/postreload.c.jj 2020-01-12 11:54:36.000000000 +0100 ++++ b/gcc/postreload.c 2020-01-23 17:23:25.359929516 +0100 +@@ -1078,6 +1078,10 @@ reload_combine_recognize_pattern (rtx_in + struct reg_use *use = reg_state[regno].reg_use + i; + if (GET_MODE (*use->usep) != mode) + return false; ++ /* Don't try to adjust (use (REGX)). */ ++ if (GET_CODE (PATTERN (use->insn)) == USE ++ && &XEXP (PATTERN (use->insn), 0) == use->usep) ++ return false; + } + + /* Look for (set (REGX) (CONST_INT)) +--- a/gcc/testsuite/gcc.c-torture/execute/pr93402.c.jj 2020-01-23 17:25:46.496803852 +0100 ++++ b/gcc/testsuite/gcc.c-torture/execute/pr93402.c 2020-01-23 17:25:05.221425501 +0100 +@@ -0,0 +1,21 @@ ++/* PR rtl-optimization/93402 */ ++ ++struct S { unsigned int a; unsigned long long b; }; ++ ++__attribute__((noipa)) struct S ++foo (unsigned long long x) ++{ ++ struct S ret; ++ ret.a = 0; ++ ret.b = x * 11111111111ULL + 111111111111ULL; ++ return ret; ++} ++ ++int ++main () ++{ ++ struct S a = foo (1); ++ if (a.a != 0 || a.b != 122222222222ULL) ++ __builtin_abort (); ++ return 0; ++} diff --git a/patches/gcc-6.5.0/0024-m68k-sqrt.diff b/patches/gcc-6.5.0/0024-m68k-sqrt.diff new file mode 100644 index 0000000..5d46272 --- /dev/null +++ b/patches/gcc-6.5.0/0024-m68k-sqrt.diff @@ -0,0 +1,18 @@ +--- gcc-9.2.0.orig/gcc/config/m68k/m68k.md 2019-01-01 07:31:55.000000000 -0500 ++++ gcc-9.2.0/gcc/config/m68k/m68k.md 2020-07-01 15:57:20.528408009 -0400 +@@ -4126,13 +4126,13 @@ + (define_expand "sqrt2" + [(set (match_operand:FP 0 "nonimmediate_operand" "") + (sqrt:FP (match_operand:FP 1 "general_operand" "")))] +- "TARGET_HARD_FLOAT" ++ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU" + "") + + (define_insn "sqrt2_68881" + [(set (match_operand:FP 0 "nonimmediate_operand" "=f") + (sqrt:FP (match_operand:FP 1 "general_operand" "fm")))] +- "TARGET_68881" ++ "TARGET_68881 && TARGET_68040" + { + if (FP_REG_P (operands[1])) + return "fsqrt%.x %1,%0"; diff --git a/patches/gcc-6.5.0/0025-powerpcspe-musl-ldsoname.diff b/patches/gcc-6.5.0/0025-powerpcspe-musl-ldsoname.diff new file mode 100644 index 0000000..f88fd85 --- /dev/null +++ b/patches/gcc-6.5.0/0025-powerpcspe-musl-ldsoname.diff @@ -0,0 +1,22 @@ +--- gcc-8.5.0/gcc/config/rs6000/sysv4.h.orig 2021-07-05 12:56:18.398813835 -0400 ++++ gcc-8.5.0/gcc/config/rs6000/sysv4.h 2021-06-23 21:49:57.592408186 -0400 +@@ -793,7 +793,7 @@ + #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" + #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0" + #define MUSL_DYNAMIC_LINKER \ +- "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" ++ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float|mcpu=854*|mspe:-sf}.so.1" + #if DEFAULT_LIBC == LIBC_UCLIBC + #define CHOOSE_DYNAMIC_LINKER(G, U, M) \ + "%{mglibc:" G ";:%{mmusl:" M ";:" U "}}" +--- gcc-8.5.0/gcc/config/rs6000/linux64.h.orig 2021-07-05 12:54:24.704854044 -0400 ++++ gcc-8.5.0/gcc/config/rs6000/linux64.h 2021-07-05 12:56:50.010806923 -0400 +@@ -426,7 +426,7 @@ + #endif + + #define MUSL_DYNAMIC_LINKER32 \ +- "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" ++ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float|mcpu=854*|mspe:-sf}.so.1" + #define MUSL_DYNAMIC_LINKER64 \ + "/lib/ld-musl-powerpc64" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" + diff --git a/patches/gcc-7.5.0/0001-ssp_nonshared.diff b/patches/gcc-7.5.0/0001-ssp_nonshared.diff new file mode 100644 index 0000000..c8d0e48 --- /dev/null +++ b/patches/gcc-7.5.0/0001-ssp_nonshared.diff @@ -0,0 +1,14 @@ +diff --git a/gcc/gcc.c b/gcc/gcc.c +index c48178f1aa3..e2fae4ef055 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -863,7 +863,8 @@ proper position among the other output files. */ + #ifndef LINK_SSP_SPEC + #ifdef TARGET_LIBC_PROVIDES_SSP + #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ +- "|fstack-protector-strong|fstack-protector-explicit:}" ++ "|fstack-protector-strong|fstack-protector-explicit" \ ++ ":-lssp_nonshared}" + #else + #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ + "|fstack-protector-strong|fstack-protector-explicit" \ diff --git a/patches/gcc-7.5.0/0002-posix_memalign.diff b/patches/gcc-7.5.0/0002-posix_memalign.diff new file mode 100644 index 0000000..30bc7b2 --- /dev/null +++ b/patches/gcc-7.5.0/0002-posix_memalign.diff @@ -0,0 +1,30 @@ +diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h +index 73d9e887b4b..33f998702fa 100644 +--- a/gcc/config/i386/pmm_malloc.h ++++ b/gcc/config/i386/pmm_malloc.h +@@ -27,12 +27,13 @@ + #include + + /* We can't depend on since the prototype of posix_memalign +- may not be visible. */ ++ may not be visible and we can't pollute the namespace either. */ + #ifndef __cplusplus +-extern int posix_memalign (void **, size_t, size_t); ++extern int _mm_posix_memalign (void **, size_t, size_t) + #else +-extern "C" int posix_memalign (void **, size_t, size_t) throw (); ++extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw () + #endif ++__asm__("posix_memalign"); + + static __inline void * + _mm_malloc (size_t __size, size_t __alignment) +@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment) + return malloc (__size); + if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4)) + __alignment = sizeof (void *); +- if (posix_memalign (&__ptr, __alignment, __size) == 0) ++ if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0) + return __ptr; + else + return NULL; diff --git a/patches/gcc-7.5.0/0003-cilkrts.diff b/patches/gcc-7.5.0/0003-cilkrts.diff new file mode 100644 index 0000000..ef2f155 --- /dev/null +++ b/patches/gcc-7.5.0/0003-cilkrts.diff @@ -0,0 +1,46 @@ +diff --git a/libcilkrts/runtime/os-unix.c b/libcilkrts/runtime/os-unix.c +index c419fb68abf..155d8669e91 100644 +--- a/libcilkrts/runtime/os-unix.c ++++ b/libcilkrts/runtime/os-unix.c +@@ -55,6 +55,7 @@ + #if defined __linux__ + # include + # include ++# include + + #elif defined __APPLE__ + # include +@@ -452,28 +453,19 @@ COMMON_SYSDEP void __cilkrts_sleep(void) + + COMMON_SYSDEP void __cilkrts_yield(void) + { +-#if defined(__ANDROID__) || \ +- defined(__APPLE__) || \ +- defined(__CYGWIN__) || \ +- defined(__FreeBSD__) || \ +- defined(__VXWORKS__) || \ +- (defined(__sun__) && defined(__svr4__)) +- // Call sched_yield to yield quantum. I'm not sure why we +- // don't do this on Linux also. +- sched_yield(); +-#elif defined(__MIC__) ++#if defined(__MIC__) + // On MIC, pthread_yield() really trashes things. Arch's measurements + // showed that calling _mm_delay_32() (or doing nothing) was a better + // option. Delaying 1024 clock cycles is a reasonable compromise between + // giving up the processor and latency starting up when work becomes + // available + _mm_delay_32(1024); +-#elif defined(__linux__) +- // On Linux, call pthread_yield (which in turn will call sched_yield) +- // to yield quantum. ++#elif defined(__sun__) && !defined(__svr4__) ++ // On old SunOS call pthread_yield to yield a quantum. + pthread_yield(); + #else +-# error "Unsupported architecture" ++ // On other platforms call sched_yield to yield a quantum. ++ sched_yield(); + #endif + } + diff --git a/patches/gcc-7.5.0/0004-libatomic-test-fix.diff b/patches/gcc-7.5.0/0004-libatomic-test-fix.diff new file mode 100644 index 0000000..97dd3c2 --- /dev/null +++ b/patches/gcc-7.5.0/0004-libatomic-test-fix.diff @@ -0,0 +1,58 @@ +diff --git a/libatomic/testsuite/Makefile.am b/libatomic/testsuite/Makefile.am +index a9a0144185a..a19101aac54 100644 +--- a/libatomic/testsuite/Makefile.am ++++ b/libatomic/testsuite/Makefile.am +@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \ + _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++ ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ +diff --git a/libatomic/testsuite/Makefile.in b/libatomic/testsuite/Makefile.in +index adfc231484a..5400ac3ce11 100644 +--- a/libatomic/testsuite/Makefile.in ++++ b/libatomic/testsuite/Makefile.in +@@ -223,6 +223,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -429,6 +430,10 @@ uninstall-am: + uninstall uninstall-am + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Tell versions [3.59,3.63) of GNU make to not export all variables. + # Otherwise a system limit (for SysV at least) may be exceeded. + .NOEXPORT: +diff --git a/libatomic/testsuite/lib/libatomic.exp b/libatomic/testsuite/lib/libatomic.exp +index cafab5432b7..dd2e1a4de49 100644 +--- a/libatomic/testsuite/lib/libatomic.exp ++++ b/libatomic/testsuite/lib/libatomic.exp +@@ -74,6 +74,7 @@ proc libatomic_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -89,6 +90,8 @@ proc libatomic_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-7.5.0/0005-libgomp-test-fix.diff b/patches/gcc-7.5.0/0005-libgomp-test-fix.diff new file mode 100644 index 0000000..fe99793 --- /dev/null +++ b/patches/gcc-7.5.0/0005-libgomp-test-fix.diff @@ -0,0 +1,60 @@ +diff --git a/libgomp/testsuite/Makefile.am b/libgomp/testsuite/Makefile.am +index e2a3f460eb0..3309f71e02e 100644 +--- a/libgomp/testsuite/Makefile.am ++++ b/libgomp/testsuite/Makefile.am +@@ -12,6 +12,11 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" + ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ + + # Instead of directly in ../testsuite/libgomp-test-support.exp.in, the + # following variables have to be "routed through" this Makefile, for expansion +diff --git a/libgomp/testsuite/Makefile.in b/libgomp/testsuite/Makefile.in +index 6edb7ae7ade..b3eddbc3e62 100644 +--- a/libgomp/testsuite/Makefile.in ++++ b/libgomp/testsuite/Makefile.in +@@ -254,6 +254,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -462,6 +463,10 @@ uninstall-am: + ps ps-am uninstall uninstall-am + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Instead of directly in ../testsuite/libgomp-test-support.exp.in, the + # following variables have to be "routed through" this Makefile, for expansion + # of the several (Makefile) variables used therein. +diff --git a/libgomp/testsuite/lib/libgomp.exp b/libgomp/testsuite/lib/libgomp.exp +index 5e47872c5c4..b277c93047d 100644 +--- a/libgomp/testsuite/lib/libgomp.exp ++++ b/libgomp/testsuite/lib/libgomp.exp +@@ -85,6 +85,7 @@ proc libgomp_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -107,6 +108,8 @@ proc libgomp_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-7.5.0/0006-libitm-test-fix.diff b/patches/gcc-7.5.0/0006-libitm-test-fix.diff new file mode 100644 index 0000000..5cc1f96 --- /dev/null +++ b/patches/gcc-7.5.0/0006-libitm-test-fix.diff @@ -0,0 +1,58 @@ +diff --git a/libitm/testsuite/Makefile.am b/libitm/testsuite/Makefile.am +index a9a0144185a..a19101aac54 100644 +--- a/libitm/testsuite/Makefile.am ++++ b/libitm/testsuite/Makefile.am +@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \ + _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++ ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ +diff --git a/libitm/testsuite/Makefile.in b/libitm/testsuite/Makefile.in +index eb9e992279d..1250e7f9a5a 100644 +--- a/libitm/testsuite/Makefile.in ++++ b/libitm/testsuite/Makefile.in +@@ -234,6 +234,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -440,6 +441,10 @@ uninstall-am: + uninstall uninstall-am + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Tell versions [3.59,3.63) of GNU make to not export all variables. + # Otherwise a system limit (for SysV at least) may be exceeded. + .NOEXPORT: +diff --git a/libitm/testsuite/lib/libitm.exp b/libitm/testsuite/lib/libitm.exp +index 041629687f6..748f492c03d 100644 +--- a/libitm/testsuite/lib/libitm.exp ++++ b/libitm/testsuite/lib/libitm.exp +@@ -74,6 +74,7 @@ proc libitm_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -89,6 +90,8 @@ proc libitm_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-7.5.0/0007-libvtv-test-fix.diff b/patches/gcc-7.5.0/0007-libvtv-test-fix.diff new file mode 100644 index 0000000..294ae45 --- /dev/null +++ b/patches/gcc-7.5.0/0007-libvtv-test-fix.diff @@ -0,0 +1,58 @@ +diff --git a/libvtv/testsuite/Makefile.am b/libvtv/testsuite/Makefile.am +index a9a0144185a..a19101aac54 100644 +--- a/libvtv/testsuite/Makefile.am ++++ b/libvtv/testsuite/Makefile.am +@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \ + _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++ ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ +diff --git a/libvtv/testsuite/Makefile.in b/libvtv/testsuite/Makefile.in +index b5dfd29973c..9f672e9ae98 100644 +--- a/libvtv/testsuite/Makefile.in ++++ b/libvtv/testsuite/Makefile.in +@@ -228,6 +228,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -434,6 +435,10 @@ uninstall-am: + uninstall uninstall-am + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Tell versions [3.59,3.63) of GNU make to not export all variables. + # Otherwise a system limit (for SysV at least) may be exceeded. + .NOEXPORT: +diff --git a/libvtv/testsuite/lib/libvtv.exp b/libvtv/testsuite/lib/libvtv.exp +index edf5fddbad2..a596091573b 100644 +--- a/libvtv/testsuite/lib/libvtv.exp ++++ b/libvtv/testsuite/lib/libvtv.exp +@@ -74,6 +74,7 @@ proc libvtv_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -89,6 +90,8 @@ proc libvtv_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-7.5.0/0008-Revert-PR-driver-81523-Make-static-override-pie.diff b/patches/gcc-7.5.0/0008-Revert-PR-driver-81523-Make-static-override-pie.diff new file mode 100644 index 0000000..baceb01 --- /dev/null +++ b/patches/gcc-7.5.0/0008-Revert-PR-driver-81523-Make-static-override-pie.diff @@ -0,0 +1,147 @@ +diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h +index de605b0c466..2787a3d16be 100644 +--- a/gcc/config/gnu-user.h ++++ b/gcc/config/gnu-user.h +@@ -50,28 +50,19 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + + #if defined HAVE_LD_PIE + #define GNU_USER_TARGET_STARTFILE_SPEC \ +- "%{shared:; \ +- pg|p|profile:gcrt1.o%s; \ +- static:crt1.o%s; \ +- " PIE_SPEC ":Scrt1.o%s; \ +- :crt1.o%s} \ +- crti.o%s \ +- %{static:crtbeginT.o%s; \ +- shared|" PIE_SPEC ":crtbeginS.o%s; \ +- :crtbegin.o%s} \ ++ "%{!shared: %{pg|p|profile:gcrt1.o%s;: \ ++ %{" PIE_SPEC ":Scrt1.o%s} %{" NO_PIE_SPEC ":crt1.o%s}}} \ ++ crti.o%s %{static:crtbeginT.o%s;: %{shared:crtbeginS.o%s} \ ++ %{" PIE_SPEC ":crtbeginS.o%s} \ ++ %{" NO_PIE_SPEC ":crtbegin.o%s}} \ + %{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_start_preinit.o%s; \ + fvtable-verify=std:vtv_start.o%s} \ + " CRTOFFLOADBEGIN + #else + #define GNU_USER_TARGET_STARTFILE_SPEC \ +- "%{shared:; \ +- pg|p|profile:gcrt1.o%s; \ +- :crt1.o%s} \ +- crti.o%s \ +- %{static:crtbeginT.o%s; \ +- shared|pie:crtbeginS.o%s; \ +- :crtbegin.o%s} \ ++ "%{!shared: %{pg|p|profile:gcrt1.o%s;:crt1.o%s}} \ ++ crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \ + %{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_start_preinit.o%s; \ + fvtable-verify=std:vtv_start.o%s} \ +@@ -91,20 +82,15 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + "%{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_end_preinit.o%s; \ + fvtable-verify=std:vtv_end.o%s} \ +- %{static:crtend.o%s; \ +- shared|" PIE_SPEC ":crtendS.o%s; \ +- :crtend.o%s} \ +- crtn.o%s \ ++ %{shared:crtendS.o%s;: %{" PIE_SPEC ":crtendS.o%s} \ ++ %{" NO_PIE_SPEC ":crtend.o%s}} crtn.o%s \ + " CRTOFFLOADEND + #else + #define GNU_USER_TARGET_ENDFILE_SPEC \ + "%{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_end_preinit.o%s; \ + fvtable-verify=std:vtv_end.o%s} \ +- %{static:crtend.o%s; \ +- shared|pie:crtendS.o%s; \ +- :crtend.o%s} \ +- crtn.o%s \ ++ %{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s \ + " CRTOFFLOADEND + #endif + #undef ENDFILE_SPEC +diff --git a/gcc/config/sol2.h b/gcc/config/sol2.h +index d522de03f4a..13b27873719 100644 +--- a/gcc/config/sol2.h ++++ b/gcc/config/sol2.h +@@ -174,9 +174,9 @@ along with GCC; see the file COPYING3. If not see + %{!ansi:values-Xa.o%s}" + + #if defined(HAVE_LD_PIE) && defined(HAVE_SOLARIS_CRTS) +-#define STARTFILE_CRTBEGIN_SPEC "%{static:crtbegin.o%s; \ +- shared|" PIE_SPEC ":crtbeginS.o%s; \ +- :crtbegin.o%s}" ++#define STARTFILE_CRTBEGIN_SPEC "%{shared:crtbeginS.o%s} \ ++ %{" PIE_SPEC ":crtbeginS.o%s} \ ++ %{" NO_PIE_SPEC ":crtbegin.o%s}" + #else + #define STARTFILE_CRTBEGIN_SPEC "crtbegin.o%s" + #endif +@@ -224,9 +224,9 @@ along with GCC; see the file COPYING3. If not see + #endif + + #if defined(HAVE_LD_PIE) && defined(HAVE_SOLARIS_CRTS) +-#define ENDFILE_CRTEND_SPEC "%{static:crtend.o%s; \ +- shared|" PIE_SPEC ":crtendS.o%s; \ +- :crtend.o%s}" ++#define ENDFILE_CRTEND_SPEC "%{shared:crtendS.o%s;: \ ++ %{" PIE_SPEC ":crtendS.o%s} \ ++ %{" NO_PIE_SPEC ":crtend.o%s}}" + #else + #define ENDFILE_CRTEND_SPEC "crtend.o%s" + #endif +diff --git a/gcc/gcc.c b/gcc/gcc.c +index e2fae4ef055..91eb0534722 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -873,7 +873,8 @@ proper position among the other output files. */ + #endif + + #ifdef ENABLE_DEFAULT_PIE +-#define PIE_SPEC "!no-pie" ++#define NO_PIE_SPEC "no-pie|static" ++#define PIE_SPEC NO_PIE_SPEC "|r|shared:;" + #define NO_FPIE1_SPEC "fno-pie" + #define FPIE1_SPEC NO_FPIE1_SPEC ":;" + #define NO_FPIE2_SPEC "fno-PIE" +@@ -894,6 +895,7 @@ proper position among the other output files. */ + #define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;" + #else + #define PIE_SPEC "pie" ++#define NO_PIE_SPEC PIE_SPEC "|r|shared:;" + #define FPIE1_SPEC "fpie" + #define NO_FPIE1_SPEC FPIE1_SPEC ":;" + #define FPIE2_SPEC "fPIE" +@@ -922,7 +924,7 @@ proper position among the other output files. */ + #else + #define LD_PIE_SPEC "" + #endif +-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} " ++#define LINK_PIE_SPEC "%{no-pie:} " "%{" PIE_SPEC ":" LD_PIE_SPEC "} " + #endif + + #ifndef LINK_BUILDID_SPEC +@@ -1010,10 +1012,8 @@ proper position among the other output files. */ + #endif + + /* -u* was put back because both BSD and SysV seem to support it. */ +-/* %{static|no-pie:} simply prevents an error message: +- 1. If the target machine doesn't handle -static. +- 2. If PIE isn't enabled by default. +- */ ++/* %{static:} simply prevents an error message if the target machine ++ doesn't handle -static. */ + /* We want %{T*} after %{L*} and %D so that it can be used to specify linker + scripts which exist in user specified directories, or in standard + directories. */ +@@ -1030,7 +1030,7 @@ proper position among the other output files. */ + "%{fuse-ld=*:-fuse-ld=%*} " LINK_COMPRESS_DEBUG_SPEC \ + "%X %{o*} %{e*} %{N} %{n} %{r}\ + %{s} %{t} %{u*} %{z} %{Z} %{!nostdlib:%{!nostartfiles:%S}} \ +- %{static|no-pie:} %{L*} %(mfwrap) %(link_libgcc) " \ ++ %{static:} %{L*} %(mfwrap) %(link_libgcc) " \ + VTABLE_VERIFICATION_SPEC " " SANITIZER_EARLY_SPEC " %o " CHKP_SPEC " \ + %{fopenacc|fopenmp|%:gt(%{ftree-parallelize-loops=*:%*} 1):\ + %:include(libgomp.spec)%(link_gomp)}\ diff --git a/patches/gcc-7.5.0/0009-Revert-RS6000-linux-startfile-endfile.diff b/patches/gcc-7.5.0/0009-Revert-RS6000-linux-startfile-endfile.diff new file mode 100644 index 0000000..c9c5ab0 --- /dev/null +++ b/patches/gcc-7.5.0/0009-Revert-RS6000-linux-startfile-endfile.diff @@ -0,0 +1,57 @@ +diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h +index cbee89140dd..de386291a51 100644 +--- a/gcc/config/rs6000/sysv4.h ++++ b/gcc/config/rs6000/sysv4.h +@@ -757,34 +757,24 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN) + #define CRTOFFLOADEND "" + #endif + +-/* STARTFILE_LINUX_SPEC should be the same as GNU_USER_TARGET_STARTFILE_SPEC +- but with the mnewlib ecrti.o%s selection substituted for crti.o%s. */ +-#define STARTFILE_LINUX_SPEC \ +- "%{shared:; \ +- pg|p|profile:gcrt1.o%s; \ +- static:crt1.o%s; \ +- " PIE_SPEC ":Scrt1.o%s; \ +- :crt1.o%s} \ +- %{mnewlib:ecrti.o%s;:crti.o%s} \ +- %{static:crtbeginT.o%s; \ +- shared|" PIE_SPEC ":crtbeginS.o%s; \ +- :crtbegin.o%s} \ +- %{fvtable-verify=none:%s; \ +- fvtable-verify=preinit:vtv_start_preinit.o%s; \ +- fvtable-verify=std:vtv_start.o%s} \ +- " CRTOFFLOADBEGIN +- +-/* ENDFILE_LINUX_SPEC should be the same as GNU_USER_TARGET_ENDFILE_SPEC +- but with the mnewlib ecrtn.o%s selection substituted for crtn.o%s. */ +-#define ENDFILE_LINUX_SPEC \ +- "%{fvtable-verify=none:%s; \ +- fvtable-verify=preinit:vtv_end_preinit.o%s; \ +- fvtable-verify=std:vtv_end.o%s} \ +- %{static:crtend.o%s; \ +- shared|" PIE_SPEC ":crtendS.o%s; \ +- :crtend.o%s} \ +- %{mnewlib:ecrtn.o%s;:crtn.o%s} \ +- " CRTOFFLOADEND ++#ifdef HAVE_LD_PIE ++#define STARTFILE_LINUX_SPEC "\ ++%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \ ++%{mnewlib:ecrti.o%s;:crti.o%s} \ ++%{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \ ++" CRTOFFLOADBEGIN ++#else ++#define STARTFILE_LINUX_SPEC "\ ++%{!shared: %{pg|p|profile:gcrt1.o%s;:crt1.o%s}} \ ++%{mnewlib:ecrti.o%s;:crti.o%s} \ ++%{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \ ++" CRTOFFLOADBEGIN ++#endif ++ ++#define ENDFILE_LINUX_SPEC "\ ++%{shared|pie:crtendS.o%s;:crtend.o%s} \ ++%{mnewlib:ecrtn.o%s;:crtn.o%s} \ ++" CRTOFFLOADEND + + #define LINK_START_LINUX_SPEC "" + diff --git a/patches/gcc-7.5.0/0010-static-pie-support.diff b/patches/gcc-7.5.0/0010-static-pie-support.diff new file mode 100644 index 0000000..02ae751 --- /dev/null +++ b/patches/gcc-7.5.0/0010-static-pie-support.diff @@ -0,0 +1,59 @@ +diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h +index 2787a3d16be..ee7b781319e 100644 +--- a/gcc/config/gnu-user.h ++++ b/gcc/config/gnu-user.h +@@ -51,10 +51,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #if defined HAVE_LD_PIE + #define GNU_USER_TARGET_STARTFILE_SPEC \ + "%{!shared: %{pg|p|profile:gcrt1.o%s;: \ +- %{" PIE_SPEC ":Scrt1.o%s} %{" NO_PIE_SPEC ":crt1.o%s}}} \ +- crti.o%s %{static:crtbeginT.o%s;: %{shared:crtbeginS.o%s} \ ++ %{" PIE_SPEC ":%{static:rcrt1.o%s;:Scrt1.o%s}} %{" NO_PIE_SPEC ":crt1.o%s}}} \ ++ crti.o%s %{shared:crtbeginS.o%s;: \ + %{" PIE_SPEC ":crtbeginS.o%s} \ +- %{" NO_PIE_SPEC ":crtbegin.o%s}} \ ++ %{" NO_PIE_SPEC ":%{static:crtbeginT.o%s;:crtbegin.o%s}}} \ + %{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_start_preinit.o%s; \ + fvtable-verify=std:vtv_start.o%s} \ +diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h +index de386291a51..577fddc8a7c 100644 +--- a/gcc/config/rs6000/sysv4.h ++++ b/gcc/config/rs6000/sysv4.h +@@ -759,9 +759,12 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN) + + #ifdef HAVE_LD_PIE + #define STARTFILE_LINUX_SPEC "\ +-%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \ ++%{!shared: %{pg|p|profile:gcrt1.o%s;: \ ++ %{" PIE_SPEC ":%{static:rcrt1.o%s;:Scrt1.o%s}} %{" NO_PIE_SPEC ":crt1.o%s}}} \ + %{mnewlib:ecrti.o%s;:crti.o%s} \ +-%{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \ ++%{shared:crtbeginS.o%s;: \ ++ %{" PIE_SPEC ":crtbeginS.o%s} \ ++ %{" NO_PIE_SPEC ":%{static:crtbeginT.o%s;:crtbegin.o%s}}} \ + " CRTOFFLOADBEGIN + #else + #define STARTFILE_LINUX_SPEC "\ +diff --git a/gcc/gcc.c b/gcc/gcc.c +index 91eb0534722..74a390e6005 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -873,7 +873,7 @@ proper position among the other output files. */ + #endif + + #ifdef ENABLE_DEFAULT_PIE +-#define NO_PIE_SPEC "no-pie|static" ++#define NO_PIE_SPEC "no-pie" + #define PIE_SPEC NO_PIE_SPEC "|r|shared:;" + #define NO_FPIE1_SPEC "fno-pie" + #define FPIE1_SPEC NO_FPIE1_SPEC ":;" +@@ -919,7 +919,7 @@ proper position among the other output files. */ + #ifndef LINK_PIE_SPEC + #ifdef HAVE_LD_PIE + #ifndef LD_PIE_SPEC +-#define LD_PIE_SPEC "-pie" ++#define LD_PIE_SPEC "-pie %{static:--no-dynamic-linker -Bsymbolic}" + #endif + #else + #define LD_PIE_SPEC "" diff --git a/patches/gcc-7.5.0/0011-j2.diff b/patches/gcc-7.5.0/0011-j2.diff new file mode 100644 index 0000000..61b81a9 --- /dev/null +++ b/patches/gcc-7.5.0/0011-j2.diff @@ -0,0 +1,346 @@ +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 6e75bd45fb9..8ab5f15ea8e 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -474,7 +474,7 @@ s390*-*-*) + extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h" + ;; + # Note the 'l'; we need to be able to match e.g. "shle" or "shl". +-sh[123456789lbe]*-*-* | sh-*-*) ++sh[123456789lbej]*-*-* | sh-*-*) + cpu_type=sh + extra_options="${extra_options} fused-madd.opt" + extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o" +@@ -2664,18 +2664,18 @@ s390x-ibm-tpf*) + extra_options="${extra_options} s390/tpf.opt" + tmake_file="${tmake_file} s390/t-s390" + ;; +-sh-*-elf* | sh[12346l]*-*-elf* | \ +- sh-*-linux* | sh[2346lbe]*-*-linux* | \ ++sh-*-elf* | sh[12346lj]*-*-elf* | \ ++ sh-*-linux* | sh[2346lbej]*-*-linux* | \ + sh-*-netbsdelf* | shl*-*-netbsdelf*) + tmake_file="${tmake_file} sh/t-sh sh/t-elf" + if test x${with_endian} = x; then + case ${target} in +- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;; ++ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;; + shbe-*-* | sheb-*-*) with_endian=big,little ;; + sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;; + shl* | sh*-*-linux* | \ + sh-superh-elf) with_endian=little,big ;; +- sh[1234]*-*-*) with_endian=big ;; ++ sh[j1234]*-*-*) with_endian=big ;; + *) with_endian=big,little ;; + esac + fi +@@ -2742,6 +2742,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;; + sh2a*) sh_cpu_target=sh2a ;; + sh2e*) sh_cpu_target=sh2e ;; ++ shj2*) sh_cpu_target=shj2;; + sh2*) sh_cpu_target=sh2 ;; + *) sh_cpu_target=sh1 ;; + esac +@@ -2763,7 +2764,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \ + sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \ + sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \ +- sh3e | sh3 | sh2e | sh2 | sh1) ;; ++ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;; + "") sh_cpu_default=${sh_cpu_target} ;; + *) echo "with_cpu=$with_cpu not supported"; exit 1 ;; + esac +@@ -2772,9 +2773,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + case ${target} in + sh[1234]*) sh_multilibs=${sh_cpu_target} ;; + sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;; +- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;; ++ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;; + sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;; +- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;; ++ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;; + esac + if test x$with_fp = xno; then + sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`" +@@ -2789,7 +2790,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + m1 | m2 | m2e | m3 | m3e | \ + m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\ + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \ +- m2a | m2a-single | m2a-single-only | m2a-nofpu) ++ m2a | m2a-single | m2a-single-only | m2a-nofpu | \ ++ mj2) + # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition + # It is passed to MULTIILIB_OPTIONS verbatim. + TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}" +@@ -2806,7 +2808,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + done + TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'` + if test x${enable_incomplete_targets} = xyes ; then +- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1" ++ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1" + fi + tm_file="$tm_file ./sysroot-suffix.h" + tmake_file="$tmake_file t-sysroot-suffix" +@@ -4380,6 +4382,8 @@ case "${target}" in + ;; + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al) + ;; ++ mj2) ++ ;; + *) + echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2 + echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2 +@@ -4589,7 +4593,7 @@ case ${target} in + tmake_file="rs6000/t-rs6000 ${tmake_file}" + ;; + +- sh[123456ble]*-*-* | sh-*-*) ++ sh[123456blej]*-*-* | sh-*-*) + c_target_objs="${c_target_objs} sh-c.o" + cxx_target_objs="${cxx_target_objs} sh-c.o" + ;; +diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c +index ff79b93adc2..5fe3f3bfe69 100644 +--- a/gcc/config/sh/sh.c ++++ b/gcc/config/sh/sh.c +@@ -662,6 +662,7 @@ parse_validate_atomic_model_option (const char* str) + model_names[sh_atomic_model::hard_llcs] = "hard-llcs"; + model_names[sh_atomic_model::soft_tcb] = "soft-tcb"; + model_names[sh_atomic_model::soft_imask] = "soft-imask"; ++ model_names[sh_atomic_model::hard_cas] = "hard-cas"; + + const char* model_cdef_names[sh_atomic_model::num_models]; + model_cdef_names[sh_atomic_model::none] = "NONE"; +@@ -669,6 +670,7 @@ parse_validate_atomic_model_option (const char* str) + model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS"; + model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB"; + model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK"; ++ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS"; + + sh_atomic_model ret; + ret.type = sh_atomic_model::none; +@@ -747,6 +749,9 @@ got_mode_name:; + if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE) + err_ret ("cannot use atomic model %s in user mode", ret.name); + ++ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2) ++ err_ret ("atomic model %s is only available J2 targets", ret.name); ++ + return ret; + + #undef err_ret +@@ -803,6 +808,8 @@ sh_option_override (void) + sh_cpu = PROCESSOR_SH2E; + if (TARGET_SH2A) + sh_cpu = PROCESSOR_SH2A; ++ if (TARGET_SHJ2) ++ sh_cpu = PROCESSOR_SHJ2; + if (TARGET_SH3) + sh_cpu = PROCESSOR_SH3; + if (TARGET_SH3E) +diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h +index b13d1b3c943..9e24649d189 100644 +--- a/gcc/config/sh/sh.h ++++ b/gcc/config/sh/sh.h +@@ -83,6 +83,7 @@ extern int code_for_indirect_jump_scratch; + #define SUPPORT_SH4_SINGLE 1 + #define SUPPORT_SH2A 1 + #define SUPPORT_SH2A_SINGLE 1 ++#define SUPPORT_SHJ2 1 + #endif + + #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) +@@ -115,6 +116,7 @@ extern int code_for_indirect_jump_scratch; + #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) + #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) + #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) ++#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2) + + #if SUPPORT_SH1 + #define SUPPORT_SH2 1 +@@ -122,6 +124,7 @@ extern int code_for_indirect_jump_scratch; + #if SUPPORT_SH2 + #define SUPPORT_SH3 1 + #define SUPPORT_SH2A_NOFPU 1 ++#define SUPPORT_SHJ2 1 + #endif + #if SUPPORT_SH3 + #define SUPPORT_SH4_NOFPU 1 +@@ -154,7 +157,7 @@ extern int code_for_indirect_jump_scratch; + #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ + | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ + | MASK_HARD_SH4 | MASK_FPU_SINGLE \ +- | MASK_FPU_SINGLE_ONLY) ++ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2) + + /* This defaults us to big-endian. */ + #ifndef TARGET_ENDIAN_DEFAULT +@@ -229,7 +232,8 @@ extern int code_for_indirect_jump_scratch; + %{m2a-single:--isa=sh2a} \ + %{m2a-single-only:--isa=sh2a} \ + %{m2a-nofpu:--isa=sh2a-nofpu} \ +-%{m4al:-dsp}" ++%{m4al:-dsp} \ ++%{mj2:-isa=j2}" + + #define ASM_SPEC SH_ASM_SPEC + +@@ -345,6 +349,7 @@ struct sh_atomic_model + hard_llcs, + soft_tcb, + soft_imask, ++ hard_cas, + + num_models + }; +@@ -388,6 +393,9 @@ extern const sh_atomic_model& selected_atomic_model (void); + #define TARGET_ATOMIC_SOFT_IMASK \ + (selected_atomic_model ().type == sh_atomic_model::soft_imask) + ++#define TARGET_ATOMIC_HARD_CAS \ ++ (selected_atomic_model ().type == sh_atomic_model::hard_cas) ++ + #endif // __cplusplus + + #define SUBTARGET_OVERRIDE_OPTIONS (void) 0 +@@ -1568,7 +1576,7 @@ extern bool current_function_interrupt; + + /* Nonzero if the target supports dynamic shift instructions + like shad and shld. */ +-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) ++#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2) + + /* The cost of using the dynamic shift insns (shad, shld) are the same + if they are available. If they are not available a library function will +@@ -1833,6 +1841,7 @@ enum processor_type { + PROCESSOR_SH2, + PROCESSOR_SH2E, + PROCESSOR_SH2A, ++ PROCESSOR_SHJ2, + PROCESSOR_SH3, + PROCESSOR_SH3E, + PROCESSOR_SH4, +diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt +index c4f0d964d00..792af395b5d 100644 +--- a/gcc/config/sh/sh.opt ++++ b/gcc/config/sh/sh.opt +@@ -65,6 +65,10 @@ m2e + Target RejectNegative Condition(SUPPORT_SH2E) + Generate SH2e code. + ++mj2 ++Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2) ++Generate J2 code. ++ + m3 + Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) + Generate SH3 code. +diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md +index b46ac3131a8..72705583f84 100644 +--- a/gcc/config/sh/sync.md ++++ b/gcc/config/sh/sync.md +@@ -240,6 +240,9 @@ + || (TARGET_SH4A && mode == SImode && !TARGET_ATOMIC_STRICT)) + atomic_insn = gen_atomic_compare_and_swap_hard (old_val, mem, + exp_val, new_val); ++ else if (TARGET_ATOMIC_HARD_CAS && mode == SImode) ++ atomic_insn = gen_atomic_compare_and_swap_cas (old_val, mem, ++ exp_val, new_val); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic_compare_and_swap_soft_gusa (old_val, mem, + exp_val, new_val); +@@ -306,6 +309,57 @@ + } + [(set_attr "length" "14")]) + ++(define_expand "atomic_compare_and_swapsi_cas" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "r")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{ ++ rtx mem = gen_rtx_REG (SImode, 0); ++ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0))); ++ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_insn "shj2_cas" ++ [(set (match_operand:SI 0 "register_operand" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "register_operand" "=r") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "0")] ++ UNSPECV_CMPXCHG_1)) ++ (set (reg:SI T_REG) ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))] ++ "TARGET_ATOMIC_HARD_CAS" ++ "cas.l %2,%0,@%1" ++ [(set_attr "length" "2")] ++) ++ ++(define_expand "atomic_compare_and_swapqi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ ++(define_expand "atomic_compare_and_swaphi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ + ;; The QIHImode llcs patterns modify the address register of the memory + ;; operand. In order to express that, we have to open code the memory + ;; operand. Initially the insn is expanded like every other atomic insn +diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh +index 409554a8c8d..d354c11c8f2 100644 +--- a/gcc/config/sh/t-sh ++++ b/gcc/config/sh/t-sh +@@ -50,7 +50,8 @@ MULTILIB_MATCHES = $(shell \ + m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \ + m2a-single,m2a-single-only \ + m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \ +- m4,m4-100,m4-200,m4-300,m4a; do \ ++ m4,m4-100,m4-200,m4-300,m4a \ ++ mj2; do \ + subst= ; \ + for lib in `echo $$abi|tr , ' '` ; do \ + if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \ +@@ -63,9 +64,9 @@ MULTILIB_MATCHES = $(shell \ + + # SH1 and SH2A support big endian only. + ifeq ($(DEFAULT_ENDIAN),ml) +-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + else +-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + endif + + MULTILIB_OSDIRNAMES = \ +@@ -87,7 +88,8 @@ MULTILIB_OSDIRNAMES = \ + m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \ + m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \ + m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \ +- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al ++ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \ ++ mj2=!j2 + + $(out_object_file): gt-sh.h + gt-sh.h : s-gtype ; @true diff --git a/patches/gcc-7.5.0/0012-s390x-muslldso.diff b/patches/gcc-7.5.0/0012-s390x-muslldso.diff new file mode 100644 index 0000000..b6c8e7e --- /dev/null +++ b/patches/gcc-7.5.0/0012-s390x-muslldso.diff @@ -0,0 +1,14 @@ +diff --git a/gcc/config/s390/linux.h b/gcc/config/s390/linux.h +index 739df00f62d..ccd48ee7b84 100644 +--- a/gcc/config/s390/linux.h ++++ b/gcc/config/s390/linux.h +@@ -76,6 +76,9 @@ along with GCC; see the file COPYING3. If not see + #define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1" + #define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1" + ++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-s390.so.1" ++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-s390x.so.1" ++ + #undef LINK_SPEC + #define LINK_SPEC \ + "%{m31:-m elf_s390}%{m64:-m elf64_s390} \ diff --git a/patches/gcc-7.5.0/0013-microblaze-pr65649.diff b/patches/gcc-7.5.0/0013-microblaze-pr65649.diff new file mode 100644 index 0000000..2d64a86 --- /dev/null +++ b/patches/gcc-7.5.0/0013-microblaze-pr65649.diff @@ -0,0 +1,22 @@ +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index d0f86fd4607..dc34ab960bf 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2375,7 +2375,7 @@ print_operand (FILE * file, rtx op, int letter) + unsigned long value_long; + REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), + value_long); +- fprintf (file, HOST_WIDE_INT_PRINT_HEX, value_long); ++ fprintf (file, "0x%lx", value_long); + } + else + { +@@ -2434,7 +2434,7 @@ print_operand (FILE * file, rtx op, int letter) + print_operand_address (file, XEXP (op, 0)); + } + else if (letter == 'm') +- fprintf (file, HOST_WIDE_INT_PRINT_DEC, (1L << INTVAL (op))); ++ fprintf (file, "%ld", (1L << INTVAL (op))); + else + output_addr_const (file, op); + } diff --git a/patches/gcc-7.5.0/0014-ldbl128-config.diff b/patches/gcc-7.5.0/0014-ldbl128-config.diff new file mode 100644 index 0000000..a1ee4d0 --- /dev/null +++ b/patches/gcc-7.5.0/0014-ldbl128-config.diff @@ -0,0 +1,63 @@ +diff --git a/gcc/configure b/gcc/configure +index 043a62b0de9..cbb10aca436 100755 +--- a/gcc/configure ++++ b/gcc/configure +@@ -29054,6 +29054,15 @@ if test "${with_long_double_128+set}" = set; then : + withval=$with_long_double_128; gcc_cv_target_ldbl128="$with_long_double_128" + else + ++ case "$target" in ++ s390*-*-linux-musl*) ++ gcc_cv_target_ldbl128=yes ++ ;; ++ powerpc*-*-linux-musl*) ++ gcc_cv_target_ldbl128=no ++ ;; ++ *) ++ + if test $glibc_version_major -gt 2 \ + || ( test $glibc_version_major -eq 2 && test $glibc_version_minor -ge 4 ); then : + gcc_cv_target_ldbl128=yes +@@ -29065,6 +29074,10 @@ else + && gcc_cv_target_ldbl128=yes + + fi ++ ++ ;; ++ esac ++ + fi + + ;; +diff --git a/gcc/configure.ac b/gcc/configure.ac +index 2b52da3bbcc..31154c73858 100644 +--- a/gcc/configure.ac ++++ b/gcc/configure.ac +@@ -5801,13 +5801,25 @@ case "$target" in + AC_ARG_WITH(long-double-128, + [AS_HELP_STRING([--with-long-double-128], + [use 128-bit long double by default])], +- gcc_cv_target_ldbl128="$with_long_double_128", ++ gcc_cv_target_ldbl128="$with_long_double_128", [ ++ case "$target" in ++ s390*-*-linux-musl*) ++ gcc_cv_target_ldbl128=yes ++ ;; ++ powerpc*-*-linux-musl*) ++ gcc_cv_target_ldbl128=no ++ ;; ++ *)] + [GCC_GLIBC_VERSION_GTE_IFELSE([2], [4], [gcc_cv_target_ldbl128=yes], [ + [gcc_cv_target_ldbl128=no + grep '^[ ]*#[ ]*define[ ][ ]*__LONG_DOUBLE_MATH_OPTIONAL' \ + $target_header_dir/bits/wordsize.h > /dev/null 2>&1 \ + && gcc_cv_target_ldbl128=yes +- ]])]) ++ ]])] ++ [ ++ ;; ++ esac ++ ]) + ;; + esac + if test x$gcc_cv_target_ldbl128 = xyes; then diff --git a/patches/gcc-7.5.0/0015-m68k.diff b/patches/gcc-7.5.0/0015-m68k.diff new file mode 100644 index 0000000..fd5ba39 --- /dev/null +++ b/patches/gcc-7.5.0/0015-m68k.diff @@ -0,0 +1,27 @@ +diff --git a/gcc/config/m68k/linux.h b/gcc/config/m68k/linux.h +index c6e005604d4..868c9cc3265 100644 +--- a/gcc/config/m68k/linux.h ++++ b/gcc/config/m68k/linux.h +@@ -73,6 +73,9 @@ along with GCC; see the file COPYING3. If not see + + #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" + ++#undef MUSL_DYNAMIC_LINKER ++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-m68k.so.1" ++ + #undef LINK_SPEC + #define LINK_SPEC "-m m68kelf %{shared} \ + %{!shared: \ +diff --git a/libgcc/config/m68k/linux-unwind.h b/libgcc/config/m68k/linux-unwind.h +index 9ea39d454aa..ecab17d3ee7 100644 +--- a/libgcc/config/m68k/linux-unwind.h ++++ b/libgcc/config/m68k/linux-unwind.h +@@ -37,7 +37,7 @@ struct uw_ucontext { + stack_t uc_stack; + mcontext_t uc_mcontext; + unsigned long uc_filler[80]; +- __sigset_t uc_sigmask; ++ sigset_t uc_sigmask; + }; + + #define MD_FALLBACK_FRAME_STATE_FOR m68k_fallback_frame_state diff --git a/patches/gcc-7.5.0/0016-invalid_tls_model.diff b/patches/gcc-7.5.0/0016-invalid_tls_model.diff new file mode 100644 index 0000000..d3b2b8e --- /dev/null +++ b/patches/gcc-7.5.0/0016-invalid_tls_model.diff @@ -0,0 +1,51 @@ +--- gcc-7.3.0/libgomp/configure.tgt.orig 2018-09-25 13:44:16.654561098 -0400 ++++ gcc-7.3.0/libgomp/configure.tgt 2018-09-25 13:44:50.452688100 -0400 +@@ -10,23 +10,6 @@ + # XCFLAGS Add extra compile flags to use. + # XLDFLAGS Add extra link flags to use. + +-# Optimize TLS usage by avoiding the overhead of dynamic allocation. +-if test $gcc_cv_have_tls = yes ; then +- case "${target}" in +- +- *-*-k*bsd*-gnu*) +- ;; +- +- *-*-linux* | *-*-gnu*) +- XCFLAGS="${XCFLAGS} -ftls-model=initial-exec" +- ;; +- +- *-*-rtems*) +- XCFLAGS="${XCFLAGS} -ftls-model=local-exec" +- ;; +- esac +-fi +- + # Since we require POSIX threads, assume a POSIX system by default. + config_path="posix" + +--- gcc-7.3.0/libitm/configure.tgt.orig 2018-09-25 13:47:31.019296903 -0400 ++++ gcc-7.3.0/libitm/configure.tgt 2018-09-25 13:47:37.676322335 -0400 +@@ -27,22 +27,6 @@ + # XCFLAGS Add extra compile flags to use. + # XLDFLAGS Add extra link flags to use. + +-# Optimize TLS usage by avoiding the overhead of dynamic allocation. +-if test "$gcc_cv_have_tls" = yes ; then +- case "${target}" in +- +- # For x86, we use slots in the TCB head for most of our TLS. +- # The setup of those slots in beginTransaction can afford to +- # use the global-dynamic model. +- i[456]86-*-linux* | x86_64-*-linux*) +- ;; +- +- *-*-linux*) +- XCFLAGS="${XCFLAGS} -ftls-model=initial-exec" +- ;; +- esac +-fi +- + # Map the target cpu to an ARCH sub-directory. At the same time, + # work out any special compilation flags as necessary. + case "${target_cpu}" in diff --git a/patches/gcc-7.5.0/0017-fix-gthr-weak-refs-for-libgcc.patch b/patches/gcc-7.5.0/0017-fix-gthr-weak-refs-for-libgcc.patch new file mode 100644 index 0000000..56291a2 --- /dev/null +++ b/patches/gcc-7.5.0/0017-fix-gthr-weak-refs-for-libgcc.patch @@ -0,0 +1,51 @@ +From 51a354a0fb54165d505bfed9819c0440027312d9 Mon Sep 17 00:00:00 2001 +From: Szabolcs Nagy +Date: Sun, 22 Sep 2019 23:04:48 +0000 +Subject: [PATCH] fix gthr weak refs for libgcc + +ideally gthr-posix.h should be fixed not to use weak refs for +single thread detection by default since that's unsafe. + +currently we have to opt out explicitly from the unsafe behaviour +in the configure machinery of each target lib that uses gthr and +musl missed libgcc previously. + +related bugs and discussions +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78017 +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87189 +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91737 +https://sourceware.org/bugzilla/show_bug.cgi?id=5784 +https://sourceware.org/ml/libc-alpha/2012-09/msg00192.html +https://sourceware.org/ml/libc-alpha/2019-08/msg00438.html +--- + libgcc/config.host | 7 +++++++ + libgcc/config/t-gthr-noweak | 2 ++ + 2 files changed, 9 insertions(+) + create mode 100644 libgcc/config/t-gthr-noweak + +diff --git a/libgcc/config.host b/libgcc/config.host +index 122113fc519..fe1b9ab93d5 100644 +--- a/libgcc/config.host ++++ b/libgcc/config.host +@@ -1500,3 +1500,10 @@ aarch64*-*-*) + tm_file="${tm_file} aarch64/value-unwind.h" + ;; + esac ++ ++case ${host} in ++*-*-musl*) ++ # The gthr weak references are unsafe with static linking ++ tmake_file="$tmake_file t-gthr-noweak" ++ ;; ++esac +diff --git a/libgcc/config/t-gthr-noweak b/libgcc/config/t-gthr-noweak +new file mode 100644 +index 00000000000..45a21e9361d +--- /dev/null ++++ b/libgcc/config/t-gthr-noweak +@@ -0,0 +1,2 @@ ++# Don't use weak references for single-thread detection ++HOST_LIBGCC2_CFLAGS += -DGTHREAD_USE_WEAK=0 +-- +2.17.1 + diff --git a/patches/gcc-7.5.0/0018-riscv-tls-copy-relocs.diff b/patches/gcc-7.5.0/0018-riscv-tls-copy-relocs.diff new file mode 100644 index 0000000..566be71 --- /dev/null +++ b/patches/gcc-7.5.0/0018-riscv-tls-copy-relocs.diff @@ -0,0 +1,16 @@ +diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c +index 677728e77ed..444d01e87ec 100644 +--- a/gcc/config/riscv/riscv.c ++++ b/gcc/config/riscv/riscv.c +@@ -1209,9 +1209,11 @@ riscv_legitimize_tls_address (rtx loc) + rtx dest, tp, tmp; + enum tls_model model = SYMBOL_REF_TLS_MODEL (loc); + ++#if 0 + /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */ + if (!flag_pic) + model = TLS_MODEL_LOCAL_EXEC; ++#endif + + switch (model) + { diff --git a/patches/gcc-7.5.0/0019-libstdc++-futex-time64.diff b/patches/gcc-7.5.0/0019-libstdc++-futex-time64.diff new file mode 100644 index 0000000..08f6261 --- /dev/null +++ b/patches/gcc-7.5.0/0019-libstdc++-futex-time64.diff @@ -0,0 +1,18 @@ +--- gcc-9.2.0/libstdc++-v3/src/c++11/futex.cc.orig 2020-01-20 14:55:05.507548334 -0500 ++++ gcc-9.2.0/libstdc++-v3/src/c++11/futex.cc 2020-01-20 14:56:52.458268068 -0500 +@@ -61,7 +61,15 @@ + struct timeval tv; + gettimeofday (&tv, NULL); + // Convert the absolute timeout value to a relative timeout ++#if defined(SYS_futex_time64) && SYS_futex_time64 != SYS_futex ++ struct ++ { ++ long tv_sec; ++ long tv_nsec; ++ } rt; ++#else + struct timespec rt; ++#endif + rt.tv_sec = __s.count() - tv.tv_sec; + rt.tv_nsec = __ns.count() - tv.tv_usec * 1000; + if (rt.tv_nsec < 0) diff --git a/patches/gcc-7.5.0/0020-pr93402.diff b/patches/gcc-7.5.0/0020-pr93402.diff new file mode 100644 index 0000000..c985fb6 --- /dev/null +++ b/patches/gcc-7.5.0/0020-pr93402.diff @@ -0,0 +1,45 @@ +2020-01-23 Jakub Jelinek + + PR rtl-optimization/93402 + * postreload.c (reload_combine_recognize_pattern): Don't try to adjust + USE insns. + + * gcc.c-torture/execute/pr93402.c: New test. + +--- a/gcc/postreload.c.jj 2020-01-12 11:54:36.000000000 +0100 ++++ b/gcc/postreload.c 2020-01-23 17:23:25.359929516 +0100 +@@ -1078,6 +1078,10 @@ reload_combine_recognize_pattern (rtx_in + struct reg_use *use = reg_state[regno].reg_use + i; + if (GET_MODE (*use->usep) != mode) + return false; ++ /* Don't try to adjust (use (REGX)). */ ++ if (GET_CODE (PATTERN (use->insn)) == USE ++ && &XEXP (PATTERN (use->insn), 0) == use->usep) ++ return false; + } + + /* Look for (set (REGX) (CONST_INT)) +--- a/gcc/testsuite/gcc.c-torture/execute/pr93402.c.jj 2020-01-23 17:25:46.496803852 +0100 ++++ b/gcc/testsuite/gcc.c-torture/execute/pr93402.c 2020-01-23 17:25:05.221425501 +0100 +@@ -0,0 +1,21 @@ ++/* PR rtl-optimization/93402 */ ++ ++struct S { unsigned int a; unsigned long long b; }; ++ ++__attribute__((noipa)) struct S ++foo (unsigned long long x) ++{ ++ struct S ret; ++ ret.a = 0; ++ ret.b = x * 11111111111ULL + 111111111111ULL; ++ return ret; ++} ++ ++int ++main () ++{ ++ struct S a = foo (1); ++ if (a.a != 0 || a.b != 122222222222ULL) ++ __builtin_abort (); ++ return 0; ++} diff --git a/patches/gcc-7.5.0/0021-m68k-sqrt.diff b/patches/gcc-7.5.0/0021-m68k-sqrt.diff new file mode 100644 index 0000000..5d46272 --- /dev/null +++ b/patches/gcc-7.5.0/0021-m68k-sqrt.diff @@ -0,0 +1,18 @@ +--- gcc-9.2.0.orig/gcc/config/m68k/m68k.md 2019-01-01 07:31:55.000000000 -0500 ++++ gcc-9.2.0/gcc/config/m68k/m68k.md 2020-07-01 15:57:20.528408009 -0400 +@@ -4126,13 +4126,13 @@ + (define_expand "sqrt2" + [(set (match_operand:FP 0 "nonimmediate_operand" "") + (sqrt:FP (match_operand:FP 1 "general_operand" "")))] +- "TARGET_HARD_FLOAT" ++ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU" + "") + + (define_insn "sqrt2_68881" + [(set (match_operand:FP 0 "nonimmediate_operand" "=f") + (sqrt:FP (match_operand:FP 1 "general_operand" "fm")))] +- "TARGET_68881" ++ "TARGET_68881 && TARGET_68040" + { + if (FP_REG_P (operands[1])) + return "fsqrt%.x %1,%0"; diff --git a/patches/gcc-7.5.0/0022-powerpcspe-musl-ldsoname.diff b/patches/gcc-7.5.0/0022-powerpcspe-musl-ldsoname.diff new file mode 100644 index 0000000..f88fd85 --- /dev/null +++ b/patches/gcc-7.5.0/0022-powerpcspe-musl-ldsoname.diff @@ -0,0 +1,22 @@ +--- gcc-8.5.0/gcc/config/rs6000/sysv4.h.orig 2021-07-05 12:56:18.398813835 -0400 ++++ gcc-8.5.0/gcc/config/rs6000/sysv4.h 2021-06-23 21:49:57.592408186 -0400 +@@ -793,7 +793,7 @@ + #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" + #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0" + #define MUSL_DYNAMIC_LINKER \ +- "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" ++ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float|mcpu=854*|mspe:-sf}.so.1" + #if DEFAULT_LIBC == LIBC_UCLIBC + #define CHOOSE_DYNAMIC_LINKER(G, U, M) \ + "%{mglibc:" G ";:%{mmusl:" M ";:" U "}}" +--- gcc-8.5.0/gcc/config/rs6000/linux64.h.orig 2021-07-05 12:54:24.704854044 -0400 ++++ gcc-8.5.0/gcc/config/rs6000/linux64.h 2021-07-05 12:56:50.010806923 -0400 +@@ -426,7 +426,7 @@ + #endif + + #define MUSL_DYNAMIC_LINKER32 \ +- "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" ++ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float|mcpu=854*|mspe:-sf}.so.1" + #define MUSL_DYNAMIC_LINKER64 \ + "/lib/ld-musl-powerpc64" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" + diff --git a/patches/gcc-8.5.0/0001-ssp_nonshared.diff b/patches/gcc-8.5.0/0001-ssp_nonshared.diff new file mode 100644 index 0000000..b4134de --- /dev/null +++ b/patches/gcc-8.5.0/0001-ssp_nonshared.diff @@ -0,0 +1,14 @@ +diff --git a/gcc/gcc.c b/gcc/gcc.c +index a716f708259..eb1610ba8b0 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -870,7 +870,8 @@ proper position among the other output files. */ + #ifndef LINK_SSP_SPEC + #ifdef TARGET_LIBC_PROVIDES_SSP + #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ +- "|fstack-protector-strong|fstack-protector-explicit:}" ++ "|fstack-protector-strong|fstack-protector-explicit" \ ++ ":-lssp_nonshared}" + #else + #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ + "|fstack-protector-strong|fstack-protector-explicit" \ diff --git a/patches/gcc-8.5.0/0002-posix_memalign.diff b/patches/gcc-8.5.0/0002-posix_memalign.diff new file mode 100644 index 0000000..b403dab --- /dev/null +++ b/patches/gcc-8.5.0/0002-posix_memalign.diff @@ -0,0 +1,30 @@ +diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h +index ffbb7f82cf5..b0b890d2403 100644 +--- a/gcc/config/i386/pmm_malloc.h ++++ b/gcc/config/i386/pmm_malloc.h +@@ -27,12 +27,13 @@ + #include + + /* We can't depend on since the prototype of posix_memalign +- may not be visible. */ ++ may not be visible and we can't pollute the namespace either. */ + #ifndef __cplusplus +-extern int posix_memalign (void **, size_t, size_t); ++extern int _mm_posix_memalign (void **, size_t, size_t) + #else +-extern "C" int posix_memalign (void **, size_t, size_t) throw (); ++extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw () + #endif ++__asm__("posix_memalign"); + + static __inline void * + _mm_malloc (size_t __size, size_t __alignment) +@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment) + return malloc (__size); + if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4)) + __alignment = sizeof (void *); +- if (posix_memalign (&__ptr, __alignment, __size) == 0) ++ if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0) + return __ptr; + else + return NULL; diff --git a/patches/gcc-8.5.0/0003-libatomic-test-fix.diff b/patches/gcc-8.5.0/0003-libatomic-test-fix.diff new file mode 100644 index 0000000..27b437e --- /dev/null +++ b/patches/gcc-8.5.0/0003-libatomic-test-fix.diff @@ -0,0 +1,58 @@ +diff --git a/libatomic/testsuite/Makefile.am b/libatomic/testsuite/Makefile.am +index a9a0144185a..a19101aac54 100644 +--- a/libatomic/testsuite/Makefile.am ++++ b/libatomic/testsuite/Makefile.am +@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \ + _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++ ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ +diff --git a/libatomic/testsuite/Makefile.in b/libatomic/testsuite/Makefile.in +index 0a7ac4b4dc7..704db219fa3 100644 +--- a/libatomic/testsuite/Makefile.in ++++ b/libatomic/testsuite/Makefile.in +@@ -226,6 +226,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -432,6 +433,10 @@ uninstall-am: + uninstall uninstall-am + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Tell versions [3.59,3.63) of GNU make to not export all variables. + # Otherwise a system limit (for SysV at least) may be exceeded. + .NOEXPORT: +diff --git a/libatomic/testsuite/lib/libatomic.exp b/libatomic/testsuite/lib/libatomic.exp +index 0a53f9e11f1..51b35919f2d 100644 +--- a/libatomic/testsuite/lib/libatomic.exp ++++ b/libatomic/testsuite/lib/libatomic.exp +@@ -75,6 +75,7 @@ proc libatomic_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -90,6 +91,8 @@ proc libatomic_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-8.5.0/0004-libgomp-test-fix.diff b/patches/gcc-8.5.0/0004-libgomp-test-fix.diff new file mode 100644 index 0000000..f60c331 --- /dev/null +++ b/patches/gcc-8.5.0/0004-libgomp-test-fix.diff @@ -0,0 +1,60 @@ +diff --git a/libgomp/testsuite/Makefile.am b/libgomp/testsuite/Makefile.am +index e2a3f460eb0..3309f71e02e 100644 +--- a/libgomp/testsuite/Makefile.am ++++ b/libgomp/testsuite/Makefile.am +@@ -12,6 +12,11 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" + ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ + + # Instead of directly in ../testsuite/libgomp-test-support.exp.in, the + # following variables have to be "routed through" this Makefile, for expansion +diff --git a/libgomp/testsuite/Makefile.in b/libgomp/testsuite/Makefile.in +index 9310138c32c..4c0cc0a3013 100644 +--- a/libgomp/testsuite/Makefile.in ++++ b/libgomp/testsuite/Makefile.in +@@ -254,6 +254,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -462,6 +463,10 @@ uninstall-am: + ps ps-am uninstall uninstall-am + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Instead of directly in ../testsuite/libgomp-test-support.exp.in, the + # following variables have to be "routed through" this Makefile, for expansion + # of the several (Makefile) variables used therein. +diff --git a/libgomp/testsuite/lib/libgomp.exp b/libgomp/testsuite/lib/libgomp.exp +index ea3da2cb383..e7df78916ea 100644 +--- a/libgomp/testsuite/lib/libgomp.exp ++++ b/libgomp/testsuite/lib/libgomp.exp +@@ -86,6 +86,7 @@ proc libgomp_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -108,6 +109,8 @@ proc libgomp_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-8.5.0/0005-libitm-test-fix.diff b/patches/gcc-8.5.0/0005-libitm-test-fix.diff new file mode 100644 index 0000000..f63a754 --- /dev/null +++ b/patches/gcc-8.5.0/0005-libitm-test-fix.diff @@ -0,0 +1,58 @@ +diff --git a/libitm/testsuite/Makefile.am b/libitm/testsuite/Makefile.am +index a9a0144185a..a19101aac54 100644 +--- a/libitm/testsuite/Makefile.am ++++ b/libitm/testsuite/Makefile.am +@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \ + _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++ ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ +diff --git a/libitm/testsuite/Makefile.in b/libitm/testsuite/Makefile.in +index 34dcdd2dae0..458932c315d 100644 +--- a/libitm/testsuite/Makefile.in ++++ b/libitm/testsuite/Makefile.in +@@ -234,6 +234,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -440,6 +441,10 @@ uninstall-am: + uninstall uninstall-am + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Tell versions [3.59,3.63) of GNU make to not export all variables. + # Otherwise a system limit (for SysV at least) may be exceeded. + .NOEXPORT: +diff --git a/libitm/testsuite/lib/libitm.exp b/libitm/testsuite/lib/libitm.exp +index b3c7eb94f94..5f06cb6c50e 100644 +--- a/libitm/testsuite/lib/libitm.exp ++++ b/libitm/testsuite/lib/libitm.exp +@@ -75,6 +75,7 @@ proc libitm_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -90,6 +91,8 @@ proc libitm_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-8.5.0/0006-libvtv-test-fix.diff b/patches/gcc-8.5.0/0006-libvtv-test-fix.diff new file mode 100644 index 0000000..a74c8e1 --- /dev/null +++ b/patches/gcc-8.5.0/0006-libvtv-test-fix.diff @@ -0,0 +1,58 @@ +diff --git a/libvtv/testsuite/Makefile.am b/libvtv/testsuite/Makefile.am +index a9a0144185a..a19101aac54 100644 +--- a/libvtv/testsuite/Makefile.am ++++ b/libvtv/testsuite/Makefile.am +@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \ + _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++ ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ +diff --git a/libvtv/testsuite/Makefile.in b/libvtv/testsuite/Makefile.in +index f6314708e9f..cd281ac1ff7 100644 +--- a/libvtv/testsuite/Makefile.in ++++ b/libvtv/testsuite/Makefile.in +@@ -229,6 +229,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)" ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -435,6 +436,10 @@ uninstall-am: + uninstall uninstall-am + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Tell versions [3.59,3.63) of GNU make to not export all variables. + # Otherwise a system limit (for SysV at least) may be exceeded. + .NOEXPORT: +diff --git a/libvtv/testsuite/lib/libvtv.exp b/libvtv/testsuite/lib/libvtv.exp +index edf5fddbad2..a596091573b 100644 +--- a/libvtv/testsuite/lib/libvtv.exp ++++ b/libvtv/testsuite/lib/libvtv.exp +@@ -74,6 +74,7 @@ proc libvtv_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -89,6 +90,8 @@ proc libvtv_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-8.5.0/0007-j2.diff b/patches/gcc-8.5.0/0007-j2.diff new file mode 100644 index 0000000..1d76040 --- /dev/null +++ b/patches/gcc-8.5.0/0007-j2.diff @@ -0,0 +1,346 @@ +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 532c33f4c2b..20cdc192b82 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -505,7 +505,7 @@ s390*-*-*) + extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h" + ;; + # Note the 'l'; we need to be able to match e.g. "shle" or "shl". +-sh[123456789lbe]*-*-* | sh-*-*) ++sh[123456789lbej]*-*-* | sh-*-*) + cpu_type=sh + extra_options="${extra_options} fused-madd.opt" + extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o" +@@ -2725,18 +2725,18 @@ s390x-ibm-tpf*) + extra_options="${extra_options} s390/tpf.opt" + tmake_file="${tmake_file} s390/t-s390" + ;; +-sh-*-elf* | sh[12346l]*-*-elf* | \ +- sh-*-linux* | sh[2346lbe]*-*-linux* | \ ++sh-*-elf* | sh[12346lj]*-*-elf* | \ ++ sh-*-linux* | sh[2346lbej]*-*-linux* | \ + sh-*-netbsdelf* | shl*-*-netbsdelf*) + tmake_file="${tmake_file} sh/t-sh sh/t-elf" + if test x${with_endian} = x; then + case ${target} in +- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;; ++ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;; + shbe-*-* | sheb-*-*) with_endian=big,little ;; + sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;; + shl* | sh*-*-linux* | \ + sh-superh-elf) with_endian=little,big ;; +- sh[1234]*-*-*) with_endian=big ;; ++ sh[j1234]*-*-*) with_endian=big ;; + *) with_endian=big,little ;; + esac + fi +@@ -2803,6 +2803,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;; + sh2a*) sh_cpu_target=sh2a ;; + sh2e*) sh_cpu_target=sh2e ;; ++ shj2*) sh_cpu_target=shj2;; + sh2*) sh_cpu_target=sh2 ;; + *) sh_cpu_target=sh1 ;; + esac +@@ -2824,7 +2825,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \ + sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \ + sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \ +- sh3e | sh3 | sh2e | sh2 | sh1) ;; ++ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;; + "") sh_cpu_default=${sh_cpu_target} ;; + *) echo "with_cpu=$with_cpu not supported"; exit 1 ;; + esac +@@ -2833,9 +2834,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + case ${target} in + sh[1234]*) sh_multilibs=${sh_cpu_target} ;; + sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;; +- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;; ++ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;; + sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;; +- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;; ++ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;; + esac + if test x$with_fp = xno; then + sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`" +@@ -2850,7 +2851,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + m1 | m2 | m2e | m3 | m3e | \ + m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\ + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \ +- m2a | m2a-single | m2a-single-only | m2a-nofpu) ++ m2a | m2a-single | m2a-single-only | m2a-nofpu | \ ++ mj2) + # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition + # It is passed to MULTIILIB_OPTIONS verbatim. + TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}" +@@ -2867,7 +2869,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + done + TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'` + if test x${enable_incomplete_targets} = xyes ; then +- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1" ++ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1" + fi + tm_file="$tm_file ./sysroot-suffix.h" + tmake_file="$tmake_file t-sysroot-suffix" +@@ -4518,6 +4520,8 @@ case "${target}" in + ;; + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al) + ;; ++ mj2) ++ ;; + *) + echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2 + echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2 +@@ -4729,7 +4733,7 @@ case ${target} in + tmake_file="${cpu_type}/t-${cpu_type} ${tmake_file}" + ;; + +- sh[123456ble]*-*-* | sh-*-*) ++ sh[123456blej]*-*-* | sh-*-*) + c_target_objs="${c_target_objs} sh-c.o" + cxx_target_objs="${cxx_target_objs} sh-c.o" + ;; +diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c +index ced66408265..c51b00d8e8b 100644 +--- a/gcc/config/sh/sh.c ++++ b/gcc/config/sh/sh.c +@@ -685,6 +685,7 @@ parse_validate_atomic_model_option (const char* str) + model_names[sh_atomic_model::hard_llcs] = "hard-llcs"; + model_names[sh_atomic_model::soft_tcb] = "soft-tcb"; + model_names[sh_atomic_model::soft_imask] = "soft-imask"; ++ model_names[sh_atomic_model::hard_cas] = "hard-cas"; + + const char* model_cdef_names[sh_atomic_model::num_models]; + model_cdef_names[sh_atomic_model::none] = "NONE"; +@@ -692,6 +693,7 @@ parse_validate_atomic_model_option (const char* str) + model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS"; + model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB"; + model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK"; ++ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS"; + + sh_atomic_model ret; + ret.type = sh_atomic_model::none; +@@ -770,6 +772,9 @@ got_mode_name:; + if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE) + err_ret ("cannot use atomic model %s in user mode", ret.name); + ++ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2) ++ err_ret ("atomic model %s is only available J2 targets", ret.name); ++ + return ret; + + #undef err_ret +@@ -826,6 +831,8 @@ sh_option_override (void) + sh_cpu = PROCESSOR_SH2E; + if (TARGET_SH2A) + sh_cpu = PROCESSOR_SH2A; ++ if (TARGET_SHJ2) ++ sh_cpu = PROCESSOR_SHJ2; + if (TARGET_SH3) + sh_cpu = PROCESSOR_SH3; + if (TARGET_SH3E) +diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h +index 2f5930bbebd..5a6d113a011 100644 +--- a/gcc/config/sh/sh.h ++++ b/gcc/config/sh/sh.h +@@ -83,6 +83,7 @@ extern int code_for_indirect_jump_scratch; + #define SUPPORT_SH4_SINGLE 1 + #define SUPPORT_SH2A 1 + #define SUPPORT_SH2A_SINGLE 1 ++#define SUPPORT_SHJ2 1 + #endif + + #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) +@@ -115,6 +116,7 @@ extern int code_for_indirect_jump_scratch; + #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) + #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) + #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) ++#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2) + + #if SUPPORT_SH1 + #define SUPPORT_SH2 1 +@@ -122,6 +124,7 @@ extern int code_for_indirect_jump_scratch; + #if SUPPORT_SH2 + #define SUPPORT_SH3 1 + #define SUPPORT_SH2A_NOFPU 1 ++#define SUPPORT_SHJ2 1 + #endif + #if SUPPORT_SH3 + #define SUPPORT_SH4_NOFPU 1 +@@ -154,7 +157,7 @@ extern int code_for_indirect_jump_scratch; + #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ + | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ + | MASK_HARD_SH4 | MASK_FPU_SINGLE \ +- | MASK_FPU_SINGLE_ONLY) ++ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2) + + /* This defaults us to big-endian. */ + #ifndef TARGET_ENDIAN_DEFAULT +@@ -229,7 +232,8 @@ extern int code_for_indirect_jump_scratch; + %{m2a-single:--isa=sh2a} \ + %{m2a-single-only:--isa=sh2a} \ + %{m2a-nofpu:--isa=sh2a-nofpu} \ +-%{m4al:-dsp}" ++%{m4al:-dsp} \ ++%{mj2:-isa=j2}" + + #define ASM_SPEC SH_ASM_SPEC + +@@ -345,6 +349,7 @@ struct sh_atomic_model + hard_llcs, + soft_tcb, + soft_imask, ++ hard_cas, + + num_models + }; +@@ -388,6 +393,9 @@ extern const sh_atomic_model& selected_atomic_model (void); + #define TARGET_ATOMIC_SOFT_IMASK \ + (selected_atomic_model ().type == sh_atomic_model::soft_imask) + ++#define TARGET_ATOMIC_HARD_CAS \ ++ (selected_atomic_model ().type == sh_atomic_model::hard_cas) ++ + #endif // __cplusplus + + #define SUBTARGET_OVERRIDE_OPTIONS (void) 0 +@@ -1521,7 +1529,7 @@ extern bool current_function_interrupt; + + /* Nonzero if the target supports dynamic shift instructions + like shad and shld. */ +-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) ++#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2) + + /* The cost of using the dynamic shift insns (shad, shld) are the same + if they are available. If they are not available a library function will +@@ -1784,6 +1792,7 @@ enum processor_type { + PROCESSOR_SH2, + PROCESSOR_SH2E, + PROCESSOR_SH2A, ++ PROCESSOR_SHJ2, + PROCESSOR_SH3, + PROCESSOR_SH3E, + PROCESSOR_SH4, +diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt +index 837d9bfdc23..86b2cd6fc79 100644 +--- a/gcc/config/sh/sh.opt ++++ b/gcc/config/sh/sh.opt +@@ -65,6 +65,10 @@ m2e + Target RejectNegative Condition(SUPPORT_SH2E) + Generate SH2e code. + ++mj2 ++Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2) ++Generate J2 code. ++ + m3 + Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) + Generate SH3 code. +diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md +index 9dba513e642..5bc8acabf2f 100644 +--- a/gcc/config/sh/sync.md ++++ b/gcc/config/sh/sync.md +@@ -240,6 +240,9 @@ + || (TARGET_SH4A && mode == SImode && !TARGET_ATOMIC_STRICT)) + atomic_insn = gen_atomic_compare_and_swap_hard (old_val, mem, + exp_val, new_val); ++ else if (TARGET_ATOMIC_HARD_CAS && mode == SImode) ++ atomic_insn = gen_atomic_compare_and_swap_cas (old_val, mem, ++ exp_val, new_val); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic_compare_and_swap_soft_gusa (old_val, mem, + exp_val, new_val); +@@ -306,6 +309,57 @@ + } + [(set_attr "length" "14")]) + ++(define_expand "atomic_compare_and_swapsi_cas" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "r")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{ ++ rtx mem = gen_rtx_REG (SImode, 0); ++ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0))); ++ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_insn "shj2_cas" ++ [(set (match_operand:SI 0 "register_operand" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "register_operand" "=r") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "0")] ++ UNSPECV_CMPXCHG_1)) ++ (set (reg:SI T_REG) ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))] ++ "TARGET_ATOMIC_HARD_CAS" ++ "cas.l %2,%0,@%1" ++ [(set_attr "length" "2")] ++) ++ ++(define_expand "atomic_compare_and_swapqi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ ++(define_expand "atomic_compare_and_swaphi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ + ;; The QIHImode llcs patterns modify the address register of the memory + ;; operand. In order to express that, we have to open code the memory + ;; operand. Initially the insn is expanded like every other atomic insn +diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh +index a78c6a55127..386934dca8a 100644 +--- a/gcc/config/sh/t-sh ++++ b/gcc/config/sh/t-sh +@@ -50,7 +50,8 @@ MULTILIB_MATCHES = $(shell \ + m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \ + m2a-single,m2a-single-only \ + m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \ +- m4,m4-100,m4-200,m4-300,m4a; do \ ++ m4,m4-100,m4-200,m4-300,m4a \ ++ mj2; do \ + subst= ; \ + for lib in `echo $$abi|tr , ' '` ; do \ + if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \ +@@ -63,9 +64,9 @@ MULTILIB_MATCHES = $(shell \ + + # SH1 and SH2A support big endian only. + ifeq ($(DEFAULT_ENDIAN),ml) +-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + else +-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + endif + + MULTILIB_OSDIRNAMES = \ +@@ -87,7 +88,8 @@ MULTILIB_OSDIRNAMES = \ + m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \ + m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \ + m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \ +- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al ++ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \ ++ mj2=!j2 + + $(out_object_file): gt-sh.h + gt-sh.h : s-gtype ; @true diff --git a/patches/gcc-8.5.0/0008-s390x-muslldso.diff b/patches/gcc-8.5.0/0008-s390x-muslldso.diff new file mode 100644 index 0000000..4286653 --- /dev/null +++ b/patches/gcc-8.5.0/0008-s390x-muslldso.diff @@ -0,0 +1,14 @@ +diff --git a/gcc/config/s390/linux.h b/gcc/config/s390/linux.h +index 525c17c2c9f..2d4f4a0654e 100644 +--- a/gcc/config/s390/linux.h ++++ b/gcc/config/s390/linux.h +@@ -76,6 +76,9 @@ along with GCC; see the file COPYING3. If not see + #define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1" + #define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1" + ++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-s390.so.1" ++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-s390x.so.1" ++ + #undef LINK_SPEC + #define LINK_SPEC \ + "%{m31:-m elf_s390}%{m64:-m elf64_s390} \ diff --git a/patches/gcc-8.5.0/0009-microblaze-pr65649.diff b/patches/gcc-8.5.0/0009-microblaze-pr65649.diff new file mode 100644 index 0000000..8a70220 --- /dev/null +++ b/patches/gcc-8.5.0/0009-microblaze-pr65649.diff @@ -0,0 +1,22 @@ +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 9a4a287be23..60aadaf51f7 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2399,7 +2399,7 @@ print_operand (FILE * file, rtx op, int letter) + unsigned long value_long; + REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), + value_long); +- fprintf (file, HOST_WIDE_INT_PRINT_HEX, value_long); ++ fprintf (file, "0x%lx", value_long); + } + else + { +@@ -2458,7 +2458,7 @@ print_operand (FILE * file, rtx op, int letter) + print_operand_address (file, XEXP (op, 0)); + } + else if (letter == 'm') +- fprintf (file, HOST_WIDE_INT_PRINT_DEC, (1L << INTVAL (op))); ++ fprintf (file, "%ld", (1L << INTVAL (op))); + else + output_addr_const (file, op); + } diff --git a/patches/gcc-8.5.0/0010-ldbl128-config.diff b/patches/gcc-8.5.0/0010-ldbl128-config.diff new file mode 100644 index 0000000..9ca6c82 --- /dev/null +++ b/patches/gcc-8.5.0/0010-ldbl128-config.diff @@ -0,0 +1,63 @@ +diff --git a/gcc/configure b/gcc/configure +index 6121e163259..07ff8597d48 100755 +--- a/gcc/configure ++++ b/gcc/configure +@@ -29309,6 +29309,15 @@ if test "${with_long_double_128+set}" = set; then : + withval=$with_long_double_128; gcc_cv_target_ldbl128="$with_long_double_128" + else + ++ case "$target" in ++ s390*-*-linux-musl*) ++ gcc_cv_target_ldbl128=yes ++ ;; ++ powerpc*-*-linux-musl*) ++ gcc_cv_target_ldbl128=no ++ ;; ++ *) ++ + if test $glibc_version_major -gt 2 \ + || ( test $glibc_version_major -eq 2 && test $glibc_version_minor -ge 4 ); then : + gcc_cv_target_ldbl128=yes +@@ -29320,6 +29329,10 @@ else + && gcc_cv_target_ldbl128=yes + + fi ++ ++ ;; ++ esac ++ + fi + + ;; +diff --git a/gcc/configure.ac b/gcc/configure.ac +index b066cc609e1..6c15ed898c0 100644 +--- a/gcc/configure.ac ++++ b/gcc/configure.ac +@@ -5971,13 +5971,25 @@ case "$target" in + AC_ARG_WITH(long-double-128, + [AS_HELP_STRING([--with-long-double-128], + [use 128-bit long double by default])], +- gcc_cv_target_ldbl128="$with_long_double_128", ++ gcc_cv_target_ldbl128="$with_long_double_128", [ ++ case "$target" in ++ s390*-*-linux-musl*) ++ gcc_cv_target_ldbl128=yes ++ ;; ++ powerpc*-*-linux-musl*) ++ gcc_cv_target_ldbl128=no ++ ;; ++ *)] + [GCC_GLIBC_VERSION_GTE_IFELSE([2], [4], [gcc_cv_target_ldbl128=yes], [ + [gcc_cv_target_ldbl128=no + grep '^[ ]*#[ ]*define[ ][ ]*__LONG_DOUBLE_MATH_OPTIONAL' \ + $target_header_dir/bits/wordsize.h > /dev/null 2>&1 \ + && gcc_cv_target_ldbl128=yes +- ]])]) ++ ]])] ++ [ ++ ;; ++ esac ++ ]) + ;; + esac + if test x$gcc_cv_target_ldbl128 = xyes; then diff --git a/patches/gcc-8.5.0/0011-m68k.diff b/patches/gcc-8.5.0/0011-m68k.diff new file mode 100644 index 0000000..7caa5cb --- /dev/null +++ b/patches/gcc-8.5.0/0011-m68k.diff @@ -0,0 +1,27 @@ +diff --git a/gcc/config/m68k/linux.h b/gcc/config/m68k/linux.h +index f584d19e179..a3c215550fe 100644 +--- a/gcc/config/m68k/linux.h ++++ b/gcc/config/m68k/linux.h +@@ -73,6 +73,9 @@ along with GCC; see the file COPYING3. If not see + + #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" + ++#undef MUSL_DYNAMIC_LINKER ++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-m68k.so.1" ++ + #undef LINK_SPEC + #define LINK_SPEC "-m m68kelf %{shared} \ + %{!shared: \ +diff --git a/libgcc/config/m68k/linux-unwind.h b/libgcc/config/m68k/linux-unwind.h +index 395e4b3212a..432b757541c 100644 +--- a/libgcc/config/m68k/linux-unwind.h ++++ b/libgcc/config/m68k/linux-unwind.h +@@ -37,7 +37,7 @@ struct uw_ucontext { + stack_t uc_stack; + mcontext_t uc_mcontext; + unsigned long uc_filler[80]; +- __sigset_t uc_sigmask; ++ sigset_t uc_sigmask; + }; + + #define MD_FALLBACK_FRAME_STATE_FOR m68k_fallback_frame_state diff --git a/patches/gcc-8.5.0/0012-static-pie.diff b/patches/gcc-8.5.0/0012-static-pie.diff new file mode 100644 index 0000000..c0fcf07 --- /dev/null +++ b/patches/gcc-8.5.0/0012-static-pie.diff @@ -0,0 +1,117 @@ +diff --git a/gcc/common.opt b/gcc/common.opt +index b52ef0b38c8..0ce5857e01d 100644 +--- a/gcc/common.opt ++++ b/gcc/common.opt +@@ -3197,11 +3197,11 @@ Driver + + no-pie + Driver RejectNegative Negative(shared) +-Don't create a dynamically linked position independent executable. ++Don't create a position independent executable. + + pie + Driver RejectNegative Negative(no-pie) +-Create a dynamically linked position independent executable. ++Create a position independent executable. + + static-pie + Driver RejectNegative Negative(pie) +diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h +index 8620de3e42d..235328a2642 100644 +--- a/gcc/config/gnu-user.h ++++ b/gcc/config/gnu-user.h +@@ -52,13 +52,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define GNU_USER_TARGET_STARTFILE_SPEC \ + "%{shared:; \ + pg|p|profile:%{static-pie:grcrt1.o%s;:gcrt1.o%s}; \ +- static:crt1.o%s; \ +- static-pie:rcrt1.o%s; \ ++ static|static-pie:%{" PIE_SPEC ":rcrt1.o%s;:crt1.o%s}; \ + " PIE_SPEC ":Scrt1.o%s; \ + :crt1.o%s} \ + crti.o%s \ +- %{static:crtbeginT.o%s; \ +- shared|static-pie|" PIE_SPEC ":crtbeginS.o%s; \ ++ %{shared|" PIE_SPEC ":crtbeginS.o%s; \ ++ static:crtbeginT.o%s; \ + :crtbegin.o%s} \ + %{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_start_preinit.o%s; \ +@@ -92,8 +91,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + "%{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_end_preinit.o%s; \ + fvtable-verify=std:vtv_end.o%s} \ +- %{static:crtend.o%s; \ +- shared|static-pie|" PIE_SPEC ":crtendS.o%s; \ ++ %{shared|" PIE_SPEC ":crtendS.o%s; \ + :crtend.o%s} \ + crtn.o%s \ + " CRTOFFLOADEND +@@ -133,7 +131,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define LIB_SPEC GNU_USER_TARGET_LIB_SPEC + + #if defined(HAVE_LD_EH_FRAME_HDR) +-#define LINK_EH_SPEC "%{!static|static-pie:--eh-frame-hdr} " ++#define LINK_EH_SPEC "%{!static|" PIE_SPEC ":--eh-frame-hdr} " + #endif + + #undef LINK_GCC_C_SEQUENCE_SPEC +diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h +index bb19d0dcd41..bb2a2324eb0 100644 +--- a/gcc/config/rs6000/sysv4.h ++++ b/gcc/config/rs6000/sysv4.h +@@ -763,12 +763,12 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN) + #define STARTFILE_LINUX_SPEC \ + "%{shared:; \ + pg|p|profile:gcrt1.o%s; \ +- static:crt1.o%s; \ +- static-pie|" PIE_SPEC ":Scrt1.o%s; \ ++ static|static-pie:%{" PIE_SPEC ":rcrt1.o%s;:crt1.o%s}; \ ++ " PIE_SPEC ":Scrt1.o%s; \ + :crt1.o%s} \ + %{mnewlib:ecrti.o%s;:crti.o%s} \ +- %{static:crtbeginT.o%s; \ +- shared|static-pie|" PIE_SPEC ":crtbeginS.o%s; \ ++ %{shared|" PIE_SPEC ":crtbeginS.o%s; \ ++ static:crtbeginT.o%s; \ + :crtbegin.o%s} \ + %{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_start_preinit.o%s; \ +@@ -781,8 +781,7 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN) + "%{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_end_preinit.o%s; \ + fvtable-verify=std:vtv_end.o%s} \ +- %{static:crtend.o%s; \ +- shared|static-pie|" PIE_SPEC ":crtendS.o%s; \ ++ %{shared|" PIE_SPEC ":crtendS.o%s; \ + :crtend.o%s} \ + %{mnewlib:ecrtn.o%s;:crtn.o%s} \ + " CRTOFFLOADEND +diff --git a/gcc/gcc.c b/gcc/gcc.c +index eb1610ba8b0..87560afb03c 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -900,7 +900,7 @@ proper position among the other output files. */ + #define NO_FPIE_AND_FPIC_SPEC NO_FPIE_SPEC "|" NO_FPIC_SPEC + #define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;" + #else +-#define PIE_SPEC "pie" ++#define PIE_SPEC "pie|static-pie" + #define FPIE1_SPEC "fpie" + #define NO_FPIE1_SPEC FPIE1_SPEC ":;" + #define FPIE2_SPEC "fPIE" +@@ -924,12 +924,12 @@ proper position among the other output files. */ + #ifndef LINK_PIE_SPEC + #ifdef HAVE_LD_PIE + #ifndef LD_PIE_SPEC +-#define LD_PIE_SPEC "-pie" ++#define LD_PIE_SPEC "-pie %{static-pie:-static} %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}" + #endif + #else + #define LD_PIE_SPEC "" + #endif +-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} " ++#define LINK_PIE_SPEC "%{shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} " + #endif + + #ifndef LINK_BUILDID_SPEC diff --git a/patches/gcc-8.5.0/0013-invalid_tls_model.diff b/patches/gcc-8.5.0/0013-invalid_tls_model.diff new file mode 100644 index 0000000..d3b2b8e --- /dev/null +++ b/patches/gcc-8.5.0/0013-invalid_tls_model.diff @@ -0,0 +1,51 @@ +--- gcc-7.3.0/libgomp/configure.tgt.orig 2018-09-25 13:44:16.654561098 -0400 ++++ gcc-7.3.0/libgomp/configure.tgt 2018-09-25 13:44:50.452688100 -0400 +@@ -10,23 +10,6 @@ + # XCFLAGS Add extra compile flags to use. + # XLDFLAGS Add extra link flags to use. + +-# Optimize TLS usage by avoiding the overhead of dynamic allocation. +-if test $gcc_cv_have_tls = yes ; then +- case "${target}" in +- +- *-*-k*bsd*-gnu*) +- ;; +- +- *-*-linux* | *-*-gnu*) +- XCFLAGS="${XCFLAGS} -ftls-model=initial-exec" +- ;; +- +- *-*-rtems*) +- XCFLAGS="${XCFLAGS} -ftls-model=local-exec" +- ;; +- esac +-fi +- + # Since we require POSIX threads, assume a POSIX system by default. + config_path="posix" + +--- gcc-7.3.0/libitm/configure.tgt.orig 2018-09-25 13:47:31.019296903 -0400 ++++ gcc-7.3.0/libitm/configure.tgt 2018-09-25 13:47:37.676322335 -0400 +@@ -27,22 +27,6 @@ + # XCFLAGS Add extra compile flags to use. + # XLDFLAGS Add extra link flags to use. + +-# Optimize TLS usage by avoiding the overhead of dynamic allocation. +-if test "$gcc_cv_have_tls" = yes ; then +- case "${target}" in +- +- # For x86, we use slots in the TCB head for most of our TLS. +- # The setup of those slots in beginTransaction can afford to +- # use the global-dynamic model. +- i[456]86-*-linux* | x86_64-*-linux*) +- ;; +- +- *-*-linux*) +- XCFLAGS="${XCFLAGS} -ftls-model=initial-exec" +- ;; +- esac +-fi +- + # Map the target cpu to an ARCH sub-directory. At the same time, + # work out any special compilation flags as necessary. + case "${target_cpu}" in diff --git a/patches/gcc-8.5.0/0014-fix-gthr-weak-refs-for-libgcc.patch b/patches/gcc-8.5.0/0014-fix-gthr-weak-refs-for-libgcc.patch new file mode 100644 index 0000000..56291a2 --- /dev/null +++ b/patches/gcc-8.5.0/0014-fix-gthr-weak-refs-for-libgcc.patch @@ -0,0 +1,51 @@ +From 51a354a0fb54165d505bfed9819c0440027312d9 Mon Sep 17 00:00:00 2001 +From: Szabolcs Nagy +Date: Sun, 22 Sep 2019 23:04:48 +0000 +Subject: [PATCH] fix gthr weak refs for libgcc + +ideally gthr-posix.h should be fixed not to use weak refs for +single thread detection by default since that's unsafe. + +currently we have to opt out explicitly from the unsafe behaviour +in the configure machinery of each target lib that uses gthr and +musl missed libgcc previously. + +related bugs and discussions +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78017 +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87189 +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91737 +https://sourceware.org/bugzilla/show_bug.cgi?id=5784 +https://sourceware.org/ml/libc-alpha/2012-09/msg00192.html +https://sourceware.org/ml/libc-alpha/2019-08/msg00438.html +--- + libgcc/config.host | 7 +++++++ + libgcc/config/t-gthr-noweak | 2 ++ + 2 files changed, 9 insertions(+) + create mode 100644 libgcc/config/t-gthr-noweak + +diff --git a/libgcc/config.host b/libgcc/config.host +index 122113fc519..fe1b9ab93d5 100644 +--- a/libgcc/config.host ++++ b/libgcc/config.host +@@ -1500,3 +1500,10 @@ aarch64*-*-*) + tm_file="${tm_file} aarch64/value-unwind.h" + ;; + esac ++ ++case ${host} in ++*-*-musl*) ++ # The gthr weak references are unsafe with static linking ++ tmake_file="$tmake_file t-gthr-noweak" ++ ;; ++esac +diff --git a/libgcc/config/t-gthr-noweak b/libgcc/config/t-gthr-noweak +new file mode 100644 +index 00000000000..45a21e9361d +--- /dev/null ++++ b/libgcc/config/t-gthr-noweak +@@ -0,0 +1,2 @@ ++# Don't use weak references for single-thread detection ++HOST_LIBGCC2_CFLAGS += -DGTHREAD_USE_WEAK=0 +-- +2.17.1 + diff --git a/patches/gcc-8.5.0/0015-riscv-tls-copy-relocs.diff b/patches/gcc-8.5.0/0015-riscv-tls-copy-relocs.diff new file mode 100644 index 0000000..566be71 --- /dev/null +++ b/patches/gcc-8.5.0/0015-riscv-tls-copy-relocs.diff @@ -0,0 +1,16 @@ +diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c +index 677728e77ed..444d01e87ec 100644 +--- a/gcc/config/riscv/riscv.c ++++ b/gcc/config/riscv/riscv.c +@@ -1209,9 +1209,11 @@ riscv_legitimize_tls_address (rtx loc) + rtx dest, tp, tmp; + enum tls_model model = SYMBOL_REF_TLS_MODEL (loc); + ++#if 0 + /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */ + if (!flag_pic) + model = TLS_MODEL_LOCAL_EXEC; ++#endif + + switch (model) + { diff --git a/patches/gcc-8.5.0/0016-libstdc++-futex-time64.diff b/patches/gcc-8.5.0/0016-libstdc++-futex-time64.diff new file mode 100644 index 0000000..08f6261 --- /dev/null +++ b/patches/gcc-8.5.0/0016-libstdc++-futex-time64.diff @@ -0,0 +1,18 @@ +--- gcc-9.2.0/libstdc++-v3/src/c++11/futex.cc.orig 2020-01-20 14:55:05.507548334 -0500 ++++ gcc-9.2.0/libstdc++-v3/src/c++11/futex.cc 2020-01-20 14:56:52.458268068 -0500 +@@ -61,7 +61,15 @@ + struct timeval tv; + gettimeofday (&tv, NULL); + // Convert the absolute timeout value to a relative timeout ++#if defined(SYS_futex_time64) && SYS_futex_time64 != SYS_futex ++ struct ++ { ++ long tv_sec; ++ long tv_nsec; ++ } rt; ++#else + struct timespec rt; ++#endif + rt.tv_sec = __s.count() - tv.tv_sec; + rt.tv_nsec = __ns.count() - tv.tv_usec * 1000; + if (rt.tv_nsec < 0) diff --git a/patches/gcc-8.5.0/0018-m68k-sqrt.diff b/patches/gcc-8.5.0/0018-m68k-sqrt.diff new file mode 100644 index 0000000..5d46272 --- /dev/null +++ b/patches/gcc-8.5.0/0018-m68k-sqrt.diff @@ -0,0 +1,18 @@ +--- gcc-9.2.0.orig/gcc/config/m68k/m68k.md 2019-01-01 07:31:55.000000000 -0500 ++++ gcc-9.2.0/gcc/config/m68k/m68k.md 2020-07-01 15:57:20.528408009 -0400 +@@ -4126,13 +4126,13 @@ + (define_expand "sqrt2" + [(set (match_operand:FP 0 "nonimmediate_operand" "") + (sqrt:FP (match_operand:FP 1 "general_operand" "")))] +- "TARGET_HARD_FLOAT" ++ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU" + "") + + (define_insn "sqrt2_68881" + [(set (match_operand:FP 0 "nonimmediate_operand" "=f") + (sqrt:FP (match_operand:FP 1 "general_operand" "fm")))] +- "TARGET_68881" ++ "TARGET_68881 && TARGET_68040" + { + if (FP_REG_P (operands[1])) + return "fsqrt%.x %1,%0"; diff --git a/patches/gcc-8.5.0/0020-powerpcspe.diff b/patches/gcc-8.5.0/0020-powerpcspe.diff new file mode 100644 index 0000000..e494d68 --- /dev/null +++ b/patches/gcc-8.5.0/0020-powerpcspe.diff @@ -0,0 +1,11 @@ +--- gcc-8.3.0/gcc/config.gcc.orig 2021-06-23 21:46:44.400306941 -0400 ++++ gcc-8.3.0/gcc/config.gcc 2021-06-23 21:46:55.459427459 -0400 +@@ -2479,7 +2479,7 @@ + extra_options="${extra_options} rs6000/sysv4.opt rs6000/linux64.opt" + tmake_file="${tmake_file} rs6000/t-fprules rs6000/t-rtems rs6000/t-ppccomm" + ;; +-powerpc*-*-linux*spe*) ++powerpc*-*-linux*gnu*spe*) + tm_file="${tm_file} dbxelf.h elfos.h gnu-user.h freebsd-spec.h powerpcspe/sysv4.h" + extra_options="${extra_options} powerpcspe/sysv4.opt" + tmake_file="${tmake_file} powerpcspe/t-fprules powerpcspe/t-ppccomm" diff --git a/patches/gcc-8.5.0/0021-powerpcspe-musl-ldsoname.diff b/patches/gcc-8.5.0/0021-powerpcspe-musl-ldsoname.diff new file mode 100644 index 0000000..f88fd85 --- /dev/null +++ b/patches/gcc-8.5.0/0021-powerpcspe-musl-ldsoname.diff @@ -0,0 +1,22 @@ +--- gcc-8.5.0/gcc/config/rs6000/sysv4.h.orig 2021-07-05 12:56:18.398813835 -0400 ++++ gcc-8.5.0/gcc/config/rs6000/sysv4.h 2021-06-23 21:49:57.592408186 -0400 +@@ -793,7 +793,7 @@ + #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" + #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0" + #define MUSL_DYNAMIC_LINKER \ +- "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" ++ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float|mcpu=854*|mspe:-sf}.so.1" + #if DEFAULT_LIBC == LIBC_UCLIBC + #define CHOOSE_DYNAMIC_LINKER(G, U, M) \ + "%{mglibc:" G ";:%{mmusl:" M ";:" U "}}" +--- gcc-8.5.0/gcc/config/rs6000/linux64.h.orig 2021-07-05 12:54:24.704854044 -0400 ++++ gcc-8.5.0/gcc/config/rs6000/linux64.h 2021-07-05 12:56:50.010806923 -0400 +@@ -426,7 +426,7 @@ + #endif + + #define MUSL_DYNAMIC_LINKER32 \ +- "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" ++ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float|mcpu=854*|mspe:-sf}.so.1" + #define MUSL_DYNAMIC_LINKER64 \ + "/lib/ld-musl-powerpc64" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1" + diff --git a/patches/gcc-9.2.0/0001-ssp_nonshared.diff b/patches/gcc-9.2.0/0001-ssp_nonshared.diff new file mode 100644 index 0000000..b00ca70 --- /dev/null +++ b/patches/gcc-9.2.0/0001-ssp_nonshared.diff @@ -0,0 +1,14 @@ +diff --git a/gcc/gcc.c b/gcc/gcc.c +index 4f57765b012..d185c01b257 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -878,7 +878,8 @@ proper position among the other output files. */ + #ifndef LINK_SSP_SPEC + #ifdef TARGET_LIBC_PROVIDES_SSP + #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ +- "|fstack-protector-strong|fstack-protector-explicit:}" ++ "|fstack-protector-strong|fstack-protector-explicit" \ ++ ":-lssp_nonshared}" + #else + #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ + "|fstack-protector-strong|fstack-protector-explicit" \ diff --git a/patches/gcc-9.2.0/0002-posix_memalign.diff b/patches/gcc-9.2.0/0002-posix_memalign.diff new file mode 100644 index 0000000..7f67f3d --- /dev/null +++ b/patches/gcc-9.2.0/0002-posix_memalign.diff @@ -0,0 +1,30 @@ +diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h +index 09a4d1447cb..fecd9afdb2e 100644 +--- a/gcc/config/i386/pmm_malloc.h ++++ b/gcc/config/i386/pmm_malloc.h +@@ -27,12 +27,13 @@ + #include + + /* We can't depend on since the prototype of posix_memalign +- may not be visible. */ ++ may not be visible and we can't pollute the namespace either. */ + #ifndef __cplusplus +-extern int posix_memalign (void **, size_t, size_t); ++extern int _mm_posix_memalign (void **, size_t, size_t) + #else +-extern "C" int posix_memalign (void **, size_t, size_t) throw (); ++extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw () + #endif ++__asm__("posix_memalign"); + + static __inline void * + _mm_malloc (size_t __size, size_t __alignment) +@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment) + return malloc (__size); + if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4)) + __alignment = sizeof (void *); +- if (posix_memalign (&__ptr, __alignment, __size) == 0) ++ if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0) + return __ptr; + else + return NULL; diff --git a/patches/gcc-9.2.0/0003-libatomic-test-fix.diff b/patches/gcc-9.2.0/0003-libatomic-test-fix.diff new file mode 100644 index 0000000..71a19e8 --- /dev/null +++ b/patches/gcc-9.2.0/0003-libatomic-test-fix.diff @@ -0,0 +1,58 @@ +diff --git a/libatomic/testsuite/Makefile.am b/libatomic/testsuite/Makefile.am +index 41cfbc46e4b..16f82bdf691 100644 +--- a/libatomic/testsuite/Makefile.am ++++ b/libatomic/testsuite/Makefile.am +@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \ + _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = $(_RUNTEST) $(AM_RUNTESTFLAGS) ++ ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ +diff --git a/libatomic/testsuite/Makefile.in b/libatomic/testsuite/Makefile.in +index 73b9d521225..2dccc4c5d21 100644 +--- a/libatomic/testsuite/Makefile.in ++++ b/libatomic/testsuite/Makefile.in +@@ -277,6 +277,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = $(_RUNTEST) $(AM_RUNTESTFLAGS) ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -484,6 +485,10 @@ uninstall-am: + .PRECIOUS: Makefile + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Tell versions [3.59,3.63) of GNU make to not export all variables. + # Otherwise a system limit (for SysV at least) may be exceeded. + .NOEXPORT: +diff --git a/libatomic/testsuite/lib/libatomic.exp b/libatomic/testsuite/lib/libatomic.exp +index 38f3e5673e2..02ec2e8b48a 100644 +--- a/libatomic/testsuite/lib/libatomic.exp ++++ b/libatomic/testsuite/lib/libatomic.exp +@@ -77,6 +77,7 @@ proc libatomic_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -92,6 +93,8 @@ proc libatomic_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-9.2.0/0004-libgomp-test-fix.diff b/patches/gcc-9.2.0/0004-libgomp-test-fix.diff new file mode 100644 index 0000000..a560f7b --- /dev/null +++ b/patches/gcc-9.2.0/0004-libgomp-test-fix.diff @@ -0,0 +1,61 @@ +diff --git a/libgomp/testsuite/Makefile.am b/libgomp/testsuite/Makefile.am +index 2100f49e53b..fa25b3a0604 100644 +--- a/libgomp/testsuite/Makefile.am ++++ b/libgomp/testsuite/Makefile.am +@@ -12,6 +12,12 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir + ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Instead of directly in ../testsuite/libgomp-test-support.exp.in, the + # following variables have to be "routed through" this Makefile, for expansion + # of the several (Makefile) variables used therein. +diff --git a/libgomp/testsuite/Makefile.in b/libgomp/testsuite/Makefile.in +index 80315b15a7d..cdbf35695f7 100644 +--- a/libgomp/testsuite/Makefile.in ++++ b/libgomp/testsuite/Makefile.in +@@ -303,6 +303,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -464,6 +465,10 @@ uninstall-am: + .PRECIOUS: Makefile + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Instead of directly in ../testsuite/libgomp-test-support.exp.in, the + # following variables have to be "routed through" this Makefile, for expansion + # of the several (Makefile) variables used therein. +diff --git a/libgomp/testsuite/lib/libgomp.exp b/libgomp/testsuite/lib/libgomp.exp +index 14d9b5f1305..186b0ba0b57 100644 +--- a/libgomp/testsuite/lib/libgomp.exp ++++ b/libgomp/testsuite/lib/libgomp.exp +@@ -68,6 +68,7 @@ proc libgomp_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -90,6 +91,8 @@ proc libgomp_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-9.2.0/0005-libitm-test-fix.diff b/patches/gcc-9.2.0/0005-libitm-test-fix.diff new file mode 100644 index 0000000..3abddbc --- /dev/null +++ b/patches/gcc-9.2.0/0005-libitm-test-fix.diff @@ -0,0 +1,58 @@ +diff --git a/libitm/testsuite/Makefile.am b/libitm/testsuite/Makefile.am +index 41cfbc46e4b..16f82bdf691 100644 +--- a/libitm/testsuite/Makefile.am ++++ b/libitm/testsuite/Makefile.am +@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \ + _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = $(_RUNTEST) $(AM_RUNTESTFLAGS) ++ ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ +diff --git a/libitm/testsuite/Makefile.in b/libitm/testsuite/Makefile.in +index 991f02c0b3b..fa331cabfc4 100644 +--- a/libitm/testsuite/Makefile.in ++++ b/libitm/testsuite/Makefile.in +@@ -285,6 +285,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = $(_RUNTEST) $(AM_RUNTESTFLAGS) ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -492,6 +493,10 @@ uninstall-am: + .PRECIOUS: Makefile + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Tell versions [3.59,3.63) of GNU make to not export all variables. + # Otherwise a system limit (for SysV at least) may be exceeded. + .NOEXPORT: +diff --git a/libitm/testsuite/lib/libitm.exp b/libitm/testsuite/lib/libitm.exp +index b3d247b9f98..47c2cd55dac 100644 +--- a/libitm/testsuite/lib/libitm.exp ++++ b/libitm/testsuite/lib/libitm.exp +@@ -77,6 +77,7 @@ proc libitm_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -92,6 +93,8 @@ proc libitm_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-9.2.0/0006-libvtv-test-fix.diff b/patches/gcc-9.2.0/0006-libvtv-test-fix.diff new file mode 100644 index 0000000..060cc58 --- /dev/null +++ b/patches/gcc-9.2.0/0006-libvtv-test-fix.diff @@ -0,0 +1,58 @@ +diff --git a/libvtv/testsuite/Makefile.am b/libvtv/testsuite/Makefile.am +index 41cfbc46e4b..16f82bdf691 100644 +--- a/libvtv/testsuite/Makefile.am ++++ b/libvtv/testsuite/Makefile.am +@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \ + _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = $(_RUNTEST) $(AM_RUNTESTFLAGS) ++ ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ +diff --git a/libvtv/testsuite/Makefile.in b/libvtv/testsuite/Makefile.in +index e104f62c035..d7401b110ff 100644 +--- a/libvtv/testsuite/Makefile.in ++++ b/libvtv/testsuite/Makefile.in +@@ -280,6 +280,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = $(_RUNTEST) $(AM_RUNTESTFLAGS) ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -487,6 +488,10 @@ uninstall-am: + .PRECIOUS: Makefile + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Tell versions [3.59,3.63) of GNU make to not export all variables. + # Otherwise a system limit (for SysV at least) may be exceeded. + .NOEXPORT: +diff --git a/libvtv/testsuite/lib/libvtv.exp b/libvtv/testsuite/lib/libvtv.exp +index 4b71c9ce7bc..ef06e4a3199 100644 +--- a/libvtv/testsuite/lib/libvtv.exp ++++ b/libvtv/testsuite/lib/libvtv.exp +@@ -76,6 +76,7 @@ proc libvtv_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -91,6 +92,8 @@ proc libvtv_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-9.2.0/0007-j2.diff b/patches/gcc-9.2.0/0007-j2.diff new file mode 100644 index 0000000..71c4bac --- /dev/null +++ b/patches/gcc-9.2.0/0007-j2.diff @@ -0,0 +1,346 @@ +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 09fb9ecd2cd..79ac206d10e 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -536,7 +536,7 @@ s390*-*-*) + extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h" + ;; + # Note the 'l'; we need to be able to match e.g. "shle" or "shl". +-sh[123456789lbe]*-*-* | sh-*-*) ++sh[123456789lbej]*-*-* | sh-*-*) + cpu_type=sh + extra_options="${extra_options} fused-madd.opt" + extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o" +@@ -2834,18 +2834,18 @@ s390x-ibm-tpf*) + extra_options="${extra_options} s390/tpf.opt" + tmake_file="${tmake_file} s390/t-s390" + ;; +-sh-*-elf* | sh[12346l]*-*-elf* | \ +- sh-*-linux* | sh[2346lbe]*-*-linux* | \ ++sh-*-elf* | sh[12346lj]*-*-elf* | \ ++ sh-*-linux* | sh[2346lbej]*-*-linux* | \ + sh-*-netbsdelf* | shl*-*-netbsdelf*) + tmake_file="${tmake_file} sh/t-sh sh/t-elf" + if test x${with_endian} = x; then + case ${target} in +- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;; ++ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;; + shbe-*-* | sheb-*-*) with_endian=big,little ;; + sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;; + shl* | sh*-*-linux* | \ + sh-superh-elf) with_endian=little,big ;; +- sh[1234]*-*-*) with_endian=big ;; ++ sh[j1234]*-*-*) with_endian=big ;; + *) with_endian=big,little ;; + esac + fi +@@ -2912,6 +2912,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;; + sh2a*) sh_cpu_target=sh2a ;; + sh2e*) sh_cpu_target=sh2e ;; ++ shj2*) sh_cpu_target=shj2;; + sh2*) sh_cpu_target=sh2 ;; + *) sh_cpu_target=sh1 ;; + esac +@@ -2933,7 +2934,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \ + sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \ + sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \ +- sh3e | sh3 | sh2e | sh2 | sh1) ;; ++ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;; + "") sh_cpu_default=${sh_cpu_target} ;; + *) echo "with_cpu=$with_cpu not supported"; exit 1 ;; + esac +@@ -2942,9 +2943,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + case ${target} in + sh[1234]*) sh_multilibs=${sh_cpu_target} ;; + sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;; +- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;; ++ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;; + sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;; +- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;; ++ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;; + esac + if test x$with_fp = xno; then + sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`" +@@ -2959,7 +2960,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + m1 | m2 | m2e | m3 | m3e | \ + m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\ + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \ +- m2a | m2a-single | m2a-single-only | m2a-nofpu) ++ m2a | m2a-single | m2a-single-only | m2a-nofpu | \ ++ mj2) + # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition + # It is passed to MULTIILIB_OPTIONS verbatim. + TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}" +@@ -2976,7 +2978,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + done + TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'` + if test x${enable_incomplete_targets} = xyes ; then +- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1" ++ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1" + fi + tm_file="$tm_file ./sysroot-suffix.h" + tmake_file="$tmake_file t-sysroot-suffix" +@@ -4760,6 +4762,8 @@ case "${target}" in + ;; + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al) + ;; ++ mj2) ++ ;; + *) + echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2 + echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2 +@@ -4984,7 +4988,7 @@ case ${target} in + tmake_file="${cpu_type}/t-${cpu_type} ${tmake_file}" + ;; + +- sh[123456ble]*-*-* | sh-*-*) ++ sh[123456blej]*-*-* | sh-*-*) + c_target_objs="${c_target_objs} sh-c.o" + cxx_target_objs="${cxx_target_objs} sh-c.o" + ;; +diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c +index 8dc79a764df..36683614277 100644 +--- a/gcc/config/sh/sh.c ++++ b/gcc/config/sh/sh.c +@@ -686,6 +686,7 @@ parse_validate_atomic_model_option (const char* str) + model_names[sh_atomic_model::hard_llcs] = "hard-llcs"; + model_names[sh_atomic_model::soft_tcb] = "soft-tcb"; + model_names[sh_atomic_model::soft_imask] = "soft-imask"; ++ model_names[sh_atomic_model::hard_cas] = "hard-cas"; + + const char* model_cdef_names[sh_atomic_model::num_models]; + model_cdef_names[sh_atomic_model::none] = "NONE"; +@@ -693,6 +694,7 @@ parse_validate_atomic_model_option (const char* str) + model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS"; + model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB"; + model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK"; ++ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS"; + + sh_atomic_model ret; + ret.type = sh_atomic_model::none; +@@ -771,6 +773,9 @@ got_mode_name:; + if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE) + err_ret ("cannot use atomic model %s in user mode", ret.name); + ++ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2) ++ err_ret ("atomic model %s is only available J2 targets", ret.name); ++ + return ret; + + #undef err_ret +@@ -827,6 +832,8 @@ sh_option_override (void) + sh_cpu = PROCESSOR_SH2E; + if (TARGET_SH2A) + sh_cpu = PROCESSOR_SH2A; ++ if (TARGET_SHJ2) ++ sh_cpu = PROCESSOR_SHJ2; + if (TARGET_SH3) + sh_cpu = PROCESSOR_SH3; + if (TARGET_SH3E) +diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h +index 0204872eae7..30416a34e30 100644 +--- a/gcc/config/sh/sh.h ++++ b/gcc/config/sh/sh.h +@@ -83,6 +83,7 @@ extern int code_for_indirect_jump_scratch; + #define SUPPORT_SH4_SINGLE 1 + #define SUPPORT_SH2A 1 + #define SUPPORT_SH2A_SINGLE 1 ++#define SUPPORT_SHJ2 1 + #endif + + #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) +@@ -115,6 +116,7 @@ extern int code_for_indirect_jump_scratch; + #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) + #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) + #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) ++#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2) + + #if SUPPORT_SH1 + #define SUPPORT_SH2 1 +@@ -122,6 +124,7 @@ extern int code_for_indirect_jump_scratch; + #if SUPPORT_SH2 + #define SUPPORT_SH3 1 + #define SUPPORT_SH2A_NOFPU 1 ++#define SUPPORT_SHJ2 1 + #endif + #if SUPPORT_SH3 + #define SUPPORT_SH4_NOFPU 1 +@@ -154,7 +157,7 @@ extern int code_for_indirect_jump_scratch; + #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ + | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ + | MASK_HARD_SH4 | MASK_FPU_SINGLE \ +- | MASK_FPU_SINGLE_ONLY) ++ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2) + + /* This defaults us to big-endian. */ + #ifndef TARGET_ENDIAN_DEFAULT +@@ -229,7 +232,8 @@ extern int code_for_indirect_jump_scratch; + %{m2a-single:--isa=sh2a} \ + %{m2a-single-only:--isa=sh2a} \ + %{m2a-nofpu:--isa=sh2a-nofpu} \ +-%{m4al:-dsp}" ++%{m4al:-dsp} \ ++%{mj2:-isa=j2}" + + #define ASM_SPEC SH_ASM_SPEC + +@@ -345,6 +349,7 @@ struct sh_atomic_model + hard_llcs, + soft_tcb, + soft_imask, ++ hard_cas, + + num_models + }; +@@ -388,6 +393,9 @@ extern const sh_atomic_model& selected_atomic_model (void); + #define TARGET_ATOMIC_SOFT_IMASK \ + (selected_atomic_model ().type == sh_atomic_model::soft_imask) + ++#define TARGET_ATOMIC_HARD_CAS \ ++ (selected_atomic_model ().type == sh_atomic_model::hard_cas) ++ + #endif // __cplusplus + + #define SUBTARGET_OVERRIDE_OPTIONS (void) 0 +@@ -1521,7 +1529,7 @@ extern bool current_function_interrupt; + + /* Nonzero if the target supports dynamic shift instructions + like shad and shld. */ +-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) ++#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2) + + /* The cost of using the dynamic shift insns (shad, shld) are the same + if they are available. If they are not available a library function will +@@ -1784,6 +1792,7 @@ enum processor_type { + PROCESSOR_SH2, + PROCESSOR_SH2E, + PROCESSOR_SH2A, ++ PROCESSOR_SHJ2, + PROCESSOR_SH3, + PROCESSOR_SH3E, + PROCESSOR_SH4, +diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt +index 8eb1a4e121a..9c28ed6b5c0 100644 +--- a/gcc/config/sh/sh.opt ++++ b/gcc/config/sh/sh.opt +@@ -65,6 +65,10 @@ m2e + Target RejectNegative Condition(SUPPORT_SH2E) + Generate SH2e code. + ++mj2 ++Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2) ++Generate J2 code. ++ + m3 + Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) + Generate SH3 code. +diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md +index 691d9287101..3ffb099195d 100644 +--- a/gcc/config/sh/sync.md ++++ b/gcc/config/sh/sync.md +@@ -240,6 +240,9 @@ + || (TARGET_SH4A && mode == SImode && !TARGET_ATOMIC_STRICT)) + atomic_insn = gen_atomic_compare_and_swap_hard (old_val, mem, + exp_val, new_val); ++ else if (TARGET_ATOMIC_HARD_CAS && mode == SImode) ++ atomic_insn = gen_atomic_compare_and_swap_cas (old_val, mem, ++ exp_val, new_val); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic_compare_and_swap_soft_gusa (old_val, mem, + exp_val, new_val); +@@ -306,6 +309,57 @@ + } + [(set_attr "length" "14")]) + ++(define_expand "atomic_compare_and_swapsi_cas" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "r")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{ ++ rtx mem = gen_rtx_REG (SImode, 0); ++ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0))); ++ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_insn "shj2_cas" ++ [(set (match_operand:SI 0 "register_operand" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "register_operand" "=r") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "0")] ++ UNSPECV_CMPXCHG_1)) ++ (set (reg:SI T_REG) ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))] ++ "TARGET_ATOMIC_HARD_CAS" ++ "cas.l %2,%0,@%1" ++ [(set_attr "length" "2")] ++) ++ ++(define_expand "atomic_compare_and_swapqi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ ++(define_expand "atomic_compare_and_swaphi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ + ;; The QIHImode llcs patterns modify the address register of the memory + ;; operand. In order to express that, we have to open code the memory + ;; operand. Initially the insn is expanded like every other atomic insn +diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh +index e1a398319d5..19a6f3f7ea8 100644 +--- a/gcc/config/sh/t-sh ++++ b/gcc/config/sh/t-sh +@@ -50,7 +50,8 @@ MULTILIB_MATCHES = $(shell \ + m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \ + m2a-single,m2a-single-only \ + m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \ +- m4,m4-100,m4-200,m4-300,m4a; do \ ++ m4,m4-100,m4-200,m4-300,m4a \ ++ mj2; do \ + subst= ; \ + for lib in `echo $$abi|tr , ' '` ; do \ + if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \ +@@ -63,9 +64,9 @@ MULTILIB_MATCHES = $(shell \ + + # SH1 and SH2A support big endian only. + ifeq ($(DEFAULT_ENDIAN),ml) +-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + else +-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + endif + + MULTILIB_OSDIRNAMES = \ +@@ -87,7 +88,8 @@ MULTILIB_OSDIRNAMES = \ + m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \ + m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \ + m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \ +- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al ++ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \ ++ mj2=!j2 + + $(out_object_file): gt-sh.h + gt-sh.h : s-gtype ; @true diff --git a/patches/gcc-9.2.0/0008-s390x-muslldso.diff b/patches/gcc-9.2.0/0008-s390x-muslldso.diff new file mode 100644 index 0000000..d385f25 --- /dev/null +++ b/patches/gcc-9.2.0/0008-s390x-muslldso.diff @@ -0,0 +1,14 @@ +diff --git a/gcc/config/s390/linux.h b/gcc/config/s390/linux.h +index f76986acdab..5f6b7041f0f 100644 +--- a/gcc/config/s390/linux.h ++++ b/gcc/config/s390/linux.h +@@ -75,6 +75,9 @@ along with GCC; see the file COPYING3. If not see + #define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1" + #define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1" + ++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-s390.so.1" ++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-s390x.so.1" ++ + #undef LINK_SPEC + #define LINK_SPEC \ + "%{m31:-m elf_s390}%{m64:-m elf64_s390} \ diff --git a/patches/gcc-9.2.0/0009-microblaze-pr65649.diff b/patches/gcc-9.2.0/0009-microblaze-pr65649.diff new file mode 100644 index 0000000..e733b5c --- /dev/null +++ b/patches/gcc-9.2.0/0009-microblaze-pr65649.diff @@ -0,0 +1,22 @@ +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 55c1becf975..45395ab86f1 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2476,7 +2476,7 @@ print_operand (FILE * file, rtx op, int letter) + unsigned long value_long; + REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), + value_long); +- fprintf (file, HOST_WIDE_INT_PRINT_HEX, value_long); ++ fprintf (file, "0x%lx", value_long); + } + else + { +@@ -2535,7 +2535,7 @@ print_operand (FILE * file, rtx op, int letter) + print_operand_address (file, XEXP (op, 0)); + } + else if (letter == 'm') +- fprintf (file, HOST_WIDE_INT_PRINT_DEC, (1L << INTVAL (op))); ++ fprintf (file, "%ld", (1L << INTVAL (op))); + else + output_addr_const (file, op); + } diff --git a/patches/gcc-9.2.0/0010-ldbl128-config.diff b/patches/gcc-9.2.0/0010-ldbl128-config.diff new file mode 100644 index 0000000..04b88a0 --- /dev/null +++ b/patches/gcc-9.2.0/0010-ldbl128-config.diff @@ -0,0 +1,63 @@ +diff --git a/gcc/configure b/gcc/configure +index 3dcf7752b7f..78aaa36dce6 100755 +--- a/gcc/configure ++++ b/gcc/configure +@@ -29356,6 +29356,15 @@ if test "${with_long_double_128+set}" = set; then : + withval=$with_long_double_128; gcc_cv_target_ldbl128="$with_long_double_128" + else + ++ case "$target" in ++ s390*-*-linux-musl*) ++ gcc_cv_target_ldbl128=yes ++ ;; ++ powerpc*-*-linux-musl*) ++ gcc_cv_target_ldbl128=no ++ ;; ++ *) ++ + if test $glibc_version_major -gt 2 \ + || ( test $glibc_version_major -eq 2 && test $glibc_version_minor -ge 4 ); then : + gcc_cv_target_ldbl128=yes +@@ -29367,6 +29376,10 @@ else + && gcc_cv_target_ldbl128=yes + + fi ++ ++ ;; ++ esac ++ + fi + + ;; +diff --git a/gcc/configure.ac b/gcc/configure.ac +index 51f520c1508..a6498239698 100644 +--- a/gcc/configure.ac ++++ b/gcc/configure.ac +@@ -6020,13 +6020,25 @@ case "$target" in + AC_ARG_WITH(long-double-128, + [AS_HELP_STRING([--with-long-double-128], + [use 128-bit long double by default])], +- gcc_cv_target_ldbl128="$with_long_double_128", ++ gcc_cv_target_ldbl128="$with_long_double_128", [ ++ case "$target" in ++ s390*-*-linux-musl*) ++ gcc_cv_target_ldbl128=yes ++ ;; ++ powerpc*-*-linux-musl*) ++ gcc_cv_target_ldbl128=no ++ ;; ++ *)] + [GCC_GLIBC_VERSION_GTE_IFELSE([2], [4], [gcc_cv_target_ldbl128=yes], [ + [gcc_cv_target_ldbl128=no + grep '^[ ]*#[ ]*define[ ][ ]*__LONG_DOUBLE_MATH_OPTIONAL' \ + $target_header_dir/bits/wordsize.h > /dev/null 2>&1 \ + && gcc_cv_target_ldbl128=yes +- ]])]) ++ ]])] ++ [ ++ ;; ++ esac ++ ]) + ;; + esac + if test x$gcc_cv_target_ldbl128 = xyes; then diff --git a/patches/gcc-9.2.0/0011-m68k.diff b/patches/gcc-9.2.0/0011-m68k.diff new file mode 100644 index 0000000..79a15d1 --- /dev/null +++ b/patches/gcc-9.2.0/0011-m68k.diff @@ -0,0 +1,27 @@ +diff --git a/gcc/config/m68k/linux.h b/gcc/config/m68k/linux.h +index ebdf0281071..beef554b31c 100644 +--- a/gcc/config/m68k/linux.h ++++ b/gcc/config/m68k/linux.h +@@ -73,6 +73,9 @@ along with GCC; see the file COPYING3. If not see + + #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" + ++#undef MUSL_DYNAMIC_LINKER ++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-m68k.so.1" ++ + #undef LINK_SPEC + #define LINK_SPEC "-m m68kelf %{shared} \ + %{!shared: \ +diff --git a/libgcc/config/m68k/linux-unwind.h b/libgcc/config/m68k/linux-unwind.h +index fbe0d4748ba..57c354ee9b4 100644 +--- a/libgcc/config/m68k/linux-unwind.h ++++ b/libgcc/config/m68k/linux-unwind.h +@@ -37,7 +37,7 @@ struct uw_ucontext { + stack_t uc_stack; + mcontext_t uc_mcontext; + unsigned long uc_filler[80]; +- __sigset_t uc_sigmask; ++ sigset_t uc_sigmask; + }; + + #define MD_FALLBACK_FRAME_STATE_FOR m68k_fallback_frame_state diff --git a/patches/gcc-9.2.0/0012-static-pie.diff b/patches/gcc-9.2.0/0012-static-pie.diff new file mode 100644 index 0000000..400d7a1 --- /dev/null +++ b/patches/gcc-9.2.0/0012-static-pie.diff @@ -0,0 +1,86 @@ +diff --git a/gcc/common.opt b/gcc/common.opt +index d342c4f3749..2aae4a3cefb 100644 +--- a/gcc/common.opt ++++ b/gcc/common.opt +@@ -3287,11 +3287,11 @@ Driver + + no-pie + Driver RejectNegative Negative(shared) +-Don't create a dynamically linked position independent executable. ++Don't create a position independent executable. + + pie + Driver RejectNegative Negative(no-pie) +-Create a dynamically linked position independent executable. ++Create a position independent executable. + + static-pie + Driver RejectNegative Negative(pie) +diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h +index 055a4f0afec..7a671c6a49c 100644 +--- a/gcc/config/gnu-user.h ++++ b/gcc/config/gnu-user.h +@@ -51,13 +51,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define GNU_USER_TARGET_STARTFILE_SPEC \ + "%{shared:; \ + pg|p|profile:%{static-pie:grcrt1.o%s;:gcrt1.o%s}; \ +- static:crt1.o%s; \ +- static-pie:rcrt1.o%s; \ ++ static|static-pie:%{" PIE_SPEC ":rcrt1.o%s;:crt1.o%s}; \ + " PIE_SPEC ":Scrt1.o%s; \ + :crt1.o%s} " \ + GNU_USER_TARGET_CRTI " \ +- %{static:crtbeginT.o%s; \ +- shared|static-pie|" PIE_SPEC ":crtbeginS.o%s; \ ++ %{shared|" PIE_SPEC ":crtbeginS.o%s; \ ++ static:crtbeginT.o%s; \ + :crtbegin.o%s} \ + %{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_start_preinit.o%s; \ +@@ -76,8 +75,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + "%{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_end_preinit.o%s; \ + fvtable-verify=std:vtv_end.o%s} \ +- %{static:crtend.o%s; \ +- shared|static-pie|" PIE_SPEC ":crtendS.o%s; \ ++ %{shared|" PIE_SPEC ":crtendS.o%s; \ + :crtend.o%s} " \ + GNU_USER_TARGET_CRTN " " \ + CRTOFFLOADEND +@@ -106,7 +104,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define LIB_SPEC GNU_USER_TARGET_LIB_SPEC + + #if defined(HAVE_LD_EH_FRAME_HDR) +-#define LINK_EH_SPEC "%{!static|static-pie:--eh-frame-hdr} " ++#define LINK_EH_SPEC "%{!static|" PIE_SPEC ":--eh-frame-hdr} " + #endif + + #define GNU_USER_TARGET_LINK_GCC_C_SEQUENCE_SPEC \ +diff --git a/gcc/gcc.c b/gcc/gcc.c +index d185c01b257..5d3f81c5fc5 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -908,7 +908,7 @@ proper position among the other output files. */ + #define NO_FPIE_AND_FPIC_SPEC NO_FPIE_SPEC "|" NO_FPIC_SPEC + #define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;" + #else +-#define PIE_SPEC "pie" ++#define PIE_SPEC "pie|static-pie" + #define FPIE1_SPEC "fpie" + #define NO_FPIE1_SPEC FPIE1_SPEC ":;" + #define FPIE2_SPEC "fPIE" +@@ -932,12 +932,12 @@ proper position among the other output files. */ + #ifndef LINK_PIE_SPEC + #ifdef HAVE_LD_PIE + #ifndef LD_PIE_SPEC +-#define LD_PIE_SPEC "-pie" ++#define LD_PIE_SPEC "-pie %{static-pie:-static} %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}" + #endif + #else + #define LD_PIE_SPEC "" + #endif +-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} " ++#define LINK_PIE_SPEC "%{shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} " + #endif + + #ifndef LINK_BUILDID_SPEC diff --git a/patches/gcc-9.2.0/0013-invalid-tls-model.diff b/patches/gcc-9.2.0/0013-invalid-tls-model.diff new file mode 100644 index 0000000..ac2d56b --- /dev/null +++ b/patches/gcc-9.2.0/0013-invalid-tls-model.diff @@ -0,0 +1,28 @@ +diff --git a/libgomp/configure.tgt b/libgomp/configure.tgt +index b88bf72fe3d..747d0485bf8 100644 +--- a/libgomp/configure.tgt ++++ b/libgomp/configure.tgt +@@ -17,6 +17,9 @@ if test $gcc_cv_have_tls = yes ; then + *-*-k*bsd*-gnu*) + ;; + ++ *-*-musl*) ++ ;; ++ + *-*-linux* | *-*-gnu*) + XCFLAGS="${XCFLAGS} -ftls-model=initial-exec -DUSING_INITIAL_EXEC_TLS" + ;; +diff --git a/libitm/configure.tgt b/libitm/configure.tgt +index 4c0b602034b..65e1c83550a 100644 +--- a/libitm/configure.tgt ++++ b/libitm/configure.tgt +@@ -31,6 +31,9 @@ + if test "$gcc_cv_have_tls" = yes ; then + case "${target}" in + ++ *-*-musl*) ++ ;; ++ + # For x86, we use slots in the TCB head for most of our TLS. + # The setup of those slots in beginTransaction can afford to + # use the global-dynamic model. diff --git a/patches/gcc-9.2.0/0014-fix-gthr-weak-refs-for-libgcc.patch b/patches/gcc-9.2.0/0014-fix-gthr-weak-refs-for-libgcc.patch new file mode 100644 index 0000000..56291a2 --- /dev/null +++ b/patches/gcc-9.2.0/0014-fix-gthr-weak-refs-for-libgcc.patch @@ -0,0 +1,51 @@ +From 51a354a0fb54165d505bfed9819c0440027312d9 Mon Sep 17 00:00:00 2001 +From: Szabolcs Nagy +Date: Sun, 22 Sep 2019 23:04:48 +0000 +Subject: [PATCH] fix gthr weak refs for libgcc + +ideally gthr-posix.h should be fixed not to use weak refs for +single thread detection by default since that's unsafe. + +currently we have to opt out explicitly from the unsafe behaviour +in the configure machinery of each target lib that uses gthr and +musl missed libgcc previously. + +related bugs and discussions +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78017 +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87189 +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91737 +https://sourceware.org/bugzilla/show_bug.cgi?id=5784 +https://sourceware.org/ml/libc-alpha/2012-09/msg00192.html +https://sourceware.org/ml/libc-alpha/2019-08/msg00438.html +--- + libgcc/config.host | 7 +++++++ + libgcc/config/t-gthr-noweak | 2 ++ + 2 files changed, 9 insertions(+) + create mode 100644 libgcc/config/t-gthr-noweak + +diff --git a/libgcc/config.host b/libgcc/config.host +index 122113fc519..fe1b9ab93d5 100644 +--- a/libgcc/config.host ++++ b/libgcc/config.host +@@ -1500,3 +1500,10 @@ aarch64*-*-*) + tm_file="${tm_file} aarch64/value-unwind.h" + ;; + esac ++ ++case ${host} in ++*-*-musl*) ++ # The gthr weak references are unsafe with static linking ++ tmake_file="$tmake_file t-gthr-noweak" ++ ;; ++esac +diff --git a/libgcc/config/t-gthr-noweak b/libgcc/config/t-gthr-noweak +new file mode 100644 +index 00000000000..45a21e9361d +--- /dev/null ++++ b/libgcc/config/t-gthr-noweak +@@ -0,0 +1,2 @@ ++# Don't use weak references for single-thread detection ++HOST_LIBGCC2_CFLAGS += -DGTHREAD_USE_WEAK=0 +-- +2.17.1 + diff --git a/patches/gcc-9.2.0/0015-riscv-tls-copy-relocs.diff b/patches/gcc-9.2.0/0015-riscv-tls-copy-relocs.diff new file mode 100644 index 0000000..566be71 --- /dev/null +++ b/patches/gcc-9.2.0/0015-riscv-tls-copy-relocs.diff @@ -0,0 +1,16 @@ +diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c +index 677728e77ed..444d01e87ec 100644 +--- a/gcc/config/riscv/riscv.c ++++ b/gcc/config/riscv/riscv.c +@@ -1209,9 +1209,11 @@ riscv_legitimize_tls_address (rtx loc) + rtx dest, tp, tmp; + enum tls_model model = SYMBOL_REF_TLS_MODEL (loc); + ++#if 0 + /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */ + if (!flag_pic) + model = TLS_MODEL_LOCAL_EXEC; ++#endif + + switch (model) + { diff --git a/patches/gcc-9.2.0/0016-libstdc++-futex-time64.diff b/patches/gcc-9.2.0/0016-libstdc++-futex-time64.diff new file mode 100644 index 0000000..08f6261 --- /dev/null +++ b/patches/gcc-9.2.0/0016-libstdc++-futex-time64.diff @@ -0,0 +1,18 @@ +--- gcc-9.2.0/libstdc++-v3/src/c++11/futex.cc.orig 2020-01-20 14:55:05.507548334 -0500 ++++ gcc-9.2.0/libstdc++-v3/src/c++11/futex.cc 2020-01-20 14:56:52.458268068 -0500 +@@ -61,7 +61,15 @@ + struct timeval tv; + gettimeofday (&tv, NULL); + // Convert the absolute timeout value to a relative timeout ++#if defined(SYS_futex_time64) && SYS_futex_time64 != SYS_futex ++ struct ++ { ++ long tv_sec; ++ long tv_nsec; ++ } rt; ++#else + struct timespec rt; ++#endif + rt.tv_sec = __s.count() - tv.tv_sec; + rt.tv_nsec = __ns.count() - tv.tv_usec * 1000; + if (rt.tv_nsec < 0) diff --git a/patches/gcc-9.2.0/0017-pr93402.diff b/patches/gcc-9.2.0/0017-pr93402.diff new file mode 100644 index 0000000..c985fb6 --- /dev/null +++ b/patches/gcc-9.2.0/0017-pr93402.diff @@ -0,0 +1,45 @@ +2020-01-23 Jakub Jelinek + + PR rtl-optimization/93402 + * postreload.c (reload_combine_recognize_pattern): Don't try to adjust + USE insns. + + * gcc.c-torture/execute/pr93402.c: New test. + +--- a/gcc/postreload.c.jj 2020-01-12 11:54:36.000000000 +0100 ++++ b/gcc/postreload.c 2020-01-23 17:23:25.359929516 +0100 +@@ -1078,6 +1078,10 @@ reload_combine_recognize_pattern (rtx_in + struct reg_use *use = reg_state[regno].reg_use + i; + if (GET_MODE (*use->usep) != mode) + return false; ++ /* Don't try to adjust (use (REGX)). */ ++ if (GET_CODE (PATTERN (use->insn)) == USE ++ && &XEXP (PATTERN (use->insn), 0) == use->usep) ++ return false; + } + + /* Look for (set (REGX) (CONST_INT)) +--- a/gcc/testsuite/gcc.c-torture/execute/pr93402.c.jj 2020-01-23 17:25:46.496803852 +0100 ++++ b/gcc/testsuite/gcc.c-torture/execute/pr93402.c 2020-01-23 17:25:05.221425501 +0100 +@@ -0,0 +1,21 @@ ++/* PR rtl-optimization/93402 */ ++ ++struct S { unsigned int a; unsigned long long b; }; ++ ++__attribute__((noipa)) struct S ++foo (unsigned long long x) ++{ ++ struct S ret; ++ ret.a = 0; ++ ret.b = x * 11111111111ULL + 111111111111ULL; ++ return ret; ++} ++ ++int ++main () ++{ ++ struct S a = foo (1); ++ if (a.a != 0 || a.b != 122222222222ULL) ++ __builtin_abort (); ++ return 0; ++} diff --git a/patches/gcc-9.2.0/0018-m68k-sqrt.diff b/patches/gcc-9.2.0/0018-m68k-sqrt.diff new file mode 100644 index 0000000..5d46272 --- /dev/null +++ b/patches/gcc-9.2.0/0018-m68k-sqrt.diff @@ -0,0 +1,18 @@ +--- gcc-9.2.0.orig/gcc/config/m68k/m68k.md 2019-01-01 07:31:55.000000000 -0500 ++++ gcc-9.2.0/gcc/config/m68k/m68k.md 2020-07-01 15:57:20.528408009 -0400 +@@ -4126,13 +4126,13 @@ + (define_expand "sqrt2" + [(set (match_operand:FP 0 "nonimmediate_operand" "") + (sqrt:FP (match_operand:FP 1 "general_operand" "")))] +- "TARGET_HARD_FLOAT" ++ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU" + "") + + (define_insn "sqrt2_68881" + [(set (match_operand:FP 0 "nonimmediate_operand" "=f") + (sqrt:FP (match_operand:FP 1 "general_operand" "fm")))] +- "TARGET_68881" ++ "TARGET_68881 && TARGET_68040" + { + if (FP_REG_P (operands[1])) + return "fsqrt%.x %1,%0"; diff --git a/patches/gcc-9.2.0/0019-broken-builtin-memcmp.diff b/patches/gcc-9.2.0/0019-broken-builtin-memcmp.diff new file mode 100644 index 0000000..84d8b3a --- /dev/null +++ b/patches/gcc-9.2.0/0019-broken-builtin-memcmp.diff @@ -0,0 +1,11 @@ +diff -ur gcc-9.3.0.orig/gcc/builtins.c gcc-9.3.0/gcc/builtins.c +--- gcc-9.3.0.orig/gcc/builtins.c 2020-03-12 11:07:21.000000000 +0000 ++++ gcc-9.3.0/gcc/builtins.c 2020-09-23 22:16:54.815251679 +0000 +@@ -4658,6 +4658,7 @@ + static rtx + expand_builtin_memcmp (tree exp, rtx target, bool result_eq) + { ++ return NULL_RTX; + if (!validate_arglist (exp, + POINTER_TYPE, POINTER_TYPE, INTEGER_TYPE, VOID_TYPE)) + return NULL_RTX; diff --git a/patches/gcc-9.4.0/0001-ssp_nonshared.diff b/patches/gcc-9.4.0/0001-ssp_nonshared.diff new file mode 100644 index 0000000..b00ca70 --- /dev/null +++ b/patches/gcc-9.4.0/0001-ssp_nonshared.diff @@ -0,0 +1,14 @@ +diff --git a/gcc/gcc.c b/gcc/gcc.c +index 4f57765b012..d185c01b257 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -878,7 +878,8 @@ proper position among the other output files. */ + #ifndef LINK_SSP_SPEC + #ifdef TARGET_LIBC_PROVIDES_SSP + #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ +- "|fstack-protector-strong|fstack-protector-explicit:}" ++ "|fstack-protector-strong|fstack-protector-explicit" \ ++ ":-lssp_nonshared}" + #else + #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ + "|fstack-protector-strong|fstack-protector-explicit" \ diff --git a/patches/gcc-9.4.0/0002-posix_memalign.diff b/patches/gcc-9.4.0/0002-posix_memalign.diff new file mode 100644 index 0000000..7f67f3d --- /dev/null +++ b/patches/gcc-9.4.0/0002-posix_memalign.diff @@ -0,0 +1,30 @@ +diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h +index 09a4d1447cb..fecd9afdb2e 100644 +--- a/gcc/config/i386/pmm_malloc.h ++++ b/gcc/config/i386/pmm_malloc.h +@@ -27,12 +27,13 @@ + #include + + /* We can't depend on since the prototype of posix_memalign +- may not be visible. */ ++ may not be visible and we can't pollute the namespace either. */ + #ifndef __cplusplus +-extern int posix_memalign (void **, size_t, size_t); ++extern int _mm_posix_memalign (void **, size_t, size_t) + #else +-extern "C" int posix_memalign (void **, size_t, size_t) throw (); ++extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw () + #endif ++__asm__("posix_memalign"); + + static __inline void * + _mm_malloc (size_t __size, size_t __alignment) +@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment) + return malloc (__size); + if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4)) + __alignment = sizeof (void *); +- if (posix_memalign (&__ptr, __alignment, __size) == 0) ++ if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0) + return __ptr; + else + return NULL; diff --git a/patches/gcc-9.4.0/0003-libatomic-test-fix.diff b/patches/gcc-9.4.0/0003-libatomic-test-fix.diff new file mode 100644 index 0000000..71a19e8 --- /dev/null +++ b/patches/gcc-9.4.0/0003-libatomic-test-fix.diff @@ -0,0 +1,58 @@ +diff --git a/libatomic/testsuite/Makefile.am b/libatomic/testsuite/Makefile.am +index 41cfbc46e4b..16f82bdf691 100644 +--- a/libatomic/testsuite/Makefile.am ++++ b/libatomic/testsuite/Makefile.am +@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \ + _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = $(_RUNTEST) $(AM_RUNTESTFLAGS) ++ ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ +diff --git a/libatomic/testsuite/Makefile.in b/libatomic/testsuite/Makefile.in +index 73b9d521225..2dccc4c5d21 100644 +--- a/libatomic/testsuite/Makefile.in ++++ b/libatomic/testsuite/Makefile.in +@@ -277,6 +277,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = $(_RUNTEST) $(AM_RUNTESTFLAGS) ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -484,6 +485,10 @@ uninstall-am: + .PRECIOUS: Makefile + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Tell versions [3.59,3.63) of GNU make to not export all variables. + # Otherwise a system limit (for SysV at least) may be exceeded. + .NOEXPORT: +diff --git a/libatomic/testsuite/lib/libatomic.exp b/libatomic/testsuite/lib/libatomic.exp +index 38f3e5673e2..02ec2e8b48a 100644 +--- a/libatomic/testsuite/lib/libatomic.exp ++++ b/libatomic/testsuite/lib/libatomic.exp +@@ -77,6 +77,7 @@ proc libatomic_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -92,6 +93,8 @@ proc libatomic_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-9.4.0/0004-libgomp-test-fix.diff b/patches/gcc-9.4.0/0004-libgomp-test-fix.diff new file mode 100644 index 0000000..a560f7b --- /dev/null +++ b/patches/gcc-9.4.0/0004-libgomp-test-fix.diff @@ -0,0 +1,61 @@ +diff --git a/libgomp/testsuite/Makefile.am b/libgomp/testsuite/Makefile.am +index 2100f49e53b..fa25b3a0604 100644 +--- a/libgomp/testsuite/Makefile.am ++++ b/libgomp/testsuite/Makefile.am +@@ -12,6 +12,12 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir + ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Instead of directly in ../testsuite/libgomp-test-support.exp.in, the + # following variables have to be "routed through" this Makefile, for expansion + # of the several (Makefile) variables used therein. +diff --git a/libgomp/testsuite/Makefile.in b/libgomp/testsuite/Makefile.in +index 80315b15a7d..cdbf35695f7 100644 +--- a/libgomp/testsuite/Makefile.in ++++ b/libgomp/testsuite/Makefile.in +@@ -303,6 +303,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -464,6 +465,10 @@ uninstall-am: + .PRECIOUS: Makefile + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Instead of directly in ../testsuite/libgomp-test-support.exp.in, the + # following variables have to be "routed through" this Makefile, for expansion + # of the several (Makefile) variables used therein. +diff --git a/libgomp/testsuite/lib/libgomp.exp b/libgomp/testsuite/lib/libgomp.exp +index 14d9b5f1305..186b0ba0b57 100644 +--- a/libgomp/testsuite/lib/libgomp.exp ++++ b/libgomp/testsuite/lib/libgomp.exp +@@ -68,6 +68,7 @@ proc libgomp_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -90,6 +91,8 @@ proc libgomp_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-9.4.0/0005-libitm-test-fix.diff b/patches/gcc-9.4.0/0005-libitm-test-fix.diff new file mode 100644 index 0000000..3abddbc --- /dev/null +++ b/patches/gcc-9.4.0/0005-libitm-test-fix.diff @@ -0,0 +1,58 @@ +diff --git a/libitm/testsuite/Makefile.am b/libitm/testsuite/Makefile.am +index 41cfbc46e4b..16f82bdf691 100644 +--- a/libitm/testsuite/Makefile.am ++++ b/libitm/testsuite/Makefile.am +@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \ + _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = $(_RUNTEST) $(AM_RUNTESTFLAGS) ++ ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ +diff --git a/libitm/testsuite/Makefile.in b/libitm/testsuite/Makefile.in +index 991f02c0b3b..fa331cabfc4 100644 +--- a/libitm/testsuite/Makefile.in ++++ b/libitm/testsuite/Makefile.in +@@ -285,6 +285,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = $(_RUNTEST) $(AM_RUNTESTFLAGS) ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -492,6 +493,10 @@ uninstall-am: + .PRECIOUS: Makefile + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Tell versions [3.59,3.63) of GNU make to not export all variables. + # Otherwise a system limit (for SysV at least) may be exceeded. + .NOEXPORT: +diff --git a/libitm/testsuite/lib/libitm.exp b/libitm/testsuite/lib/libitm.exp +index b3d247b9f98..47c2cd55dac 100644 +--- a/libitm/testsuite/lib/libitm.exp ++++ b/libitm/testsuite/lib/libitm.exp +@@ -77,6 +77,7 @@ proc libitm_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -92,6 +93,8 @@ proc libitm_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-9.4.0/0006-libvtv-test-fix.diff b/patches/gcc-9.4.0/0006-libvtv-test-fix.diff new file mode 100644 index 0000000..060cc58 --- /dev/null +++ b/patches/gcc-9.4.0/0006-libvtv-test-fix.diff @@ -0,0 +1,58 @@ +diff --git a/libvtv/testsuite/Makefile.am b/libvtv/testsuite/Makefile.am +index 41cfbc46e4b..16f82bdf691 100644 +--- a/libvtv/testsuite/Makefile.am ++++ b/libvtv/testsuite/Makefile.am +@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \ + _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + RUNTEST = $(_RUNTEST) $(AM_RUNTESTFLAGS) ++ ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp ++ ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ +diff --git a/libvtv/testsuite/Makefile.in b/libvtv/testsuite/Makefile.in +index e104f62c035..d7401b110ff 100644 +--- a/libvtv/testsuite/Makefile.in ++++ b/libvtv/testsuite/Makefile.in +@@ -280,6 +280,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \ + echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi) + + RUNTEST = $(_RUNTEST) $(AM_RUNTESTFLAGS) ++EXTRA_DEJAGNU_SITE_CONFIG = extra.exp + all: all-am + + .SUFFIXES: +@@ -487,6 +488,10 @@ uninstall-am: + .PRECIOUS: Makefile + + ++extra.exp: ++ echo 'set BUILD_CC "$(CC)"' > $@.tmp ++ mv $@.tmp $@ ++ + # Tell versions [3.59,3.63) of GNU make to not export all variables. + # Otherwise a system limit (for SysV at least) may be exceeded. + .NOEXPORT: +diff --git a/libvtv/testsuite/lib/libvtv.exp b/libvtv/testsuite/lib/libvtv.exp +index 4b71c9ce7bc..ef06e4a3199 100644 +--- a/libvtv/testsuite/lib/libvtv.exp ++++ b/libvtv/testsuite/lib/libvtv.exp +@@ -76,6 +76,7 @@ proc libvtv_init { args } { + global ALWAYS_CFLAGS + global CFLAGS + global TOOL_EXECUTABLE TOOL_OPTIONS ++ global BUILD_CC + global GCC_UNDER_TEST + global TESTING_IN_BUILD_TREE + global target_triplet +@@ -91,6 +92,8 @@ proc libvtv_init { args } { + if ![info exists GCC_UNDER_TEST] then { + if [info exists TOOL_EXECUTABLE] { + set GCC_UNDER_TEST $TOOL_EXECUTABLE ++ } elseif [info exists BUILD_CC] { ++ set GCC_UNDER_TEST $BUILD_CC + } else { + set GCC_UNDER_TEST "[find_gcc]" + } diff --git a/patches/gcc-9.4.0/0007-j2.diff b/patches/gcc-9.4.0/0007-j2.diff new file mode 100644 index 0000000..71c4bac --- /dev/null +++ b/patches/gcc-9.4.0/0007-j2.diff @@ -0,0 +1,346 @@ +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 09fb9ecd2cd..79ac206d10e 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -536,7 +536,7 @@ s390*-*-*) + extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h" + ;; + # Note the 'l'; we need to be able to match e.g. "shle" or "shl". +-sh[123456789lbe]*-*-* | sh-*-*) ++sh[123456789lbej]*-*-* | sh-*-*) + cpu_type=sh + extra_options="${extra_options} fused-madd.opt" + extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o" +@@ -2834,18 +2834,18 @@ s390x-ibm-tpf*) + extra_options="${extra_options} s390/tpf.opt" + tmake_file="${tmake_file} s390/t-s390" + ;; +-sh-*-elf* | sh[12346l]*-*-elf* | \ +- sh-*-linux* | sh[2346lbe]*-*-linux* | \ ++sh-*-elf* | sh[12346lj]*-*-elf* | \ ++ sh-*-linux* | sh[2346lbej]*-*-linux* | \ + sh-*-netbsdelf* | shl*-*-netbsdelf*) + tmake_file="${tmake_file} sh/t-sh sh/t-elf" + if test x${with_endian} = x; then + case ${target} in +- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;; ++ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;; + shbe-*-* | sheb-*-*) with_endian=big,little ;; + sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;; + shl* | sh*-*-linux* | \ + sh-superh-elf) with_endian=little,big ;; +- sh[1234]*-*-*) with_endian=big ;; ++ sh[j1234]*-*-*) with_endian=big ;; + *) with_endian=big,little ;; + esac + fi +@@ -2912,6 +2912,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;; + sh2a*) sh_cpu_target=sh2a ;; + sh2e*) sh_cpu_target=sh2e ;; ++ shj2*) sh_cpu_target=shj2;; + sh2*) sh_cpu_target=sh2 ;; + *) sh_cpu_target=sh1 ;; + esac +@@ -2933,7 +2934,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \ + sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \ + sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \ +- sh3e | sh3 | sh2e | sh2 | sh1) ;; ++ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;; + "") sh_cpu_default=${sh_cpu_target} ;; + *) echo "with_cpu=$with_cpu not supported"; exit 1 ;; + esac +@@ -2942,9 +2943,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + case ${target} in + sh[1234]*) sh_multilibs=${sh_cpu_target} ;; + sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;; +- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;; ++ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;; + sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;; +- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;; ++ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;; + esac + if test x$with_fp = xno; then + sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`" +@@ -2959,7 +2960,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + m1 | m2 | m2e | m3 | m3e | \ + m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\ + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \ +- m2a | m2a-single | m2a-single-only | m2a-nofpu) ++ m2a | m2a-single | m2a-single-only | m2a-nofpu | \ ++ mj2) + # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition + # It is passed to MULTIILIB_OPTIONS verbatim. + TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}" +@@ -2976,7 +2978,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \ + done + TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'` + if test x${enable_incomplete_targets} = xyes ; then +- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1" ++ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1" + fi + tm_file="$tm_file ./sysroot-suffix.h" + tmake_file="$tmake_file t-sysroot-suffix" +@@ -4760,6 +4762,8 @@ case "${target}" in + ;; + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al) + ;; ++ mj2) ++ ;; + *) + echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2 + echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2 +@@ -4984,7 +4988,7 @@ case ${target} in + tmake_file="${cpu_type}/t-${cpu_type} ${tmake_file}" + ;; + +- sh[123456ble]*-*-* | sh-*-*) ++ sh[123456blej]*-*-* | sh-*-*) + c_target_objs="${c_target_objs} sh-c.o" + cxx_target_objs="${cxx_target_objs} sh-c.o" + ;; +diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c +index 8dc79a764df..36683614277 100644 +--- a/gcc/config/sh/sh.c ++++ b/gcc/config/sh/sh.c +@@ -686,6 +686,7 @@ parse_validate_atomic_model_option (const char* str) + model_names[sh_atomic_model::hard_llcs] = "hard-llcs"; + model_names[sh_atomic_model::soft_tcb] = "soft-tcb"; + model_names[sh_atomic_model::soft_imask] = "soft-imask"; ++ model_names[sh_atomic_model::hard_cas] = "hard-cas"; + + const char* model_cdef_names[sh_atomic_model::num_models]; + model_cdef_names[sh_atomic_model::none] = "NONE"; +@@ -693,6 +694,7 @@ parse_validate_atomic_model_option (const char* str) + model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS"; + model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB"; + model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK"; ++ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS"; + + sh_atomic_model ret; + ret.type = sh_atomic_model::none; +@@ -771,6 +773,9 @@ got_mode_name:; + if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE) + err_ret ("cannot use atomic model %s in user mode", ret.name); + ++ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2) ++ err_ret ("atomic model %s is only available J2 targets", ret.name); ++ + return ret; + + #undef err_ret +@@ -827,6 +832,8 @@ sh_option_override (void) + sh_cpu = PROCESSOR_SH2E; + if (TARGET_SH2A) + sh_cpu = PROCESSOR_SH2A; ++ if (TARGET_SHJ2) ++ sh_cpu = PROCESSOR_SHJ2; + if (TARGET_SH3) + sh_cpu = PROCESSOR_SH3; + if (TARGET_SH3E) +diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h +index 0204872eae7..30416a34e30 100644 +--- a/gcc/config/sh/sh.h ++++ b/gcc/config/sh/sh.h +@@ -83,6 +83,7 @@ extern int code_for_indirect_jump_scratch; + #define SUPPORT_SH4_SINGLE 1 + #define SUPPORT_SH2A 1 + #define SUPPORT_SH2A_SINGLE 1 ++#define SUPPORT_SHJ2 1 + #endif + + #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) +@@ -115,6 +116,7 @@ extern int code_for_indirect_jump_scratch; + #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) + #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) + #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) ++#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2) + + #if SUPPORT_SH1 + #define SUPPORT_SH2 1 +@@ -122,6 +124,7 @@ extern int code_for_indirect_jump_scratch; + #if SUPPORT_SH2 + #define SUPPORT_SH3 1 + #define SUPPORT_SH2A_NOFPU 1 ++#define SUPPORT_SHJ2 1 + #endif + #if SUPPORT_SH3 + #define SUPPORT_SH4_NOFPU 1 +@@ -154,7 +157,7 @@ extern int code_for_indirect_jump_scratch; + #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ + | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ + | MASK_HARD_SH4 | MASK_FPU_SINGLE \ +- | MASK_FPU_SINGLE_ONLY) ++ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2) + + /* This defaults us to big-endian. */ + #ifndef TARGET_ENDIAN_DEFAULT +@@ -229,7 +232,8 @@ extern int code_for_indirect_jump_scratch; + %{m2a-single:--isa=sh2a} \ + %{m2a-single-only:--isa=sh2a} \ + %{m2a-nofpu:--isa=sh2a-nofpu} \ +-%{m4al:-dsp}" ++%{m4al:-dsp} \ ++%{mj2:-isa=j2}" + + #define ASM_SPEC SH_ASM_SPEC + +@@ -345,6 +349,7 @@ struct sh_atomic_model + hard_llcs, + soft_tcb, + soft_imask, ++ hard_cas, + + num_models + }; +@@ -388,6 +393,9 @@ extern const sh_atomic_model& selected_atomic_model (void); + #define TARGET_ATOMIC_SOFT_IMASK \ + (selected_atomic_model ().type == sh_atomic_model::soft_imask) + ++#define TARGET_ATOMIC_HARD_CAS \ ++ (selected_atomic_model ().type == sh_atomic_model::hard_cas) ++ + #endif // __cplusplus + + #define SUBTARGET_OVERRIDE_OPTIONS (void) 0 +@@ -1521,7 +1529,7 @@ extern bool current_function_interrupt; + + /* Nonzero if the target supports dynamic shift instructions + like shad and shld. */ +-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) ++#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2) + + /* The cost of using the dynamic shift insns (shad, shld) are the same + if they are available. If they are not available a library function will +@@ -1784,6 +1792,7 @@ enum processor_type { + PROCESSOR_SH2, + PROCESSOR_SH2E, + PROCESSOR_SH2A, ++ PROCESSOR_SHJ2, + PROCESSOR_SH3, + PROCESSOR_SH3E, + PROCESSOR_SH4, +diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt +index 8eb1a4e121a..9c28ed6b5c0 100644 +--- a/gcc/config/sh/sh.opt ++++ b/gcc/config/sh/sh.opt +@@ -65,6 +65,10 @@ m2e + Target RejectNegative Condition(SUPPORT_SH2E) + Generate SH2e code. + ++mj2 ++Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2) ++Generate J2 code. ++ + m3 + Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) + Generate SH3 code. +diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md +index 691d9287101..3ffb099195d 100644 +--- a/gcc/config/sh/sync.md ++++ b/gcc/config/sh/sync.md +@@ -240,6 +240,9 @@ + || (TARGET_SH4A && mode == SImode && !TARGET_ATOMIC_STRICT)) + atomic_insn = gen_atomic_compare_and_swap_hard (old_val, mem, + exp_val, new_val); ++ else if (TARGET_ATOMIC_HARD_CAS && mode == SImode) ++ atomic_insn = gen_atomic_compare_and_swap_cas (old_val, mem, ++ exp_val, new_val); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic_compare_and_swap_soft_gusa (old_val, mem, + exp_val, new_val); +@@ -306,6 +309,57 @@ + } + [(set_attr "length" "14")]) + ++(define_expand "atomic_compare_and_swapsi_cas" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "r")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{ ++ rtx mem = gen_rtx_REG (SImode, 0); ++ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0))); ++ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_insn "shj2_cas" ++ [(set (match_operand:SI 0 "register_operand" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "register_operand" "=r") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "0")] ++ UNSPECV_CMPXCHG_1)) ++ (set (reg:SI T_REG) ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))] ++ "TARGET_ATOMIC_HARD_CAS" ++ "cas.l %2,%0,@%1" ++ [(set_attr "length" "2")] ++) ++ ++(define_expand "atomic_compare_and_swapqi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ ++(define_expand "atomic_compare_and_swaphi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ + ;; The QIHImode llcs patterns modify the address register of the memory + ;; operand. In order to express that, we have to open code the memory + ;; operand. Initially the insn is expanded like every other atomic insn +diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh +index e1a398319d5..19a6f3f7ea8 100644 +--- a/gcc/config/sh/t-sh ++++ b/gcc/config/sh/t-sh +@@ -50,7 +50,8 @@ MULTILIB_MATCHES = $(shell \ + m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \ + m2a-single,m2a-single-only \ + m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \ +- m4,m4-100,m4-200,m4-300,m4a; do \ ++ m4,m4-100,m4-200,m4-300,m4a \ ++ mj2; do \ + subst= ; \ + for lib in `echo $$abi|tr , ' '` ; do \ + if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \ +@@ -63,9 +64,9 @@ MULTILIB_MATCHES = $(shell \ + + # SH1 and SH2A support big endian only. + ifeq ($(DEFAULT_ENDIAN),ml) +-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + else +-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + endif + + MULTILIB_OSDIRNAMES = \ +@@ -87,7 +88,8 @@ MULTILIB_OSDIRNAMES = \ + m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \ + m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \ + m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \ +- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al ++ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \ ++ mj2=!j2 + + $(out_object_file): gt-sh.h + gt-sh.h : s-gtype ; @true diff --git a/patches/gcc-9.4.0/0008-s390x-muslldso.diff b/patches/gcc-9.4.0/0008-s390x-muslldso.diff new file mode 100644 index 0000000..d385f25 --- /dev/null +++ b/patches/gcc-9.4.0/0008-s390x-muslldso.diff @@ -0,0 +1,14 @@ +diff --git a/gcc/config/s390/linux.h b/gcc/config/s390/linux.h +index f76986acdab..5f6b7041f0f 100644 +--- a/gcc/config/s390/linux.h ++++ b/gcc/config/s390/linux.h +@@ -75,6 +75,9 @@ along with GCC; see the file COPYING3. If not see + #define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1" + #define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1" + ++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-s390.so.1" ++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-s390x.so.1" ++ + #undef LINK_SPEC + #define LINK_SPEC \ + "%{m31:-m elf_s390}%{m64:-m elf64_s390} \ diff --git a/patches/gcc-9.4.0/0009-microblaze-pr65649.diff b/patches/gcc-9.4.0/0009-microblaze-pr65649.diff new file mode 100644 index 0000000..e733b5c --- /dev/null +++ b/patches/gcc-9.4.0/0009-microblaze-pr65649.diff @@ -0,0 +1,22 @@ +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 55c1becf975..45395ab86f1 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2476,7 +2476,7 @@ print_operand (FILE * file, rtx op, int letter) + unsigned long value_long; + REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), + value_long); +- fprintf (file, HOST_WIDE_INT_PRINT_HEX, value_long); ++ fprintf (file, "0x%lx", value_long); + } + else + { +@@ -2535,7 +2535,7 @@ print_operand (FILE * file, rtx op, int letter) + print_operand_address (file, XEXP (op, 0)); + } + else if (letter == 'm') +- fprintf (file, HOST_WIDE_INT_PRINT_DEC, (1L << INTVAL (op))); ++ fprintf (file, "%ld", (1L << INTVAL (op))); + else + output_addr_const (file, op); + } diff --git a/patches/gcc-9.4.0/0010-ldbl128-config.diff b/patches/gcc-9.4.0/0010-ldbl128-config.diff new file mode 100644 index 0000000..04b88a0 --- /dev/null +++ b/patches/gcc-9.4.0/0010-ldbl128-config.diff @@ -0,0 +1,63 @@ +diff --git a/gcc/configure b/gcc/configure +index 3dcf7752b7f..78aaa36dce6 100755 +--- a/gcc/configure ++++ b/gcc/configure +@@ -29356,6 +29356,15 @@ if test "${with_long_double_128+set}" = set; then : + withval=$with_long_double_128; gcc_cv_target_ldbl128="$with_long_double_128" + else + ++ case "$target" in ++ s390*-*-linux-musl*) ++ gcc_cv_target_ldbl128=yes ++ ;; ++ powerpc*-*-linux-musl*) ++ gcc_cv_target_ldbl128=no ++ ;; ++ *) ++ + if test $glibc_version_major -gt 2 \ + || ( test $glibc_version_major -eq 2 && test $glibc_version_minor -ge 4 ); then : + gcc_cv_target_ldbl128=yes +@@ -29367,6 +29376,10 @@ else + && gcc_cv_target_ldbl128=yes + + fi ++ ++ ;; ++ esac ++ + fi + + ;; +diff --git a/gcc/configure.ac b/gcc/configure.ac +index 51f520c1508..a6498239698 100644 +--- a/gcc/configure.ac ++++ b/gcc/configure.ac +@@ -6020,13 +6020,25 @@ case "$target" in + AC_ARG_WITH(long-double-128, + [AS_HELP_STRING([--with-long-double-128], + [use 128-bit long double by default])], +- gcc_cv_target_ldbl128="$with_long_double_128", ++ gcc_cv_target_ldbl128="$with_long_double_128", [ ++ case "$target" in ++ s390*-*-linux-musl*) ++ gcc_cv_target_ldbl128=yes ++ ;; ++ powerpc*-*-linux-musl*) ++ gcc_cv_target_ldbl128=no ++ ;; ++ *)] + [GCC_GLIBC_VERSION_GTE_IFELSE([2], [4], [gcc_cv_target_ldbl128=yes], [ + [gcc_cv_target_ldbl128=no + grep '^[ ]*#[ ]*define[ ][ ]*__LONG_DOUBLE_MATH_OPTIONAL' \ + $target_header_dir/bits/wordsize.h > /dev/null 2>&1 \ + && gcc_cv_target_ldbl128=yes +- ]])]) ++ ]])] ++ [ ++ ;; ++ esac ++ ]) + ;; + esac + if test x$gcc_cv_target_ldbl128 = xyes; then diff --git a/patches/gcc-9.4.0/0011-m68k.diff b/patches/gcc-9.4.0/0011-m68k.diff new file mode 100644 index 0000000..79a15d1 --- /dev/null +++ b/patches/gcc-9.4.0/0011-m68k.diff @@ -0,0 +1,27 @@ +diff --git a/gcc/config/m68k/linux.h b/gcc/config/m68k/linux.h +index ebdf0281071..beef554b31c 100644 +--- a/gcc/config/m68k/linux.h ++++ b/gcc/config/m68k/linux.h +@@ -73,6 +73,9 @@ along with GCC; see the file COPYING3. If not see + + #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" + ++#undef MUSL_DYNAMIC_LINKER ++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-m68k.so.1" ++ + #undef LINK_SPEC + #define LINK_SPEC "-m m68kelf %{shared} \ + %{!shared: \ +diff --git a/libgcc/config/m68k/linux-unwind.h b/libgcc/config/m68k/linux-unwind.h +index fbe0d4748ba..57c354ee9b4 100644 +--- a/libgcc/config/m68k/linux-unwind.h ++++ b/libgcc/config/m68k/linux-unwind.h +@@ -37,7 +37,7 @@ struct uw_ucontext { + stack_t uc_stack; + mcontext_t uc_mcontext; + unsigned long uc_filler[80]; +- __sigset_t uc_sigmask; ++ sigset_t uc_sigmask; + }; + + #define MD_FALLBACK_FRAME_STATE_FOR m68k_fallback_frame_state diff --git a/patches/gcc-9.4.0/0012-static-pie.diff b/patches/gcc-9.4.0/0012-static-pie.diff new file mode 100644 index 0000000..400d7a1 --- /dev/null +++ b/patches/gcc-9.4.0/0012-static-pie.diff @@ -0,0 +1,86 @@ +diff --git a/gcc/common.opt b/gcc/common.opt +index d342c4f3749..2aae4a3cefb 100644 +--- a/gcc/common.opt ++++ b/gcc/common.opt +@@ -3287,11 +3287,11 @@ Driver + + no-pie + Driver RejectNegative Negative(shared) +-Don't create a dynamically linked position independent executable. ++Don't create a position independent executable. + + pie + Driver RejectNegative Negative(no-pie) +-Create a dynamically linked position independent executable. ++Create a position independent executable. + + static-pie + Driver RejectNegative Negative(pie) +diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h +index 055a4f0afec..7a671c6a49c 100644 +--- a/gcc/config/gnu-user.h ++++ b/gcc/config/gnu-user.h +@@ -51,13 +51,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define GNU_USER_TARGET_STARTFILE_SPEC \ + "%{shared:; \ + pg|p|profile:%{static-pie:grcrt1.o%s;:gcrt1.o%s}; \ +- static:crt1.o%s; \ +- static-pie:rcrt1.o%s; \ ++ static|static-pie:%{" PIE_SPEC ":rcrt1.o%s;:crt1.o%s}; \ + " PIE_SPEC ":Scrt1.o%s; \ + :crt1.o%s} " \ + GNU_USER_TARGET_CRTI " \ +- %{static:crtbeginT.o%s; \ +- shared|static-pie|" PIE_SPEC ":crtbeginS.o%s; \ ++ %{shared|" PIE_SPEC ":crtbeginS.o%s; \ ++ static:crtbeginT.o%s; \ + :crtbegin.o%s} \ + %{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_start_preinit.o%s; \ +@@ -76,8 +75,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + "%{fvtable-verify=none:%s; \ + fvtable-verify=preinit:vtv_end_preinit.o%s; \ + fvtable-verify=std:vtv_end.o%s} \ +- %{static:crtend.o%s; \ +- shared|static-pie|" PIE_SPEC ":crtendS.o%s; \ ++ %{shared|" PIE_SPEC ":crtendS.o%s; \ + :crtend.o%s} " \ + GNU_USER_TARGET_CRTN " " \ + CRTOFFLOADEND +@@ -106,7 +104,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + #define LIB_SPEC GNU_USER_TARGET_LIB_SPEC + + #if defined(HAVE_LD_EH_FRAME_HDR) +-#define LINK_EH_SPEC "%{!static|static-pie:--eh-frame-hdr} " ++#define LINK_EH_SPEC "%{!static|" PIE_SPEC ":--eh-frame-hdr} " + #endif + + #define GNU_USER_TARGET_LINK_GCC_C_SEQUENCE_SPEC \ +diff --git a/gcc/gcc.c b/gcc/gcc.c +index d185c01b257..5d3f81c5fc5 100644 +--- a/gcc/gcc.c ++++ b/gcc/gcc.c +@@ -908,7 +908,7 @@ proper position among the other output files. */ + #define NO_FPIE_AND_FPIC_SPEC NO_FPIE_SPEC "|" NO_FPIC_SPEC + #define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;" + #else +-#define PIE_SPEC "pie" ++#define PIE_SPEC "pie|static-pie" + #define FPIE1_SPEC "fpie" + #define NO_FPIE1_SPEC FPIE1_SPEC ":;" + #define FPIE2_SPEC "fPIE" +@@ -932,12 +932,12 @@ proper position among the other output files. */ + #ifndef LINK_PIE_SPEC + #ifdef HAVE_LD_PIE + #ifndef LD_PIE_SPEC +-#define LD_PIE_SPEC "-pie" ++#define LD_PIE_SPEC "-pie %{static-pie:-static} %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}" + #endif + #else + #define LD_PIE_SPEC "" + #endif +-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} " ++#define LINK_PIE_SPEC "%{shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} " + #endif + + #ifndef LINK_BUILDID_SPEC diff --git a/patches/gcc-9.4.0/0013-invalid-tls-model.diff b/patches/gcc-9.4.0/0013-invalid-tls-model.diff new file mode 100644 index 0000000..ac2d56b --- /dev/null +++ b/patches/gcc-9.4.0/0013-invalid-tls-model.diff @@ -0,0 +1,28 @@ +diff --git a/libgomp/configure.tgt b/libgomp/configure.tgt +index b88bf72fe3d..747d0485bf8 100644 +--- a/libgomp/configure.tgt ++++ b/libgomp/configure.tgt +@@ -17,6 +17,9 @@ if test $gcc_cv_have_tls = yes ; then + *-*-k*bsd*-gnu*) + ;; + ++ *-*-musl*) ++ ;; ++ + *-*-linux* | *-*-gnu*) + XCFLAGS="${XCFLAGS} -ftls-model=initial-exec -DUSING_INITIAL_EXEC_TLS" + ;; +diff --git a/libitm/configure.tgt b/libitm/configure.tgt +index 4c0b602034b..65e1c83550a 100644 +--- a/libitm/configure.tgt ++++ b/libitm/configure.tgt +@@ -31,6 +31,9 @@ + if test "$gcc_cv_have_tls" = yes ; then + case "${target}" in + ++ *-*-musl*) ++ ;; ++ + # For x86, we use slots in the TCB head for most of our TLS. + # The setup of those slots in beginTransaction can afford to + # use the global-dynamic model. diff --git a/patches/gcc-9.4.0/0014-fix-gthr-weak-refs-for-libgcc.patch b/patches/gcc-9.4.0/0014-fix-gthr-weak-refs-for-libgcc.patch new file mode 100644 index 0000000..56291a2 --- /dev/null +++ b/patches/gcc-9.4.0/0014-fix-gthr-weak-refs-for-libgcc.patch @@ -0,0 +1,51 @@ +From 51a354a0fb54165d505bfed9819c0440027312d9 Mon Sep 17 00:00:00 2001 +From: Szabolcs Nagy +Date: Sun, 22 Sep 2019 23:04:48 +0000 +Subject: [PATCH] fix gthr weak refs for libgcc + +ideally gthr-posix.h should be fixed not to use weak refs for +single thread detection by default since that's unsafe. + +currently we have to opt out explicitly from the unsafe behaviour +in the configure machinery of each target lib that uses gthr and +musl missed libgcc previously. + +related bugs and discussions +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78017 +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87189 +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91737 +https://sourceware.org/bugzilla/show_bug.cgi?id=5784 +https://sourceware.org/ml/libc-alpha/2012-09/msg00192.html +https://sourceware.org/ml/libc-alpha/2019-08/msg00438.html +--- + libgcc/config.host | 7 +++++++ + libgcc/config/t-gthr-noweak | 2 ++ + 2 files changed, 9 insertions(+) + create mode 100644 libgcc/config/t-gthr-noweak + +diff --git a/libgcc/config.host b/libgcc/config.host +index 122113fc519..fe1b9ab93d5 100644 +--- a/libgcc/config.host ++++ b/libgcc/config.host +@@ -1500,3 +1500,10 @@ aarch64*-*-*) + tm_file="${tm_file} aarch64/value-unwind.h" + ;; + esac ++ ++case ${host} in ++*-*-musl*) ++ # The gthr weak references are unsafe with static linking ++ tmake_file="$tmake_file t-gthr-noweak" ++ ;; ++esac +diff --git a/libgcc/config/t-gthr-noweak b/libgcc/config/t-gthr-noweak +new file mode 100644 +index 00000000000..45a21e9361d +--- /dev/null ++++ b/libgcc/config/t-gthr-noweak +@@ -0,0 +1,2 @@ ++# Don't use weak references for single-thread detection ++HOST_LIBGCC2_CFLAGS += -DGTHREAD_USE_WEAK=0 +-- +2.17.1 + diff --git a/patches/gcc-9.4.0/0015-riscv-tls-copy-relocs.diff b/patches/gcc-9.4.0/0015-riscv-tls-copy-relocs.diff new file mode 100644 index 0000000..566be71 --- /dev/null +++ b/patches/gcc-9.4.0/0015-riscv-tls-copy-relocs.diff @@ -0,0 +1,16 @@ +diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c +index 677728e77ed..444d01e87ec 100644 +--- a/gcc/config/riscv/riscv.c ++++ b/gcc/config/riscv/riscv.c +@@ -1209,9 +1209,11 @@ riscv_legitimize_tls_address (rtx loc) + rtx dest, tp, tmp; + enum tls_model model = SYMBOL_REF_TLS_MODEL (loc); + ++#if 0 + /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */ + if (!flag_pic) + model = TLS_MODEL_LOCAL_EXEC; ++#endif + + switch (model) + { diff --git a/patches/gcc-9.4.0/0016-libstdc++-futex-time64.diff b/patches/gcc-9.4.0/0016-libstdc++-futex-time64.diff new file mode 100644 index 0000000..08f6261 --- /dev/null +++ b/patches/gcc-9.4.0/0016-libstdc++-futex-time64.diff @@ -0,0 +1,18 @@ +--- gcc-9.2.0/libstdc++-v3/src/c++11/futex.cc.orig 2020-01-20 14:55:05.507548334 -0500 ++++ gcc-9.2.0/libstdc++-v3/src/c++11/futex.cc 2020-01-20 14:56:52.458268068 -0500 +@@ -61,7 +61,15 @@ + struct timeval tv; + gettimeofday (&tv, NULL); + // Convert the absolute timeout value to a relative timeout ++#if defined(SYS_futex_time64) && SYS_futex_time64 != SYS_futex ++ struct ++ { ++ long tv_sec; ++ long tv_nsec; ++ } rt; ++#else + struct timespec rt; ++#endif + rt.tv_sec = __s.count() - tv.tv_sec; + rt.tv_nsec = __ns.count() - tv.tv_usec * 1000; + if (rt.tv_nsec < 0) diff --git a/patches/gcc-9.4.0/0018-m68k-sqrt.diff b/patches/gcc-9.4.0/0018-m68k-sqrt.diff new file mode 100644 index 0000000..5d46272 --- /dev/null +++ b/patches/gcc-9.4.0/0018-m68k-sqrt.diff @@ -0,0 +1,18 @@ +--- gcc-9.2.0.orig/gcc/config/m68k/m68k.md 2019-01-01 07:31:55.000000000 -0500 ++++ gcc-9.2.0/gcc/config/m68k/m68k.md 2020-07-01 15:57:20.528408009 -0400 +@@ -4126,13 +4126,13 @@ + (define_expand "sqrt2" + [(set (match_operand:FP 0 "nonimmediate_operand" "") + (sqrt:FP (match_operand:FP 1 "general_operand" "")))] +- "TARGET_HARD_FLOAT" ++ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU" + "") + + (define_insn "sqrt2_68881" + [(set (match_operand:FP 0 "nonimmediate_operand" "=f") + (sqrt:FP (match_operand:FP 1 "general_operand" "fm")))] +- "TARGET_68881" ++ "TARGET_68881 && TARGET_68040" + { + if (FP_REG_P (operands[1])) + return "fsqrt%.x %1,%0"; diff --git a/patches/gcc-9.4.0/0019-broken-builtin-memcmp.diff b/patches/gcc-9.4.0/0019-broken-builtin-memcmp.diff new file mode 100644 index 0000000..84d8b3a --- /dev/null +++ b/patches/gcc-9.4.0/0019-broken-builtin-memcmp.diff @@ -0,0 +1,11 @@ +diff -ur gcc-9.3.0.orig/gcc/builtins.c gcc-9.3.0/gcc/builtins.c +--- gcc-9.3.0.orig/gcc/builtins.c 2020-03-12 11:07:21.000000000 +0000 ++++ gcc-9.3.0/gcc/builtins.c 2020-09-23 22:16:54.815251679 +0000 +@@ -4658,6 +4658,7 @@ + static rtx + expand_builtin_memcmp (tree exp, rtx target, bool result_eq) + { ++ return NULL_RTX; + if (!validate_arglist (exp, + POINTER_TYPE, POINTER_TYPE, INTEGER_TYPE, VOID_TYPE)) + return NULL_RTX; diff --git a/patches/linux-4.19.90/0001-asound-time64.diff b/patches/linux-4.19.90/0001-asound-time64.diff new file mode 100644 index 0000000..a943961 --- /dev/null +++ b/patches/linux-4.19.90/0001-asound-time64.diff @@ -0,0 +1,289 @@ +diff -ur a/include/uapi/sound/asound.h b/include/uapi/sound/asound.h +--- a/include/uapi/sound/asound.h 2019-10-15 12:26:39.634141383 -0400 ++++ b/include/uapi/sound/asound.h 2020-01-30 21:43:56.477450321 -0500 +@@ -35,6 +35,8 @@ + #include + #endif + ++#include ++ + /* + * protocol version + */ +@@ -154,7 +156,7 @@ + * * + *****************************************************************************/ + +-#define SNDRV_PCM_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 14) ++#define SNDRV_PCM_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 15) + + typedef unsigned long snd_pcm_uframes_t; + typedef signed long snd_pcm_sframes_t; +@@ -301,7 +303,9 @@ + #define SNDRV_PCM_INFO_DRAIN_TRIGGER 0x40000000 /* internal kernel flag - trigger in drain */ + #define SNDRV_PCM_INFO_FIFO_IN_FRAMES 0x80000000 /* internal kernel flag - FIFO size is in frames */ + +- ++#if (__BITS_PER_LONG == 32 && defined(__USE_TIME_BITS64)) || defined __KERNEL__ ++#define __SND_STRUCT_TIME64 ++#endif + + typedef int __bitwise snd_pcm_state_t; + #define SNDRV_PCM_STATE_OPEN ((__force snd_pcm_state_t) 0) /* stream is open */ +@@ -317,8 +321,17 @@ + + enum { + SNDRV_PCM_MMAP_OFFSET_DATA = 0x00000000, +- SNDRV_PCM_MMAP_OFFSET_STATUS = 0x80000000, +- SNDRV_PCM_MMAP_OFFSET_CONTROL = 0x81000000, ++ SNDRV_PCM_MMAP_OFFSET_STATUS_OLD = 0x80000000, ++ SNDRV_PCM_MMAP_OFFSET_CONTROL_OLD = 0x81000000, ++ SNDRV_PCM_MMAP_OFFSET_STATUS_NEW = 0x82000000, ++ SNDRV_PCM_MMAP_OFFSET_CONTROL_NEW = 0x83000000, ++#ifdef __SND_STRUCT_TIME64 ++ SNDRV_PCM_MMAP_OFFSET_STATUS = SNDRV_PCM_MMAP_OFFSET_STATUS_NEW, ++ SNDRV_PCM_MMAP_OFFSET_CONTROL = SNDRV_PCM_MMAP_OFFSET_CONTROL_NEW, ++#else ++ SNDRV_PCM_MMAP_OFFSET_STATUS = SNDRV_PCM_MMAP_OFFSET_STATUS_OLD, ++ SNDRV_PCM_MMAP_OFFSET_CONTROL = SNDRV_PCM_MMAP_OFFSET_CONTROL_OLD, ++#endif + }; + + union snd_pcm_sync_id { +@@ -456,8 +469,13 @@ + SNDRV_PCM_AUDIO_TSTAMP_TYPE_LAST = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED + }; + ++#ifndef __KERNEL__ ++/* explicit padding avoids incompatibility between i386 and x86-64 */ ++typedef struct { unsigned char pad[sizeof(time_t) - sizeof(int)] } __time_pad; ++ + struct snd_pcm_status { + snd_pcm_state_t state; /* stream state */ ++ __time_pad pad1; /* align to timespec */ + struct timespec trigger_tstamp; /* time when stream was started/stopped/paused */ + struct timespec tstamp; /* reference timestamp */ + snd_pcm_uframes_t appl_ptr; /* appl ptr */ +@@ -473,17 +491,48 @@ + __u32 audio_tstamp_accuracy; /* in ns units, only valid if indicated in audio_tstamp_data */ + unsigned char reserved[52-2*sizeof(struct timespec)]; /* must be filled with zero */ + }; ++#endif + +-struct snd_pcm_mmap_status { ++/* ++ * For mmap operations, we need the 64-bit layout, both for compat mode, ++ * and for y2038 compatibility. For 64-bit applications, the two definitions ++ * are identical, so we keep the traditional version. ++ */ ++#ifdef __SND_STRUCT_TIME64 ++#define __snd_pcm_mmap_status64 snd_pcm_mmap_status ++#define __snd_pcm_mmap_control64 snd_pcm_mmap_control ++#define __snd_pcm_sync_ptr64 snd_pcm_sync_ptr ++#ifdef __KERNEL__ ++#define __snd_timespec64 __kernel_timespec ++#else ++#define __snd_timespec64 timespec ++#endif ++struct __snd_timespec { ++ __s32 tv_sec; ++ __s32 tv_nsec; ++}; ++#else ++#define __snd_pcm_mmap_status snd_pcm_mmap_status ++#define __snd_pcm_mmap_control snd_pcm_mmap_control ++#define __snd_pcm_sync_ptr snd_pcm_sync_ptr ++#define __snd_timespec timespec ++struct __snd_timespec64 { ++ __s64 tv_sec; ++ __s64 tv_nsec; ++}; ++ ++#endif ++ ++struct __snd_pcm_mmap_status { + snd_pcm_state_t state; /* RO: state - SNDRV_PCM_STATE_XXXX */ + int pad1; /* Needed for 64 bit alignment */ + snd_pcm_uframes_t hw_ptr; /* RO: hw ptr (0...boundary-1) */ +- struct timespec tstamp; /* Timestamp */ ++ struct __snd_timespec tstamp; /* Timestamp */ + snd_pcm_state_t suspended_state; /* RO: suspended stream state */ +- struct timespec audio_tstamp; /* from sample counter or wall clock */ ++ struct __snd_timespec audio_tstamp; /* from sample counter or wall clock */ + }; + +-struct snd_pcm_mmap_control { ++struct __snd_pcm_mmap_control { + snd_pcm_uframes_t appl_ptr; /* RW: appl ptr (0...boundary-1) */ + snd_pcm_uframes_t avail_min; /* RW: min available frames for wakeup */ + }; +@@ -492,14 +541,59 @@ + #define SNDRV_PCM_SYNC_PTR_APPL (1<<1) /* get appl_ptr from driver (r/w op) */ + #define SNDRV_PCM_SYNC_PTR_AVAIL_MIN (1<<2) /* get avail_min from driver */ + +-struct snd_pcm_sync_ptr { ++struct __snd_pcm_sync_ptr { + unsigned int flags; + union { +- struct snd_pcm_mmap_status status; ++ struct __snd_pcm_mmap_status status; + unsigned char reserved[64]; + } s; + union { +- struct snd_pcm_mmap_control control; ++ struct __snd_pcm_mmap_control control; ++ unsigned char reserved[64]; ++ } c; ++}; ++ ++#if defined(__BYTE_ORDER) ? __BYTE_ORDER == __BIG_ENDIAN : defined(__BIG_ENDIAN) ++typedef char __pad_before_uframe[sizeof(__u64) - sizeof(snd_pcm_uframes_t)]; ++typedef char __pad_after_uframe[0]; ++#endif ++ ++#if defined(__BYTE_ORDER) ? __BYTE_ORDER == __LITTLE_ENDIAN : defined(__LITTLE_ENDIAN) ++typedef char __pad_before_uframe[0]; ++typedef char __pad_after_uframe[sizeof(__u64) - sizeof(snd_pcm_uframes_t)]; ++#endif ++ ++struct __snd_pcm_mmap_status64 { ++ __s32 state; /* RO: state - SNDRV_PCM_STATE_XXXX */ ++ __u32 pad1; /* Needed for 64 bit alignment */ ++ __pad_before_uframe __pad1; ++ snd_pcm_uframes_t hw_ptr; /* RO: hw ptr (0...boundary-1) */ ++ __pad_after_uframe __pad2; ++ struct __snd_timespec64 tstamp; /* Timestamp */ ++ __s32 suspended_state; /* RO: suspended stream state */ ++ __u32 pad3; /* Needed for 64 bit alignment */ ++ struct __snd_timespec64 audio_tstamp; /* sample counter or wall clock */ ++}; ++ ++struct __snd_pcm_mmap_control64 { ++ __pad_before_uframe __pad1; ++ snd_pcm_uframes_t appl_ptr; /* RW: appl ptr (0...boundary-1) */ ++ __pad_before_uframe __pad2; ++ ++ __pad_before_uframe __pad3; ++ snd_pcm_uframes_t avail_min; /* RW: min available frames for wakeup */ ++ __pad_after_uframe __pad4; ++}; ++ ++struct __snd_pcm_sync_ptr64 { ++ __u32 flags; ++ __u32 pad1; ++ union { ++ struct __snd_pcm_mmap_status64 status; ++ unsigned char reserved[64]; ++ } s; ++ union { ++ struct __snd_pcm_mmap_control64 control; + unsigned char reserved[64]; + } c; + }; +@@ -584,6 +678,8 @@ + #define SNDRV_PCM_IOCTL_STATUS _IOR('A', 0x20, struct snd_pcm_status) + #define SNDRV_PCM_IOCTL_DELAY _IOR('A', 0x21, snd_pcm_sframes_t) + #define SNDRV_PCM_IOCTL_HWSYNC _IO('A', 0x22) ++#define __SNDRV_PCM_IOCTL_SYNC_PTR _IOWR('A', 0x23, struct __snd_pcm_sync_ptr) ++#define __SNDRV_PCM_IOCTL_SYNC_PTR64 _IOWR('A', 0x23, struct __snd_pcm_sync_ptr64) + #define SNDRV_PCM_IOCTL_SYNC_PTR _IOWR('A', 0x23, struct snd_pcm_sync_ptr) + #define SNDRV_PCM_IOCTL_STATUS_EXT _IOWR('A', 0x24, struct snd_pcm_status) + #define SNDRV_PCM_IOCTL_CHANNEL_INFO _IOR('A', 0x32, struct snd_pcm_channel_info) +@@ -614,7 +710,7 @@ + * Raw MIDI section - /dev/snd/midi?? + */ + +-#define SNDRV_RAWMIDI_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 0) ++#define SNDRV_RAWMIDI_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 1) + + enum { + SNDRV_RAWMIDI_STREAM_OUTPUT = 0, +@@ -648,13 +744,16 @@ + unsigned char reserved[16]; /* reserved for future use */ + }; + ++#ifndef __KERNEL__ + struct snd_rawmidi_status { + int stream; ++ __time_pad pad1; + struct timespec tstamp; /* Timestamp */ + size_t avail; /* available bytes */ + size_t xruns; /* count of overruns since last status (in bytes) */ + unsigned char reserved[16]; /* reserved for future use */ + }; ++#endif + + #define SNDRV_RAWMIDI_IOCTL_PVERSION _IOR('W', 0x00, int) + #define SNDRV_RAWMIDI_IOCTL_INFO _IOR('W', 0x01, struct snd_rawmidi_info) +@@ -667,7 +766,7 @@ + * Timer section - /dev/snd/timer + */ + +-#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 6) ++#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 7) + + enum { + SNDRV_TIMER_CLASS_NONE = -1, +@@ -761,6 +860,7 @@ + unsigned char reserved[60]; /* reserved */ + }; + ++#ifndef __KERNEL__ + struct snd_timer_status { + struct timespec tstamp; /* Timestamp - last update */ + unsigned int resolution; /* current period resolution in ns */ +@@ -769,10 +869,11 @@ + unsigned int queue; /* used queue size */ + unsigned char reserved[64]; /* reserved */ + }; ++#endif + + #define SNDRV_TIMER_IOCTL_PVERSION _IOR('T', 0x00, int) + #define SNDRV_TIMER_IOCTL_NEXT_DEVICE _IOWR('T', 0x01, struct snd_timer_id) +-#define SNDRV_TIMER_IOCTL_TREAD _IOW('T', 0x02, int) ++#define SNDRV_TIMER_IOCTL_TREAD_OLD _IOW('T', 0x02, int) + #define SNDRV_TIMER_IOCTL_GINFO _IOWR('T', 0x03, struct snd_timer_ginfo) + #define SNDRV_TIMER_IOCTL_GPARAMS _IOW('T', 0x04, struct snd_timer_gparams) + #define SNDRV_TIMER_IOCTL_GSTATUS _IOWR('T', 0x05, struct snd_timer_gstatus) +@@ -785,6 +886,15 @@ + #define SNDRV_TIMER_IOCTL_STOP _IO('T', 0xa1) + #define SNDRV_TIMER_IOCTL_CONTINUE _IO('T', 0xa2) + #define SNDRV_TIMER_IOCTL_PAUSE _IO('T', 0xa3) ++#define SNDRV_TIMER_IOCTL_TREAD64 _IOW('T', 0xa4, int) ++ ++#if __BITS_PER_LONG == 64 ++#define SNDRV_TIMER_IOCTL_TREAD SNDRV_TIMER_IOCTL_TREAD_OLD ++#else ++#define SNDRV_TIMER_IOCTL_TREAD ((sizeof(__kernel_long_t) >= sizeof(time_t)) ? \ ++ SNDRV_TIMER_IOCTL_TREAD_OLD : \ ++ SNDRV_TIMER_IOCTL_TREAD64) ++#endif + + struct snd_timer_read { + unsigned int resolution; +@@ -810,11 +920,15 @@ + SNDRV_TIMER_EVENT_MRESUME = SNDRV_TIMER_EVENT_RESUME + 10, + }; + ++#ifndef __KERNEL__ + struct snd_timer_tread { + int event; ++ __time_pad pad1; + struct timespec tstamp; + unsigned int val; ++ __time_pad pad2; + }; ++#endif + + /**************************************************************************** + * * +@@ -955,8 +1069,7 @@ + } bytes; + struct snd_aes_iec958 iec958; + } value; /* RO */ +- struct timespec tstamp; +- unsigned char reserved[128-sizeof(struct timespec)]; ++ unsigned char reserved[128]; + }; + + struct snd_ctl_tlv { diff --git a/patches/linux-4.19.90/0101-archscripts.diff b/patches/linux-4.19.90/0101-archscripts.diff new file mode 100644 index 0000000..51e34d7 --- /dev/null +++ b/patches/linux-4.19.90/0101-archscripts.diff @@ -0,0 +1,11 @@ +--- linux-4.19.90.orig/Makefile 2019-12-17 14:36:04.000000000 -0500 ++++ linux-4.19.90/Makefile 2020-01-30 22:06:04.216550425 -0500 +@@ -1173,7 +1173,7 @@ + archscripts: + + PHONY += __headers +-__headers: $(version_h) scripts_basic uapi-asm-generic archheaders archscripts ++__headers: $(version_h) scripts_basic uapi-asm-generic archheaders + $(Q)$(MAKE) $(build)=scripts build_unifdef + + PHONY += headers_install_all diff --git a/patches/linux-5.8.5/0101-archscripts.diff b/patches/linux-5.8.5/0101-archscripts.diff new file mode 100644 index 0000000..da6f13c --- /dev/null +++ b/patches/linux-5.8.5/0101-archscripts.diff @@ -0,0 +1,14 @@ +diff -ur linux-5.8.5.orig/Makefile linux-5.8.5.tmp/Makefile +--- linux-5.8.5.orig/Makefile 2020-08-27 03:31:49.000000000 -0400 ++++ linux-5.8.5/Makefile 2020-08-28 19:00:50.980172582 -0400 +@@ -1253,7 +1253,7 @@ + hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj + + PHONY += headers +-headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders archscripts ++headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders + $(if $(wildcard $(srctree)/arch/$(SRCARCH)/include/uapi/asm/Kbuild),, \ + $(error Headers not exportable for the $(SRCARCH) architecture)) + $(Q)$(MAKE) $(hdr-inst)=include/uapi +Only in linux-5.8.5.tmp/: Makefile.orig +Only in linux-5.8.5.tmp/: Makefile.rej diff --git a/patches/linux-headers-4.19.88-1/0001-asound-time64.diff b/patches/linux-headers-4.19.88-1/0001-asound-time64.diff new file mode 100644 index 0000000..1a23259 --- /dev/null +++ b/patches/linux-headers-4.19.88-1/0001-asound-time64.diff @@ -0,0 +1,289 @@ +diff -ur a/generic/include/sound/asound.h b/generic/include/sound/asound.h +--- a/generic/include/sound/asound.h 2019-10-15 12:26:39.634141383 -0400 ++++ b/generic/include/sound/asound.h 2020-01-30 21:43:56.477450321 -0500 +@@ -35,6 +35,8 @@ + #include + #endif + ++#include ++ + /* + * protocol version + */ +@@ -154,7 +156,7 @@ + * * + *****************************************************************************/ + +-#define SNDRV_PCM_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 14) ++#define SNDRV_PCM_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 15) + + typedef unsigned long snd_pcm_uframes_t; + typedef signed long snd_pcm_sframes_t; +@@ -301,7 +303,9 @@ + #define SNDRV_PCM_INFO_DRAIN_TRIGGER 0x40000000 /* internal kernel flag - trigger in drain */ + #define SNDRV_PCM_INFO_FIFO_IN_FRAMES 0x80000000 /* internal kernel flag - FIFO size is in frames */ + +- ++#if (__BITS_PER_LONG == 32 && defined(__USE_TIME_BITS64)) || defined __KERNEL__ ++#define __SND_STRUCT_TIME64 ++#endif + + typedef int __bitwise snd_pcm_state_t; + #define SNDRV_PCM_STATE_OPEN ((__force snd_pcm_state_t) 0) /* stream is open */ +@@ -317,8 +321,17 @@ + + enum { + SNDRV_PCM_MMAP_OFFSET_DATA = 0x00000000, +- SNDRV_PCM_MMAP_OFFSET_STATUS = 0x80000000, +- SNDRV_PCM_MMAP_OFFSET_CONTROL = 0x81000000, ++ SNDRV_PCM_MMAP_OFFSET_STATUS_OLD = 0x80000000, ++ SNDRV_PCM_MMAP_OFFSET_CONTROL_OLD = 0x81000000, ++ SNDRV_PCM_MMAP_OFFSET_STATUS_NEW = 0x82000000, ++ SNDRV_PCM_MMAP_OFFSET_CONTROL_NEW = 0x83000000, ++#ifdef __SND_STRUCT_TIME64 ++ SNDRV_PCM_MMAP_OFFSET_STATUS = SNDRV_PCM_MMAP_OFFSET_STATUS_NEW, ++ SNDRV_PCM_MMAP_OFFSET_CONTROL = SNDRV_PCM_MMAP_OFFSET_CONTROL_NEW, ++#else ++ SNDRV_PCM_MMAP_OFFSET_STATUS = SNDRV_PCM_MMAP_OFFSET_STATUS_OLD, ++ SNDRV_PCM_MMAP_OFFSET_CONTROL = SNDRV_PCM_MMAP_OFFSET_CONTROL_OLD, ++#endif + }; + + union snd_pcm_sync_id { +@@ -456,8 +469,13 @@ + SNDRV_PCM_AUDIO_TSTAMP_TYPE_LAST = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED + }; + ++#ifndef __KERNEL__ ++/* explicit padding avoids incompatibility between i386 and x86-64 */ ++typedef struct { unsigned char pad[sizeof(time_t) - sizeof(int)] } __time_pad; ++ + struct snd_pcm_status { + snd_pcm_state_t state; /* stream state */ ++ __time_pad pad1; /* align to timespec */ + struct timespec trigger_tstamp; /* time when stream was started/stopped/paused */ + struct timespec tstamp; /* reference timestamp */ + snd_pcm_uframes_t appl_ptr; /* appl ptr */ +@@ -473,17 +491,48 @@ + __u32 audio_tstamp_accuracy; /* in ns units, only valid if indicated in audio_tstamp_data */ + unsigned char reserved[52-2*sizeof(struct timespec)]; /* must be filled with zero */ + }; ++#endif + +-struct snd_pcm_mmap_status { ++/* ++ * For mmap operations, we need the 64-bit layout, both for compat mode, ++ * and for y2038 compatibility. For 64-bit applications, the two definitions ++ * are identical, so we keep the traditional version. ++ */ ++#ifdef __SND_STRUCT_TIME64 ++#define __snd_pcm_mmap_status64 snd_pcm_mmap_status ++#define __snd_pcm_mmap_control64 snd_pcm_mmap_control ++#define __snd_pcm_sync_ptr64 snd_pcm_sync_ptr ++#ifdef __KERNEL__ ++#define __snd_timespec64 __kernel_timespec ++#else ++#define __snd_timespec64 timespec ++#endif ++struct __snd_timespec { ++ __s32 tv_sec; ++ __s32 tv_nsec; ++}; ++#else ++#define __snd_pcm_mmap_status snd_pcm_mmap_status ++#define __snd_pcm_mmap_control snd_pcm_mmap_control ++#define __snd_pcm_sync_ptr snd_pcm_sync_ptr ++#define __snd_timespec timespec ++struct __snd_timespec64 { ++ __s64 tv_sec; ++ __s64 tv_nsec; ++}; ++ ++#endif ++ ++struct __snd_pcm_mmap_status { + snd_pcm_state_t state; /* RO: state - SNDRV_PCM_STATE_XXXX */ + int pad1; /* Needed for 64 bit alignment */ + snd_pcm_uframes_t hw_ptr; /* RO: hw ptr (0...boundary-1) */ +- struct timespec tstamp; /* Timestamp */ ++ struct __snd_timespec tstamp; /* Timestamp */ + snd_pcm_state_t suspended_state; /* RO: suspended stream state */ +- struct timespec audio_tstamp; /* from sample counter or wall clock */ ++ struct __snd_timespec audio_tstamp; /* from sample counter or wall clock */ + }; + +-struct snd_pcm_mmap_control { ++struct __snd_pcm_mmap_control { + snd_pcm_uframes_t appl_ptr; /* RW: appl ptr (0...boundary-1) */ + snd_pcm_uframes_t avail_min; /* RW: min available frames for wakeup */ + }; +@@ -492,14 +541,59 @@ + #define SNDRV_PCM_SYNC_PTR_APPL (1<<1) /* get appl_ptr from driver (r/w op) */ + #define SNDRV_PCM_SYNC_PTR_AVAIL_MIN (1<<2) /* get avail_min from driver */ + +-struct snd_pcm_sync_ptr { ++struct __snd_pcm_sync_ptr { + unsigned int flags; + union { +- struct snd_pcm_mmap_status status; ++ struct __snd_pcm_mmap_status status; + unsigned char reserved[64]; + } s; + union { +- struct snd_pcm_mmap_control control; ++ struct __snd_pcm_mmap_control control; ++ unsigned char reserved[64]; ++ } c; ++}; ++ ++#if defined(__BYTE_ORDER) ? __BYTE_ORDER == __BIG_ENDIAN : defined(__BIG_ENDIAN) ++typedef char __pad_before_uframe[sizeof(__u64) - sizeof(snd_pcm_uframes_t)]; ++typedef char __pad_after_uframe[0]; ++#endif ++ ++#if defined(__BYTE_ORDER) ? __BYTE_ORDER == __LITTLE_ENDIAN : defined(__LITTLE_ENDIAN) ++typedef char __pad_before_uframe[0]; ++typedef char __pad_after_uframe[sizeof(__u64) - sizeof(snd_pcm_uframes_t)]; ++#endif ++ ++struct __snd_pcm_mmap_status64 { ++ __s32 state; /* RO: state - SNDRV_PCM_STATE_XXXX */ ++ __u32 pad1; /* Needed for 64 bit alignment */ ++ __pad_before_uframe __pad1; ++ snd_pcm_uframes_t hw_ptr; /* RO: hw ptr (0...boundary-1) */ ++ __pad_after_uframe __pad2; ++ struct __snd_timespec64 tstamp; /* Timestamp */ ++ __s32 suspended_state; /* RO: suspended stream state */ ++ __u32 pad3; /* Needed for 64 bit alignment */ ++ struct __snd_timespec64 audio_tstamp; /* sample counter or wall clock */ ++}; ++ ++struct __snd_pcm_mmap_control64 { ++ __pad_before_uframe __pad1; ++ snd_pcm_uframes_t appl_ptr; /* RW: appl ptr (0...boundary-1) */ ++ __pad_before_uframe __pad2; ++ ++ __pad_before_uframe __pad3; ++ snd_pcm_uframes_t avail_min; /* RW: min available frames for wakeup */ ++ __pad_after_uframe __pad4; ++}; ++ ++struct __snd_pcm_sync_ptr64 { ++ __u32 flags; ++ __u32 pad1; ++ union { ++ struct __snd_pcm_mmap_status64 status; ++ unsigned char reserved[64]; ++ } s; ++ union { ++ struct __snd_pcm_mmap_control64 control; + unsigned char reserved[64]; + } c; + }; +@@ -584,6 +678,8 @@ + #define SNDRV_PCM_IOCTL_STATUS _IOR('A', 0x20, struct snd_pcm_status) + #define SNDRV_PCM_IOCTL_DELAY _IOR('A', 0x21, snd_pcm_sframes_t) + #define SNDRV_PCM_IOCTL_HWSYNC _IO('A', 0x22) ++#define __SNDRV_PCM_IOCTL_SYNC_PTR _IOWR('A', 0x23, struct __snd_pcm_sync_ptr) ++#define __SNDRV_PCM_IOCTL_SYNC_PTR64 _IOWR('A', 0x23, struct __snd_pcm_sync_ptr64) + #define SNDRV_PCM_IOCTL_SYNC_PTR _IOWR('A', 0x23, struct snd_pcm_sync_ptr) + #define SNDRV_PCM_IOCTL_STATUS_EXT _IOWR('A', 0x24, struct snd_pcm_status) + #define SNDRV_PCM_IOCTL_CHANNEL_INFO _IOR('A', 0x32, struct snd_pcm_channel_info) +@@ -614,7 +710,7 @@ + * Raw MIDI section - /dev/snd/midi?? + */ + +-#define SNDRV_RAWMIDI_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 0) ++#define SNDRV_RAWMIDI_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 1) + + enum { + SNDRV_RAWMIDI_STREAM_OUTPUT = 0, +@@ -648,13 +744,16 @@ + unsigned char reserved[16]; /* reserved for future use */ + }; + ++#ifndef __KERNEL__ + struct snd_rawmidi_status { + int stream; ++ __time_pad pad1; + struct timespec tstamp; /* Timestamp */ + size_t avail; /* available bytes */ + size_t xruns; /* count of overruns since last status (in bytes) */ + unsigned char reserved[16]; /* reserved for future use */ + }; ++#endif + + #define SNDRV_RAWMIDI_IOCTL_PVERSION _IOR('W', 0x00, int) + #define SNDRV_RAWMIDI_IOCTL_INFO _IOR('W', 0x01, struct snd_rawmidi_info) +@@ -667,7 +766,7 @@ + * Timer section - /dev/snd/timer + */ + +-#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 6) ++#define SNDRV_TIMER_VERSION SNDRV_PROTOCOL_VERSION(2, 0, 7) + + enum { + SNDRV_TIMER_CLASS_NONE = -1, +@@ -761,6 +860,7 @@ + unsigned char reserved[60]; /* reserved */ + }; + ++#ifndef __KERNEL__ + struct snd_timer_status { + struct timespec tstamp; /* Timestamp - last update */ + unsigned int resolution; /* current period resolution in ns */ +@@ -769,10 +869,11 @@ + unsigned int queue; /* used queue size */ + unsigned char reserved[64]; /* reserved */ + }; ++#endif + + #define SNDRV_TIMER_IOCTL_PVERSION _IOR('T', 0x00, int) + #define SNDRV_TIMER_IOCTL_NEXT_DEVICE _IOWR('T', 0x01, struct snd_timer_id) +-#define SNDRV_TIMER_IOCTL_TREAD _IOW('T', 0x02, int) ++#define SNDRV_TIMER_IOCTL_TREAD_OLD _IOW('T', 0x02, int) + #define SNDRV_TIMER_IOCTL_GINFO _IOWR('T', 0x03, struct snd_timer_ginfo) + #define SNDRV_TIMER_IOCTL_GPARAMS _IOW('T', 0x04, struct snd_timer_gparams) + #define SNDRV_TIMER_IOCTL_GSTATUS _IOWR('T', 0x05, struct snd_timer_gstatus) +@@ -785,6 +886,15 @@ + #define SNDRV_TIMER_IOCTL_STOP _IO('T', 0xa1) + #define SNDRV_TIMER_IOCTL_CONTINUE _IO('T', 0xa2) + #define SNDRV_TIMER_IOCTL_PAUSE _IO('T', 0xa3) ++#define SNDRV_TIMER_IOCTL_TREAD64 _IOW('T', 0xa4, int) ++ ++#if __BITS_PER_LONG == 64 ++#define SNDRV_TIMER_IOCTL_TREAD SNDRV_TIMER_IOCTL_TREAD_OLD ++#else ++#define SNDRV_TIMER_IOCTL_TREAD ((sizeof(__kernel_long_t) >= sizeof(time_t)) ? \ ++ SNDRV_TIMER_IOCTL_TREAD_OLD : \ ++ SNDRV_TIMER_IOCTL_TREAD64) ++#endif + + struct snd_timer_read { + unsigned int resolution; +@@ -810,11 +920,15 @@ + SNDRV_TIMER_EVENT_MRESUME = SNDRV_TIMER_EVENT_RESUME + 10, + }; + ++#ifndef __KERNEL__ + struct snd_timer_tread { + int event; ++ __time_pad pad1; + struct timespec tstamp; + unsigned int val; ++ __time_pad pad2; + }; ++#endif + + /**************************************************************************** + * * +@@ -955,8 +1069,7 @@ + } bytes; + struct snd_aes_iec958 iec958; + } value; /* RO */ +- struct timespec tstamp; +- unsigned char reserved[128-sizeof(struct timespec)]; ++ unsigned char reserved[128]; + }; + + struct snd_ctl_tlv { diff --git a/patches/musl-1.2.0/0001-broken_arm_vdso.diff b/patches/musl-1.2.0/0001-broken_arm_vdso.diff new file mode 100644 index 0000000..dfe3961 --- /dev/null +++ b/patches/musl-1.2.0/0001-broken_arm_vdso.diff @@ -0,0 +1,17 @@ +diff --git a/arch/arm/syscall_arch.h b/arch/arm/syscall_arch.h +index 4b08762d..a877b2cf 100644 +--- a/arch/arm/syscall_arch.h ++++ b/arch/arm/syscall_arch.h +@@ -98,12 +98,6 @@ static inline long __syscall6(long n, long a, long b, long c, long d, long e, lo + __asm_syscall(R7_OPERAND, "0"(r0), "r"(r1), "r"(r2), "r"(r3), "r"(r4), "r"(r5)); + } + +-#define VDSO_USEFUL +-#define VDSO_CGT32_SYM "__vdso_clock_gettime" +-#define VDSO_CGT32_VER "LINUX_2.6" +-#define VDSO_CGT_SYM "__vdso_clock_gettime64" +-#define VDSO_CGT_VER "LINUX_2.6" +- + #define SYSCALL_FADVISE_6_ARG + + #define SYSCALL_IPC_BROKEN_MODE diff --git a/presets/j2-fdpic b/presets/j2-fdpic new file mode 100644 index 0000000..bd72ac3 --- /dev/null +++ b/presets/j2-fdpic @@ -0,0 +1,6 @@ +TARGET = sh2eb-linux-muslfdpic +GCC_CONFIG += --with-cpu=mj2 + +# Optional to produce a smaller toolchain: +# COMMON_CONFIG += --disable-nls +# GCC_CONFIG += --disable-libquadmath --disable-decimal-float diff --git a/presets/j2-pie-gplv2 b/presets/j2-pie-gplv2 new file mode 100644 index 0000000..6e6c7f9 --- /dev/null +++ b/presets/j2-pie-gplv2 @@ -0,0 +1,14 @@ +TARGET = sh2eb-linux-musl +GCC_CONFIG += --with-cpu=mj2 +GCC_CONFIG += --enable-default-pie + +# This configuration should be compatible with the old GPLv2 tools, +# but it is not regularly tested. Uncomment the following and remove +# the above --with-cpu=mj2 in order to try: +# GCC_VER = 4.2.1 +# BINUTILS_VER = 397a64b3 +# BINUTILS_SITE = http://landley.net/aboriginal/mirror + +# Optional to produce a smaller toolchain: +# COMMON_CONFIG += --disable-nls +# GCC_CONFIG += --disable-libquadmath --disable-decimal-float