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lw-everestlinux
2022-10-05 12:03:03 -04:00
commit 6e0177dfbf
225 changed files with 21395 additions and 0 deletions
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507
patches/binutils-2.25.1/0001-staticpie.diff Normal file
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@@ -0,0 +1,507 @@
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index bd4b576..41803c2 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -13786,7 +13786,7 @@ elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-bfin.c b/bfd/elf32-bfin.c
index 49ef360..8346d57 100644
--- a/bfd/elf32-bfin.c
+++ b/bfd/elf32-bfin.c
@@ -4257,7 +4257,7 @@ elf32_bfinfdpic_size_dynamic_sections (bfd *output_bfd,
if (htab->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-cr16.c b/bfd/elf32-cr16.c
index 5d8ffbc..497630e 100644
--- a/bfd/elf32-cr16.c
+++ b/bfd/elf32-cr16.c
@@ -2464,7 +2464,7 @@ _bfd_cr16_elf_size_dynamic_sections (bfd * output_bfd,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
#if 0
s = bfd_get_linker_section (dynobj, ".interp");
diff --git a/bfd/elf32-cris.c b/bfd/elf32-cris.c
index 3031173..5b40524 100644
--- a/bfd/elf32-cris.c
+++ b/bfd/elf32-cris.c
@@ -3764,7 +3764,7 @@ elf_cris_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-frv.c b/bfd/elf32-frv.c
index b55a7ab..ef72c23 100644
--- a/bfd/elf32-frv.c
+++ b/bfd/elf32-frv.c
@@ -5444,7 +5444,7 @@ elf32_frvfdpic_size_dynamic_sections (bfd *output_bfd,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-hppa.c b/bfd/elf32-hppa.c
index 41bf5c5..62c7cf6 100644
--- a/bfd/elf32-hppa.c
+++ b/bfd/elf32-hppa.c
@@ -2215,7 +2215,7 @@ elf32_hppa_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (htab->etab.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
sec = bfd_get_linker_section (dynobj, ".interp");
if (sec == NULL)
diff --git a/bfd/elf32-i370.c b/bfd/elf32-i370.c
index 7fba4d1..458f694 100644
--- a/bfd/elf32-i370.c
+++ b/bfd/elf32-i370.c
@@ -594,7 +594,7 @@ i370_elf_size_dynamic_sections (bfd *output_bfd,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-i386.c b/bfd/elf32-i386.c
index 7642d0f..b0844c8 100644
--- a/bfd/elf32-i386.c
+++ b/bfd/elf32-i386.c
@@ -2834,7 +2834,7 @@ elf_i386_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info)
if (htab->elf.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
if (s == NULL)
diff --git a/bfd/elf32-lm32.c b/bfd/elf32-lm32.c
index 23f6e5e..0805e3c 100644
--- a/bfd/elf32-lm32.c
+++ b/bfd/elf32-lm32.c
@@ -2141,7 +2141,7 @@ lm32_elf_size_dynamic_sections (bfd *output_bfd,
if (htab->root.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-m32r.c b/bfd/elf32-m32r.c
index 155d079..a2e3c7c 100644
--- a/bfd/elf32-m32r.c
+++ b/bfd/elf32-m32r.c
@@ -2170,7 +2170,7 @@ m32r_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (htab->root.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-m68k.c b/bfd/elf32-m68k.c
index 10d2fcb..489f3f1 100644
--- a/bfd/elf32-m68k.c
+++ b/bfd/elf32-m68k.c
@@ -3257,7 +3257,7 @@ elf_m68k_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-metag.c b/bfd/elf32-metag.c
index 9c54a71..755c431 100644
--- a/bfd/elf32-metag.c
+++ b/bfd/elf32-metag.c
@@ -2848,7 +2848,7 @@ elf_metag_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (htab->etab.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
if (s == NULL)
diff --git a/bfd/elf32-nios2.c b/bfd/elf32-nios2.c
index fd70007..2a2b3a6 100644
--- a/bfd/elf32-nios2.c
+++ b/bfd/elf32-nios2.c
@@ -5849,7 +5849,7 @@ nios2_elf32_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-or1k.c b/bfd/elf32-or1k.c
index d4f92b7..a1eba09 100644
--- a/bfd/elf32-or1k.c
+++ b/bfd/elf32-or1k.c
@@ -2447,7 +2447,7 @@ or1k_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (htab->root.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_section_by_name (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-ppc.c b/bfd/elf32-ppc.c
index 8415f1e..5597051 100644
--- a/bfd/elf32-ppc.c
+++ b/bfd/elf32-ppc.c
@@ -6191,7 +6191,7 @@ ppc_elf_size_dynamic_sections (bfd *output_bfd,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (htab->elf.dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-s390.c b/bfd/elf32-s390.c
index de37ca4..a1e628c 100644
--- a/bfd/elf32-s390.c
+++ b/bfd/elf32-s390.c
@@ -2039,7 +2039,7 @@ elf_s390_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (htab->elf.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
if (s == NULL)
diff --git a/bfd/elf32-sh.c b/bfd/elf32-sh.c
index 012ee4e..a51453f 100644
--- a/bfd/elf32-sh.c
+++ b/bfd/elf32-sh.c
@@ -3349,7 +3349,7 @@ sh_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (htab->root.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-tic6x.c b/bfd/elf32-tic6x.c
index b6640ea..380ab8d 100644
--- a/bfd/elf32-tic6x.c
+++ b/bfd/elf32-tic6x.c
@@ -3300,7 +3300,7 @@ elf32_tic6x_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info)
if (htab->elf.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
if (s == NULL)
diff --git a/bfd/elf32-tilepro.c b/bfd/elf32-tilepro.c
index cb3f896..d55be2d 100644
--- a/bfd/elf32-tilepro.c
+++ b/bfd/elf32-tilepro.c
@@ -2463,7 +2463,7 @@ tilepro_elf_size_dynamic_sections (bfd *output_bfd,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-vax.c b/bfd/elf32-vax.c
index 6089e8c..893ea8d 100644
--- a/bfd/elf32-vax.c
+++ b/bfd/elf32-vax.c
@@ -1124,7 +1124,7 @@ elf_vax_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info)
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-xtensa.c b/bfd/elf32-xtensa.c
index 73538cd..37ea5da 100644
--- a/bfd/elf32-xtensa.c
+++ b/bfd/elf32-xtensa.c
@@ -1637,7 +1637,7 @@ elf_xtensa_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
&& htab->sgotloc != NULL);
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
if (s == NULL)
diff --git a/bfd/elf64-alpha.c b/bfd/elf64-alpha.c
index f67b0af..1973cd0 100644
--- a/bfd/elf64-alpha.c
+++ b/bfd/elf64-alpha.c
@@ -2877,7 +2877,7 @@ elf64_alpha_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf64-hppa.c b/bfd/elf64-hppa.c
index 6f40b88..3b628b4 100644
--- a/bfd/elf64-hppa.c
+++ b/bfd/elf64-hppa.c
@@ -1558,7 +1558,7 @@ elf64_hppa_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info)
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
sec = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (sec != NULL);
diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c
index 8cff990..851845f 100644
--- a/bfd/elf64-ppc.c
+++ b/bfd/elf64-ppc.c
@@ -9748,7 +9748,7 @@ ppc64_elf_size_dynamic_sections (bfd *output_bfd,
if (htab->elf.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
if (s == NULL)
diff --git a/bfd/elf64-s390.c b/bfd/elf64-s390.c
index 2e505f3..406bb66 100644
--- a/bfd/elf64-s390.c
+++ b/bfd/elf64-s390.c
@@ -1989,7 +1989,7 @@ elf_s390_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (htab->elf.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
if (s == NULL)
diff --git a/bfd/elf64-sh64.c b/bfd/elf64-sh64.c
index e460895..d920598 100644
--- a/bfd/elf64-sh64.c
+++ b/bfd/elf64-sh64.c
@@ -3404,7 +3404,7 @@ sh64_elf64_size_dynamic_sections (bfd *output_bfd,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf64-x86-64.c b/bfd/elf64-x86-64.c
index f15d33e..870aadf 100644
--- a/bfd/elf64-x86-64.c
+++ b/bfd/elf64-x86-64.c
@@ -3181,7 +3181,7 @@ elf_x86_64_size_dynamic_sections (bfd *output_bfd,
if (htab->elf.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
if (s == NULL)
diff --git a/bfd/elflink.c b/bfd/elflink.c
index 7f04271..5b3438d 100644
--- a/bfd/elflink.c
+++ b/bfd/elflink.c
@@ -246,7 +246,7 @@ _bfd_elf_link_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
/* A dynamically linked executable has a .interp section, but a
shared library does not. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_make_section_anyway_with_flags (abfd, ".interp",
flags | SEC_READONLY);
@@ -5763,7 +5763,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
bfd_boolean all_defined;
*sinterpptr = bfd_get_linker_section (dynobj, ".interp");
- BFD_ASSERT (*sinterpptr != NULL || !info->executable);
+ BFD_ASSERT (*sinterpptr != NULL || !info->executable || info->nointerp);
if (soname != NULL)
{
diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c
index beedb70..599f9cf 100644
--- a/bfd/elfnn-aarch64.c
+++ b/bfd/elfnn-aarch64.c
@@ -7674,7 +7674,7 @@ elfNN_aarch64_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (htab->root.dynamic_sections_created)
{
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
if (s == NULL)
diff --git a/bfd/elfnn-ia64.c b/bfd/elfnn-ia64.c
index c45fa28..3b304d5 100644
--- a/bfd/elfnn-ia64.c
+++ b/bfd/elfnn-ia64.c
@@ -2992,7 +2992,7 @@ elfNN_ia64_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
/* Set the contents of the .interp section to the interpreter. */
if (ia64_info->root.dynamic_sections_created
- && info->executable)
+ && info->executable && !info->nointerp)
{
sec = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (sec != NULL);
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index be1e59a..329dec3 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -9579,7 +9579,7 @@ _bfd_mips_elf_size_dynamic_sections (bfd *output_bfd,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elfxx-sparc.c b/bfd/elfxx-sparc.c
index 9bb71a9..db0d4f1 100644
--- a/bfd/elfxx-sparc.c
+++ b/bfd/elfxx-sparc.c
@@ -2559,7 +2559,7 @@ _bfd_sparc_elf_size_dynamic_sections (bfd *output_bfd,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elfxx-tilegx.c b/bfd/elfxx-tilegx.c
index 59a2f7e..6f7485a 100644
--- a/bfd/elfxx-tilegx.c
+++ b/bfd/elfxx-tilegx.c
@@ -2724,7 +2724,7 @@ tilegx_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/include/bfdlink.h b/include/bfdlink.h
index 797a465..cf533dd 100644
--- a/include/bfdlink.h
+++ b/include/bfdlink.h
@@ -433,6 +433,9 @@ struct bfd_link_info
/* TRUE if BND prefix in PLT entries is always generated. */
unsigned int bndplt: 1;
+ /* TRUE if generation of .interp/PT_INTERP should be suppressed. */
+ unsigned int nointerp: 1;
+
/* Char that may appear as the first char of a symbol, but should be
skipped (like symbol_leading_char) when looking up symbols in
wrap_hash. Used by PowerPC Linux for 'dot' symbols. */
diff --git a/ld/ld.texinfo b/ld/ld.texinfo
index cf3b586..1e5e5cf 100644
--- a/ld/ld.texinfo
+++ b/ld/ld.texinfo
@@ -1426,6 +1426,13 @@ generating dynamically linked ELF executables. The default dynamic
linker is normally correct; don't use this unless you know what you are
doing.
+@kindex --no-dynamic-linker
+@item --no-dynamic-linker
+When producing an executable file, omit the request for a dynamic
+linker to be used at load-time. This is only meaningful for ELF
+executables that contain dynamic relocations, and usually requires
+entry point code that is capable of processing these relocations.
+
@kindex --fatal-warnings
@kindex --no-fatal-warnings
@item --fatal-warnings
diff --git a/ld/ldlex.h b/ld/ldlex.h
index 59bd14f..8b57f84 100644
--- a/ld/ldlex.h
+++ b/ld/ldlex.h
@@ -33,6 +33,7 @@ enum option_values
OPTION_DEFSYM,
OPTION_DEMANGLE,
OPTION_DYNAMIC_LINKER,
+ OPTION_NO_DYNAMIC_LINKER,
OPTION_SYSROOT,
OPTION_EB,
OPTION_EL,
diff --git a/ld/lexsup.c b/ld/lexsup.c
index 777d6e2..1b992f7 100644
--- a/ld/lexsup.c
+++ b/ld/lexsup.c
@@ -138,6 +138,9 @@ static const struct ld_option ld_options[] =
{ {"dynamic-linker", required_argument, NULL, OPTION_DYNAMIC_LINKER},
'I', N_("PROGRAM"), N_("Set PROGRAM as the dynamic linker to use"),
TWO_DASHES },
+ { {"no-dynamic-linker", no_argument, NULL, OPTION_NO_DYNAMIC_LINKER},
+ '\0', NULL, N_("Produce an executable with no program interpreter header"),
+ TWO_DASHES },
{ {"library", required_argument, NULL, 'l'},
'l', N_("LIBNAME"), N_("Search for library LIBNAME"), TWO_DASHES },
{ {"library-path", required_argument, NULL, 'L'},
@@ -762,6 +765,10 @@ parse_args (unsigned argc, char **argv)
case 'I': /* Used on Solaris. */
case OPTION_DYNAMIC_LINKER:
command_line.interpreter = optarg;
+ link_info.nointerp = 0;
+ break;
+ case OPTION_NO_DYNAMIC_LINKER:
+ link_info.nointerp = 1;
break;
case OPTION_SYSROOT:
/* Already handled in ldmain.c. */

640
patches/binutils-2.25.1/0002-cas.diff Normal file
View File

@@ -0,0 +1,640 @@
diff --git a/bfd/archures.c b/bfd/archures.c
index 51068b9..c67d76b 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -294,10 +294,12 @@ DESCRIPTION
.#define bfd_mach_sh_dsp 0x2d
.#define bfd_mach_sh2a 0x2a
.#define bfd_mach_sh2a_nofpu 0x2b
+.#define bfd_mach_shj2 0x2c
.#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
.#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
.#define bfd_mach_sh2a_or_sh4 0x2a3
.#define bfd_mach_sh2a_or_sh3e 0x2a4
+.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
.#define bfd_mach_sh2e 0x2e
.#define bfd_mach_sh3 0x30
.#define bfd_mach_sh3_nommu 0x31
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index ca0cafd..99e92c6 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -2109,10 +2109,12 @@ enum bfd_architecture
#define bfd_mach_sh_dsp 0x2d
#define bfd_mach_sh2a 0x2a
#define bfd_mach_sh2a_nofpu 0x2b
+#define bfd_mach_shj2 0x2c
#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
#define bfd_mach_sh2a_or_sh4 0x2a3
#define bfd_mach_sh2a_or_sh3e 0x2a4
+#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
#define bfd_mach_sh2e 0x2e
#define bfd_mach_sh3 0x30
#define bfd_mach_sh3_nommu 0x31
diff --git a/bfd/cpu-sh.c b/bfd/cpu-sh.c
index d516d66..66d21a5 100644
--- a/bfd/cpu-sh.c
+++ b/bfd/cpu-sh.c
@@ -44,7 +44,9 @@
#define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17
#define SH2A_OR_SH4_NEXT arch_info_struct + 18
#define SH2A_OR_SH3E_NEXT arch_info_struct + 19
-#define SH64_NEXT NULL
+#define SH64_NEXT arch_info_struct + 20
+#define SHJ2_NEXT arch_info_struct + 21
+#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT NULL
static const bfd_arch_info_type arch_info_struct[] =
{
@@ -348,6 +350,36 @@ static const bfd_arch_info_type arch_info_struct[] =
bfd_arch_default_fill,
SH64_NEXT
},
+ {
+ 32, /* 32 bits in a word. */
+ 32, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+ bfd_arch_sh,
+ bfd_mach_shj2,
+ "sh", /* Architecture name. . */
+ "j2", /* Machine name. */
+ 1,
+ FALSE, /* Not the default. */
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
+ SHJ2_NEXT
+ },
+ {
+ 32, /* 32 bits in a word. */
+ 32, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+ bfd_arch_sh,
+ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu,
+ "sh", /* Architecture name. . */
+ "sh2a-or-sh3e-or-j2", /* Machine name. */
+ 1,
+ FALSE, /* Not the default. */
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
+ SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT
+ },
};
const bfd_arch_info_type bfd_sh_arch =
@@ -398,6 +430,8 @@ static struct { unsigned long bfd_mach, arch, arch_up; } bfd_to_arch_table[] =
{ bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
{ bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
{ bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
+ { bfd_mach_shj2, arch_shj2, arch_shj2_up },
+ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
{ 0, 0, 0 } /* Terminator. */
};
diff --git a/binutils/readelf.c b/binutils/readelf.c
index a31db52..5ec21b0 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -3217,6 +3217,8 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
+ case EF_SHJ2: strcat (buf, ", j2"); break;
+ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
default: strcat (buf, _(", unknown ISA")); break;
}
diff --git a/gas/config/tc-sh.c b/gas/config/tc-sh.c
index 125f073..37f6fb0 100644
--- a/gas/config/tc-sh.c
+++ b/gas/config/tc-sh.c
@@ -1648,6 +1648,8 @@ get_operands (sh_opcode_info *info, char *args, sh_operand_info *operand)
ptr++;
}
get_operand (&ptr, operand + 2);
+ if (strcmp (info->name,"cas") == 0)
+ operand[2].type = A_IND_0;
}
else
{
@@ -2187,7 +2189,10 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
goto fail;
reg_m = 4;
break;
-
+ case A_IND_0:
+ if (user->reg != 0)
+ goto fail;
+ break;
default:
printf (_("unhandled %d\n"), arg);
goto fail;
diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
index cc29889..a3e18b5 100644
--- a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
+++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
@@ -12,7 +12,5 @@
sh2a_nofpu_or_sh3_nommu:
! Instructions introduced into sh2a-nofpu-or-sh3-nommu
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
! Instructions inherited from ancestors: sh sh2
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
index c702845..812aa76 100644
--- a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
+++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
@@ -12,7 +12,7 @@
sh2a_nofpu_or_sh4_nommu_nofpu:
! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -119,8 +119,8 @@ sh2a_nofpu_or_sh4_nommu_nofpu:
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
index 6f4a17e..5b38643 100644
--- a/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
+++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
@@ -64,7 +64,7 @@ sh2a_nofpu:
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -171,8 +171,8 @@ sh2a_nofpu:
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff --git a/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s b/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
index 25c8ae1..69d3536 100644
--- a/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
+++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
@@ -13,7 +13,7 @@ sh2a_or_sh3e:
! Instructions introduced into sh2a-or-sh3e
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -124,8 +124,8 @@ sh2a_or_sh3e:
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff --git a/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s b/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
index d3300ca..c697268 100644
--- a/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
+++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
@@ -39,7 +39,7 @@ sh2a_or_sh4:
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -150,8 +150,8 @@ sh2a_or_sh4:
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff --git a/gas/testsuite/gas/sh/arch/sh2a.s b/gas/testsuite/gas/sh/arch/sh2a.s
index 370dbd4..0d9f3b0 100644
--- a/gas/testsuite/gas/sh/arch/sh2a.s
+++ b/gas/testsuite/gas/sh/arch/sh2a.s
@@ -16,7 +16,7 @@ sh2a:
fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -140,8 +140,8 @@ sh2a:
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff --git a/gas/testsuite/gas/sh/arch/sh3-dsp.s b/gas/testsuite/gas/sh/arch/sh3-dsp.s
index acc26be..cfd4dfe 100644
--- a/gas/testsuite/gas/sh/arch/sh3-dsp.s
+++ b/gas/testsuite/gas/sh/arch/sh3-dsp.s
@@ -12,7 +12,7 @@
sh3_dsp:
! Instructions introduced into sh3-dsp
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -152,8 +152,8 @@ sh3_dsp:
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff --git a/gas/testsuite/gas/sh/arch/sh3-nommu.s b/gas/testsuite/gas/sh/arch/sh3-nommu.s
index 3e8ff02..dacaae1 100644
--- a/gas/testsuite/gas/sh/arch/sh3-nommu.s
+++ b/gas/testsuite/gas/sh/arch/sh3-nommu.s
@@ -26,7 +26,7 @@ sh3_nommu:
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -133,8 +133,8 @@ sh3_nommu:
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff --git a/gas/testsuite/gas/sh/arch/sh3.s b/gas/testsuite/gas/sh/arch/sh3.s
index 97ab939..aa70fc3 100644
--- a/gas/testsuite/gas/sh/arch/sh3.s
+++ b/gas/testsuite/gas/sh/arch/sh3.s
@@ -13,7 +13,7 @@ sh3:
! Instructions introduced into sh3
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -128,8 +128,8 @@ sh3:
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff --git a/gas/testsuite/gas/sh/arch/sh3e.s b/gas/testsuite/gas/sh/arch/sh3e.s
index f5c8ab9..215e5ec 100644
--- a/gas/testsuite/gas/sh/arch/sh3e.s
+++ b/gas/testsuite/gas/sh/arch/sh3e.s
@@ -12,7 +12,7 @@
sh3e:
! Instructions introduced into sh3e
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -132,8 +132,8 @@ sh3e:
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff --git a/gas/testsuite/gas/sh/arch/sh4-nofpu.s b/gas/testsuite/gas/sh/arch/sh4-nofpu.s
index 32b58f9..1fef035 100644
--- a/gas/testsuite/gas/sh/arch/sh4-nofpu.s
+++ b/gas/testsuite/gas/sh/arch/sh4-nofpu.s
@@ -12,7 +12,7 @@
sh4_nofpu:
! Instructions introduced into sh4-nofpu
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -136,8 +136,8 @@ sh4_nofpu:
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff --git a/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s b/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
index 61f0bc6..65d11c5 100644
--- a/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
+++ b/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
@@ -24,7 +24,7 @@ sh4_nommu_nofpu:
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -139,8 +139,8 @@ sh4_nommu_nofpu:
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff --git a/gas/testsuite/gas/sh/arch/sh4.s b/gas/testsuite/gas/sh/arch/sh4.s
index af135ce..dc199cb 100644
--- a/gas/testsuite/gas/sh/arch/sh4.s
+++ b/gas/testsuite/gas/sh/arch/sh4.s
@@ -17,7 +17,7 @@ sh4:
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -145,8 +145,8 @@ sh4:
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff --git a/gas/testsuite/gas/sh/arch/sh4a-nofpu.s b/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
index 9522bb6..7581f47 100644
--- a/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
+++ b/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
@@ -19,7 +19,7 @@ sh4a_nofpu:
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -143,8 +143,8 @@ sh4a_nofpu:
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff --git a/gas/testsuite/gas/sh/arch/sh4a.s b/gas/testsuite/gas/sh/arch/sh4a.s
index 950ed2d..55e9611 100644
--- a/gas/testsuite/gas/sh/arch/sh4a.s
+++ b/gas/testsuite/gas/sh/arch/sh4a.s
@@ -13,7 +13,7 @@ sh4a:
! Instructions introduced into sh4a
fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -147,8 +147,8 @@ sh4a:
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff --git a/gas/testsuite/gas/sh/arch/sh4al-dsp.s b/gas/testsuite/gas/sh/arch/sh4al-dsp.s
index 6caaf2c..fde6c1e 100644
--- a/gas/testsuite/gas/sh/arch/sh4al-dsp.s
+++ b/gas/testsuite/gas/sh/arch/sh4al-dsp.s
@@ -48,7 +48,7 @@ sh4al_dsp:
dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -202,8 +202,8 @@ sh4al_dsp:
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff --git a/include/elf/sh.h b/include/elf/sh.h
index a54158f..109d90f 100644
--- a/include/elf/sh.h
+++ b/include/elf/sh.h
@@ -35,6 +35,7 @@
#define EF_SH2E 11
#define EF_SH4A 12
#define EF_SH2A 13
+#define EF_SHJ2 14
#define EF_SH4_NOFPU 16
#define EF_SH4A_NOFPU 17
@@ -46,6 +47,7 @@
#define EF_SH2A_SH3_NOFPU 22
#define EF_SH2A_SH4 23
#define EF_SH2A_SH3E 24
+#define EF_SH2A_SH3_SHJ2 25
/* This one can only mix in objects from other EF_SH5 objects. */
#define EF_SH5 10
@@ -68,7 +70,8 @@
/* EF_SH2E */ bfd_mach_sh2e , \
/* EF_SH4A */ bfd_mach_sh4a , \
/* EF_SH2A */ bfd_mach_sh2a , \
-/* 14, 15 */ 0, 0, \
+/* EF_SHJ2 */ bfd_mach_shj2 , \
+/* 15 */ 0, \
/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
@@ -77,7 +80,8 @@
/* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
/* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
/* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
+/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
+/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
/* Convert arch_sh* into EF_SH*. */
int sh_find_elf_flags (unsigned int arch_set);
diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c
index d4e1a6d..181e21a 100644
--- a/opcodes/sh-dis.c
+++ b/opcodes/sh-dis.c
@@ -868,6 +868,9 @@ print_insn_sh (bfd_vma memaddr, struct disassemble_info *info)
case XMTRX_M4:
fprintf_fn (stream, "xmtrx");
break;
+ case A_IND_0:
+ fprintf_fn (stream, "@r0");
+ break;
default:
abort ();
}
diff --git a/opcodes/sh-opc.h b/opcodes/sh-opc.h
index 5863aa9..19c5a61 100644
--- a/opcodes/sh-opc.h
+++ b/opcodes/sh-opc.h
@@ -187,7 +187,8 @@ typedef enum
FPUL_N,
FPUL_M,
FPSCR_N,
- FPSCR_M
+ FPSCR_M,
+ A_IND_0
}
sh_arg_type;
@@ -214,9 +215,11 @@ sh_dsp_reg_nums;
#define arch_sh4_base (1 << 5)
#define arch_sh4a_base (1 << 6)
#define arch_sh2a_base (1 << 7)
-#define arch_sh_base_mask MASK (0, 7)
+#define arch_shj2_base (1 << 8)
+#define arch_sh2a_sh3_shj2_base (1 << 9)
+#define arch_sh_base_mask MASK (0, 9)
-/* Bits 8 ... 24 are currently free. */
+/* Bits 10 ... 24 are currently free. */
/* This is an annotation on instruction types, but we
abuse the arch field in instructions to denote it. */
@@ -254,6 +257,8 @@ sh_dsp_reg_nums;
#define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
#define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
#define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
+#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
@@ -319,7 +324,8 @@ SH4AL-dsp SH4A
#define arch_sh2_up (arch_sh2 \
| arch_sh2e_up \
| arch_sh2a_nofpu_or_sh3_nommu_up \
- | arch_sh_dsp_up)
+ | arch_sh_dsp_up \
+ | arch_shj2_up)
#define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
| arch_sh2a_or_sh3e_up \
@@ -345,6 +351,12 @@ SH4AL-dsp SH4A
#define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
| arch_sh4a_up \
| arch_sh4al_dsp_up)
+#define arch_shj2_up ( arch_shj2)
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
+ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
+ | arch_sh2a_or_sh3e_up \
+ | arch_sh3_nommu_up \
+ | arch_shj2_up)
/* Right branches. */
#define arch_sh2e_up (arch_sh2e \
@@ -713,9 +725,9 @@ const sh_opcode_info sh_table[] =
/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
+/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
+/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
@@ -1193,7 +1205,7 @@ const sh_opcode_info sh_table[] =
{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
-
+ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
{ 0, {0}, {0}, 0 }
};

48
patches/binutils-2.25.1/0003-shemuls.diff Normal file
View File

@@ -0,0 +1,48 @@
diff -ur ../baseline/binutils-2.25.1/bfd/config.bfd binutils-2.25.1/bfd/config.bfd
--- ../baseline/binutils-2.25.1/bfd/config.bfd 2014-10-14 07:32:02.000000000 +0000
+++ binutils-2.25.1/bfd/config.bfd 2015-09-04 19:24:08.678337083 +0000
@@ -1370,6 +1370,7 @@
sh-*-linux*)
targ_defvec=sh_elf32_linux_be_vec
targ_selvecs="sh_elf32_linux_vec sh64_elf32_linux_vec sh64_elf32_linux_be_vec sh64_elf64_linux_vec sh64_elf64_linux_be_vec"
+ targ_selvecs="${targ_selvecs} sh_elf32_vec sh_elf32_le_vec sh_elf32_fdpic_le_vec sh_elf32_fdpic_be_vec"
want64=true
;;
#endif /* BFD64 */
@@ -1377,10 +1378,12 @@
sh*eb-*-linux*)
targ_defvec=sh_elf32_linux_be_vec
targ_selvecs=sh_elf32_linux_vec
+ targ_selvecs="${targ_selvecs} sh_elf32_vec sh_elf32_le_vec sh_elf32_fdpic_le_vec sh_elf32_fdpic_be_vec"
;;
sh*-*-linux*)
targ_defvec=sh_elf32_linux_vec
targ_selvecs=sh_elf32_linux_be_vec
+ targ_selvecs="${targ_selvecs} sh_elf32_vec sh_elf32_le_vec sh_elf32_fdpic_le_vec sh_elf32_fdpic_be_vec"
;;
sh-*-uclinux* | sh[12]-*-uclinux*)
diff -ur ../baseline/binutils-2.25.1/ld/configure.tgt binutils-2.25.1/ld/configure.tgt
--- ../baseline/binutils-2.25.1/ld/configure.tgt 2014-10-14 07:32:04.000000000 +0000
+++ binutils-2.25.1/ld/configure.tgt 2015-09-04 19:22:05.151677949 +0000
@@ -623,15 +623,17 @@
score-*-elf) targ_emul=score7_elf
targ_extra_emuls=score3_elf ;;
sh-*-linux*) targ_emul=shlelf_linux
- targ_extra_emuls=shelf_linux
+ targ_extra_emuls="shelf_linux shlelf_fd shelf_fd shlelf shelf"
targ_extra_libpath=shelf_linux ;;
sh64eb-*-linux*) targ_emul=shelf32_linux
targ_extra_emuls="shlelf32_linux" ;;
sh64-*-linux*) targ_emul=shlelf32_linux
targ_extra_emuls="shelf32_linux"
targ_extra_libpath=shelf32_linux ;;
-sh*eb-*-linux*) targ_emul=shelf_linux ;;
-sh*-*-linux*) targ_emul=shlelf_linux ;;
+sh*eb-*-linux*) targ_emul=shelf_linux
+ targ_extra_emuls="shelf_fd shelf" ;;
+sh*-*-linux*) targ_emul=shlelf_linux
+ targ_extra_emuls="shlelf_fd shlelf" ;;
sh5le-*-netbsd*) targ_emul=shlelf32_nbsd
targ_extra_emuls="shelf32_nbsd shelf64_nbsd shlelf64_nbsd shelf_nbsd shlelf_nbsd" ;;
sh5-*-netbsd*) targ_emul=shelf32_nbsd

21
patches/binutils-2.25.1/0004-shfdpicflag.diff Normal file
View File

@@ -0,0 +1,21 @@
diff -ur binutils-2.25.1.orig/bfd/elf32-sh.c binutils-2.25.1/bfd/elf32-sh.c
--- binutils-2.25.1.orig/bfd/elf32-sh.c 2015-09-03 21:52:17.000000000 +0000
+++ binutils-2.25.1/bfd/elf32-sh.c 2015-09-14 17:08:48.114426847 +0000
@@ -5487,7 +5487,7 @@
input_bfd, input_section, rel->r_offset, symname);
}
- elf_elfheader (output_bfd)->e_flags &= ~EF_SH_PIC;
+ elf_elfheader (output_bfd)->e_flags |= EF_SH_PIC;
}
if (r != bfd_reloc_ok)
@@ -6644,7 +6644,7 @@
elf_elfheader (obfd)->e_flags = elf_elfheader (ibfd)->e_flags;
sh_elf_set_mach_from_flags (obfd);
if (elf_elfheader (obfd)->e_flags & EF_SH_FDPIC)
- elf_elfheader (obfd)->e_flags |= EF_SH_PIC;
+ elf_elfheader (obfd)->e_flags &= ~EF_SH_PIC;
}
if (! sh_merge_bfd_arch (ibfd, obfd))

11
patches/binutils-2.25.1/0005-shfdpicgot.diff Normal file
View File

@@ -0,0 +1,11 @@
--- binutils-2.25.1/bfd/elf32-sh.c.orig 2015-10-08 16:33:04.413334344 +0000
+++ binutils-2.25.1/bfd/elf32-sh.c 2015-10-08 16:23:05.709980166 +0000
@@ -3604,7 +3604,7 @@ sh_elf_size_dynamic_sections (bfd *outpu
return FALSE;
}
else if ((elf_elfheader (output_bfd)->e_flags & EF_SH_FDPIC)
- && htab->sgot->size != 0)
+ /* && htab->sgot->size != 0 */)
{
if (! add_dynamic_entry (DT_PLTGOT, 0))
return FALSE;

12
patches/binutils-2.25.1/0006-mbbadsymindx.diff Normal file
View File

@@ -0,0 +1,12 @@
--- binutils-2.25.1/bfd/elf32-microblaze.c.orig 2016-02-11 23:12:00.301992882 +0000
+++ binutils-2.25.1/bfd/elf32-microblaze.c 2016-02-11 23:28:12.043074209 +0000
@@ -3293,8 +3293,7 @@
The entry in the global offset table will already have been
initialized in the relocate_section function. */
if (info->shared
- && (info->symbolic || h->dynindx == -1)
- && h->def_regular)
+ && ((info->symbolic && h->def_regular) || h->dynindx == -1))
{
asection *sec = h->root.u.def.section;
microblaze_elf_output_dynamic_relocation (output_bfd,

21
patches/binutils-2.25.1/0007-tcarm.diff Normal file
View File

@@ -0,0 +1,21 @@
From d840c081f8082e8b9e63fead5306643975a97bb3 Mon Sep 17 00:00:00 2001
From: Richard Earnshaw <Richard.Earnshaw@arm.com>
Date: Thu, 20 Nov 2014 17:02:47 +0000
Subject: [PATCH] * config/tc-arm.c (rotate_left): Avoid undefined behaviour
when N = 0.
---
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 5077f87..9100fb2 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7251,7 +7251,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
/* Functions for operand encoding. ARM, then Thumb. */
-#define rotate_left(v, n) (v << n | v >> (32 - n))
+#define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
/* If VAL can be encoded in the immediate field of an ARM instruction,
return the encoded form. Otherwise, return FAIL. */

21
patches/binutils-2.25.1/0008-mips-pie-tls.diff Normal file
View File

@@ -0,0 +1,21 @@
diff -ur binutils-2.25.1.orig/bfd/elfxx-mips.c binutils-2.25.1/bfd/elfxx-mips.c
--- binutils-2.25.1.orig/bfd/elfxx-mips.c 2018-01-31 11:26:12.000000000 -0500
+++ binutils-2.25.1/bfd/elfxx-mips.c 2018-01-31 12:16:00.179841734 -0500
@@ -3228,7 +3228,7 @@
&& (!info->shared || !SYMBOL_REFERENCES_LOCAL (info, h)))
indx = h->dynindx;
- if ((info->shared || indx != 0)
+ if ((!info->executable || indx != 0)
&& (h == NULL
|| ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|| h->root.type != bfd_link_hash_undefweak))
@@ -3338,7 +3338,7 @@
if (entry->tls_initialized)
return;
- if ((info->shared || indx != 0)
+ if ((!info->executable || indx != 0)
&& (h == NULL
|| ELF_ST_VISIBILITY (h->root.other) == STV_DEFAULT
|| h->root.type != bfd_link_hash_undefweak))

47
patches/binutils-2.25.1/0009-arm-pie-tls.diff Normal file
View File

@@ -0,0 +1,47 @@
--- binutils-2.25.1/bfd/elf32-arm.c.orig 2019-10-06 20:40:39.213623570 -0400
+++ binutils-2.25.1/bfd/elf32-arm.c 2019-10-06 20:45:09.688207243 -0400
@@ -4097,7 +4097,7 @@
{
int is_local = (h == NULL);
- if (info->shared || (h && h->root.type == bfd_link_hash_undefweak))
+ if (!info->executable || (h && h->root.type == bfd_link_hash_undefweak))
return r_type;
/* We do not support relaxations for Old TLS models. */
@@ -9493,7 +9493,7 @@
{
/* If we don't know the module number, create a relocation
for it. */
- if (info->shared)
+ if (!info->executable)
{
Elf_Internal_Rela outrel;
@@ -9581,7 +9581,7 @@
now, and emit any relocations. If both an IE GOT and a
GD GOT are necessary, we emit the GD first. */
- if ((info->shared || indx != 0)
+ if ((!info->executable || indx != 0)
&& (h == NULL
|| ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|| h->root.type != bfd_link_hash_undefweak))
@@ -9597,7 +9597,7 @@
/* We should have relaxed, unless this is an undefined
weak symbol. */
BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
- || info->shared);
+ || !info->executable);
BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
<= globals->root.sgotplt->size);
@@ -13504,7 +13504,7 @@
indx = h->dynindx;
if (tls_type != GOT_NORMAL
- && (info->shared || indx != 0)
+ && (!info->executable || indx != 0)
&& (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|| h->root.type != bfd_link_hash_undefweak))
{

16
patches/binutils-2.25.1/0010-arm-tlsdesc-64bithost.diff Normal file
View File

@@ -0,0 +1,16 @@
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index bb53e039e3..d52c046979 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -12027,9 +12027,9 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
unsigned long data, insn;
unsigned thumb;
- data = bfd_get_32 (input_bfd, hit_data);
+ data = bfd_get_signed_32 (input_bfd, hit_data);
thumb = data & 1;
- data &= ~1u;
+ data &= ~1ul;
if (thumb)
{

617
patches/binutils-2.27/0001-j2.diff Normal file
View File

@@ -0,0 +1,617 @@
diff -ur binutils-2.27.orig/bfd/archures.c binutils-2.27/bfd/archures.c
--- binutils-2.27.orig/bfd/archures.c 2016-08-03 03:36:50.000000000 -0400
+++ binutils-2.27/bfd/archures.c 2016-11-06 22:13:54.556453406 -0500
@@ -310,10 +310,12 @@
.#define bfd_mach_sh_dsp 0x2d
.#define bfd_mach_sh2a 0x2a
.#define bfd_mach_sh2a_nofpu 0x2b
+.#define bfd_mach_shj2 0x2c
.#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
.#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
.#define bfd_mach_sh2a_or_sh4 0x2a3
.#define bfd_mach_sh2a_or_sh3e 0x2a4
+.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
.#define bfd_mach_sh2e 0x2e
.#define bfd_mach_sh3 0x30
.#define bfd_mach_sh3_nommu 0x31
diff -ur binutils-2.27.orig/bfd/bfd-in2.h binutils-2.27/bfd/bfd-in2.h
--- binutils-2.27.orig/bfd/bfd-in2.h 2016-08-03 03:36:50.000000000 -0400
+++ binutils-2.27/bfd/bfd-in2.h 2016-11-06 22:13:54.562451813 -0500
@@ -2121,10 +2121,12 @@
#define bfd_mach_sh_dsp 0x2d
#define bfd_mach_sh2a 0x2a
#define bfd_mach_sh2a_nofpu 0x2b
+#define bfd_mach_shj2 0x2c
#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
#define bfd_mach_sh2a_or_sh4 0x2a3
#define bfd_mach_sh2a_or_sh3e 0x2a4
+#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
#define bfd_mach_sh2e 0x2e
#define bfd_mach_sh3 0x30
#define bfd_mach_sh3_nommu 0x31
diff -ur binutils-2.27.orig/bfd/cpu-sh.c binutils-2.27/bfd/cpu-sh.c
--- binutils-2.27.orig/bfd/cpu-sh.c 2016-08-03 03:36:50.000000000 -0400
+++ binutils-2.27/bfd/cpu-sh.c 2016-11-06 22:13:54.562451813 -0500
@@ -44,7 +44,9 @@
#define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17
#define SH2A_OR_SH4_NEXT arch_info_struct + 18
#define SH2A_OR_SH3E_NEXT arch_info_struct + 19
-#define SH64_NEXT NULL
+#define SH64_NEXT arch_info_struct + 20
+#define SHJ2_NEXT arch_info_struct + 21
+#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT NULL
static const bfd_arch_info_type arch_info_struct[] =
{
@@ -348,6 +350,36 @@
bfd_arch_default_fill,
SH64_NEXT
},
+ {
+ 32, /* 32 bits in a word. */
+ 32, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+ bfd_arch_sh,
+ bfd_mach_shj2,
+ "sh", /* Architecture name. . */
+ "j2", /* Machine name. */
+ 1,
+ FALSE, /* Not the default. */
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
+ SHJ2_NEXT
+ },
+ {
+ 32, /* 32 bits in a word. */
+ 32, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+ bfd_arch_sh,
+ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu,
+ "sh", /* Architecture name. . */
+ "sh2a-or-sh3e-or-j2", /* Machine name. */
+ 1,
+ FALSE, /* Not the default. */
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
+ SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT
+ },
};
const bfd_arch_info_type bfd_sh_arch =
@@ -398,6 +430,8 @@
{ bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
{ bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
{ bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
+ { bfd_mach_shj2, arch_shj2, arch_shj2_up },
+ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
{ 0, 0, 0 } /* Terminator. */
};
diff -ur binutils-2.27.orig/binutils/readelf.c binutils-2.27/binutils/readelf.c
--- binutils-2.27.orig/binutils/readelf.c 2016-08-03 03:36:51.000000000 -0400
+++ binutils-2.27/binutils/readelf.c 2016-11-06 22:13:54.571449425 -0500
@@ -3307,6 +3307,8 @@
case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
+ case EF_SHJ2: strcat (buf, ", j2"); break;
+ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
default: strcat (buf, _(", unknown ISA")); break;
}
diff -ur binutils-2.27.orig/gas/config/tc-sh.c binutils-2.27/gas/config/tc-sh.c
--- binutils-2.27.orig/gas/config/tc-sh.c 2016-08-03 03:36:51.000000000 -0400
+++ binutils-2.27/gas/config/tc-sh.c 2016-11-06 22:13:54.575448363 -0500
@@ -1648,6 +1648,8 @@
ptr++;
}
get_operand (&ptr, operand + 2);
+ if (strcmp (info->name,"cas") == 0)
+ operand[2].type = A_IND_0;
}
else
{
@@ -2187,7 +2189,10 @@
goto fail;
reg_m = 4;
break;
-
+ case A_IND_0:
+ if (user->reg != 0)
+ goto fail;
+ break;
default:
printf (_("unhandled %d\n"), arg);
goto fail;
diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2015-11-13 03:27:41.000000000 -0500
+++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2016-11-06 22:13:54.576448097 -0500
@@ -12,8 +12,6 @@
sh2a_nofpu_or_sh3_nommu:
! Instructions introduced into sh2a-nofpu-or-sh3-nommu
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
! Instructions inherited from ancestors: sh sh2
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2015-11-13 03:27:41.000000000 -0500
+++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2016-11-06 22:13:54.576448097 -0500
@@ -12,7 +12,7 @@
sh2a_nofpu_or_sh4_nommu_nofpu:
! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -119,8 +119,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2015-11-13 03:27:41.000000000 -0500
+++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2016-11-06 22:13:54.577447832 -0500
@@ -64,7 +64,7 @@
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -171,8 +171,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2015-11-13 03:27:41.000000000 -0500
+++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2016-11-06 22:13:54.578447567 -0500
@@ -13,7 +13,7 @@
! Instructions introduced into sh2a-or-sh3e
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -124,8 +124,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2015-11-13 03:27:41.000000000 -0500
+++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2016-11-06 22:13:54.579447301 -0500
@@ -39,7 +39,7 @@
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -150,8 +150,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.27/gas/testsuite/gas/sh/arch/sh2a.s
--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh2a.s 2015-11-13 03:27:41.000000000 -0500
+++ binutils-2.27/gas/testsuite/gas/sh/arch/sh2a.s 2016-11-06 22:13:54.579447301 -0500
@@ -16,7 +16,7 @@
fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -140,8 +140,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.27/gas/testsuite/gas/sh/arch/sh3-dsp.s
--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s 2015-11-13 03:27:41.000000000 -0500
+++ binutils-2.27/gas/testsuite/gas/sh/arch/sh3-dsp.s 2016-11-06 22:13:54.580447036 -0500
@@ -12,7 +12,7 @@
sh3_dsp:
! Instructions introduced into sh3-dsp
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -152,8 +152,8 @@
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh3-nommu.s
--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s 2015-11-13 03:27:41.000000000 -0500
+++ binutils-2.27/gas/testsuite/gas/sh/arch/sh3-nommu.s 2016-11-06 22:13:54.581446771 -0500
@@ -26,7 +26,7 @@
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -133,8 +133,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.27/gas/testsuite/gas/sh/arch/sh3.s
--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3.s 2015-11-13 03:27:41.000000000 -0500
+++ binutils-2.27/gas/testsuite/gas/sh/arch/sh3.s 2016-11-06 22:13:54.581446771 -0500
@@ -13,7 +13,7 @@
! Instructions introduced into sh3
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -128,8 +128,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.27/gas/testsuite/gas/sh/arch/sh3e.s
--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh3e.s 2015-11-13 03:27:41.000000000 -0500
+++ binutils-2.27/gas/testsuite/gas/sh/arch/sh3e.s 2016-11-06 22:13:54.582446505 -0500
@@ -12,7 +12,7 @@
sh3e:
! Instructions introduced into sh3e
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -132,8 +132,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4-nofpu.s
--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2015-11-13 03:27:41.000000000 -0500
+++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2016-11-06 22:13:54.583446240 -0500
@@ -12,7 +12,7 @@
sh4_nofpu:
! Instructions introduced into sh4-nofpu
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -136,8 +136,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2015-11-13 03:27:41.000000000 -0500
+++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2016-11-06 22:13:54.583446240 -0500
@@ -24,7 +24,7 @@
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -139,8 +139,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4.s
--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4.s 2015-11-13 03:27:41.000000000 -0500
+++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4.s 2016-11-06 22:13:54.584445974 -0500
@@ -17,7 +17,7 @@
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -145,8 +145,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2015-11-13 03:27:41.000000000 -0500
+++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2016-11-06 22:13:54.584445974 -0500
@@ -19,7 +19,7 @@
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -143,8 +143,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4a.s
--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4a.s 2015-11-13 03:27:41.000000000 -0500
+++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4a.s 2016-11-06 22:13:54.585445709 -0500
@@ -13,7 +13,7 @@
! Instructions introduced into sh4a
fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -147,8 +147,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.27/gas/testsuite/gas/sh/arch/sh4al-dsp.s
--- binutils-2.27.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2015-11-13 03:27:41.000000000 -0500
+++ binutils-2.27/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2016-11-06 22:13:54.586445443 -0500
@@ -48,7 +48,7 @@
dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -202,8 +202,8 @@
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.27.orig/include/elf/sh.h binutils-2.27/include/elf/sh.h
--- binutils-2.27.orig/include/elf/sh.h 2016-08-03 03:36:53.000000000 -0400
+++ binutils-2.27/include/elf/sh.h 2016-11-06 22:13:54.586445443 -0500
@@ -39,6 +39,7 @@
#define EF_SH2E 11
#define EF_SH4A 12
#define EF_SH2A 13
+#define EF_SHJ2 14
#define EF_SH4_NOFPU 16
#define EF_SH4A_NOFPU 17
@@ -50,6 +51,7 @@
#define EF_SH2A_SH3_NOFPU 22
#define EF_SH2A_SH4 23
#define EF_SH2A_SH3E 24
+#define EF_SH2A_SH3_SHJ2 25
/* This one can only mix in objects from other EF_SH5 objects. */
#define EF_SH5 10
@@ -72,7 +74,8 @@
/* EF_SH2E */ bfd_mach_sh2e , \
/* EF_SH4A */ bfd_mach_sh4a , \
/* EF_SH2A */ bfd_mach_sh2a , \
-/* 14, 15 */ 0, 0, \
+/* EF_SHJ2 */ bfd_mach_shj2 , \
+/* 15 */ 0, \
/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
@@ -81,7 +84,8 @@
/* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
/* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
/* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
+/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
+/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
/* Convert arch_sh* into EF_SH*. */
int sh_find_elf_flags (unsigned int arch_set);
diff -ur binutils-2.27.orig/opcodes/sh-dis.c binutils-2.27/opcodes/sh-dis.c
--- binutils-2.27.orig/opcodes/sh-dis.c 2016-08-03 03:36:55.000000000 -0400
+++ binutils-2.27/opcodes/sh-dis.c 2016-11-06 22:13:54.587445178 -0500
@@ -868,6 +868,9 @@
case XMTRX_M4:
fprintf_fn (stream, "xmtrx");
break;
+ case A_IND_0:
+ fprintf_fn (stream, "@r0");
+ break;
default:
abort ();
}
diff -ur binutils-2.27.orig/opcodes/sh-opc.h binutils-2.27/opcodes/sh-opc.h
--- binutils-2.27.orig/opcodes/sh-opc.h 2016-08-03 03:36:55.000000000 -0400
+++ binutils-2.27/opcodes/sh-opc.h 2016-11-06 22:13:54.588444913 -0500
@@ -191,7 +191,8 @@
FPUL_N,
FPUL_M,
FPSCR_N,
- FPSCR_M
+ FPSCR_M,
+ A_IND_0
}
sh_arg_type;
@@ -218,9 +219,11 @@
#define arch_sh4_base (1 << 5)
#define arch_sh4a_base (1 << 6)
#define arch_sh2a_base (1 << 7)
-#define arch_sh_base_mask MASK (0, 7)
+#define arch_shj2_base (1 << 8)
+#define arch_sh2a_sh3_shj2_base (1 << 9)
+#define arch_sh_base_mask MASK (0, 9)
-/* Bits 8 ... 24 are currently free. */
+/* Bits 10 ... 24 are currently free. */
/* This is an annotation on instruction types, but we
abuse the arch field in instructions to denote it. */
@@ -258,6 +261,8 @@
#define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
#define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
#define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
+#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
@@ -323,7 +328,8 @@
#define arch_sh2_up (arch_sh2 \
| arch_sh2e_up \
| arch_sh2a_nofpu_or_sh3_nommu_up \
- | arch_sh_dsp_up)
+ | arch_sh_dsp_up \
+ | arch_shj2_up)
#define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
| arch_sh2a_or_sh3e_up \
@@ -349,6 +355,12 @@
#define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
| arch_sh4a_up \
| arch_sh4al_dsp_up)
+#define arch_shj2_up ( arch_shj2)
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
+ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
+ | arch_sh2a_or_sh3e_up \
+ | arch_sh3_nommu_up \
+ | arch_shj2_up)
/* Right branches. */
#define arch_sh2e_up (arch_sh2e \
@@ -717,9 +729,9 @@
/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
+/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
+/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
@@ -1197,7 +1209,7 @@
{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
-
+ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
{ 0, {0}, {0}, 0 }
};

364
patches/binutils-2.27/0002-pr17739-sh-gc-sections-bug.diff Normal file
View File

@@ -0,0 +1,364 @@
From a94d834c9d0108f0bb50ddc311554d1bed320f54 Mon Sep 17 00:00:00 2001
From: Nick Clifton <nickc@redhat.com>
Date: Tue, 2 Aug 2016 11:56:55 +0100
Subject: [PATCH] Fix SH GOT allocation in the presence of linker garbage collection.
PR ld/17739
ld * emulparams/shelf.sh (CHECK_RELOCS_AFTER_OPEN_INPUT): Define with
valye 'yes'.
* emulparams/shelf32.sh: Likewise.
* emulparams/shelf32.sh: Likewise.
* emulparams/shelf_nto.sh: Likewise.
* emulparams/shelf_nto.sh: Likewise.
* emulparams/shelf_vxworks.sh: Likewise.
* emulparams/shelf_vxworks.sh: Likewise.
* emulparams/shlelf32_linux.sh: Likewise.
* emulparams/shlelf32_linux.sh: Likewise.
* emulparams/shlelf_linux.sh: Likewise.
* emulparams/shlelf_linux.sh: Likewise.
* emulparams/shlelf_nto.sh: Likewise.
* emulparams/shlelf_nto.sh: Likewise.
bfd * elf32-sh.c (sh_elf_gc_sweep_hook): Delete.
(elf_backend_sweep_hook): Delete.
---
bfd/elf32-sh.c | 215 ---------------------------------------
ld/emulparams/shelf.sh | 3 +
ld/emulparams/shelf32.sh | 3 +
ld/emulparams/shelf_nto.sh | 3 +
ld/emulparams/shelf_vxworks.sh | 4 +
ld/emulparams/shlelf32_linux.sh | 4 +-
ld/emulparams/shlelf_linux.sh | 3 +
ld/emulparams/shlelf_nto.sh | 3 +
10 files changed, 46 insertions(+), 216 deletions(-)
diff --git a/bfd/elf32-sh.c b/bfd/elf32-sh.c
index 52a5fd1..84c5b1e 100644
--- a/bfd/elf32-sh.c
+++ b/bfd/elf32-sh.c
@@ -5682,220 +5682,6 @@ sh_elf_gc_mark_hook (asection *sec,
return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
}
-/* Update the got entry reference counts for the section being removed. */
-
-static bfd_boolean
-sh_elf_gc_sweep_hook (bfd *abfd, struct bfd_link_info *info,
- asection *sec, const Elf_Internal_Rela *relocs)
-{
- Elf_Internal_Shdr *symtab_hdr;
- struct elf_link_hash_entry **sym_hashes;
- bfd_signed_vma *local_got_refcounts;
- union gotref *local_funcdesc;
- const Elf_Internal_Rela *rel, *relend;
-
- if (bfd_link_relocatable (info))
- return TRUE;
-
- elf_section_data (sec)->local_dynrel = NULL;
-
- symtab_hdr = &elf_symtab_hdr (abfd);
- sym_hashes = elf_sym_hashes (abfd);
- local_got_refcounts = elf_local_got_refcounts (abfd);
- local_funcdesc = sh_elf_local_funcdesc (abfd);
-
- relend = relocs + sec->reloc_count;
- for (rel = relocs; rel < relend; rel++)
- {
- unsigned long r_symndx;
- unsigned int r_type;
- struct elf_link_hash_entry *h = NULL;
-#ifdef INCLUDE_SHMEDIA
- int seen_stt_datalabel = 0;
-#endif
-
- r_symndx = ELF32_R_SYM (rel->r_info);
- if (r_symndx >= symtab_hdr->sh_info)
- {
- struct elf_sh_link_hash_entry *eh;
- struct elf_sh_dyn_relocs **pp;
- struct elf_sh_dyn_relocs *p;
-
- h = sym_hashes[r_symndx - symtab_hdr->sh_info];
- while (h->root.type == bfd_link_hash_indirect
- || h->root.type == bfd_link_hash_warning)
- {
-#ifdef INCLUDE_SHMEDIA
- seen_stt_datalabel |= h->type == STT_DATALABEL;
-#endif
- h = (struct elf_link_hash_entry *) h->root.u.i.link;
- }
- eh = (struct elf_sh_link_hash_entry *) h;
- for (pp = &eh->dyn_relocs; (p = *pp) != NULL; pp = &p->next)
- if (p->sec == sec)
- {
- /* Everything must go for SEC. */
- *pp = p->next;
- break;
- }
- }
-
- r_type = ELF32_R_TYPE (rel->r_info);
- switch (sh_elf_optimized_tls_reloc (info, r_type, h != NULL))
- {
- case R_SH_TLS_LD_32:
- if (sh_elf_hash_table (info)->tls_ldm_got.refcount > 0)
- sh_elf_hash_table (info)->tls_ldm_got.refcount -= 1;
- break;
-
- case R_SH_GOT32:
- case R_SH_GOT20:
- case R_SH_GOTOFF:
- case R_SH_GOTOFF20:
- case R_SH_GOTPC:
-#ifdef INCLUDE_SHMEDIA
- case R_SH_GOT_LOW16:
- case R_SH_GOT_MEDLOW16:
- case R_SH_GOT_MEDHI16:
- case R_SH_GOT_HI16:
- case R_SH_GOT10BY4:
- case R_SH_GOT10BY8:
- case R_SH_GOTOFF_LOW16:
- case R_SH_GOTOFF_MEDLOW16:
- case R_SH_GOTOFF_MEDHI16:
- case R_SH_GOTOFF_HI16:
- case R_SH_GOTPC_LOW16:
- case R_SH_GOTPC_MEDLOW16:
- case R_SH_GOTPC_MEDHI16:
- case R_SH_GOTPC_HI16:
-#endif
- case R_SH_TLS_GD_32:
- case R_SH_TLS_IE_32:
- case R_SH_GOTFUNCDESC:
- case R_SH_GOTFUNCDESC20:
- if (h != NULL)
- {
-#ifdef INCLUDE_SHMEDIA
- if (seen_stt_datalabel)
- {
- struct elf_sh_link_hash_entry *eh;
- eh = (struct elf_sh_link_hash_entry *) h;
- if (eh->datalabel_got.refcount > 0)
- eh->datalabel_got.refcount -= 1;
- }
- else
-#endif
- if (h->got.refcount > 0)
- h->got.refcount -= 1;
- }
- else if (local_got_refcounts != NULL)
- {
-#ifdef INCLUDE_SHMEDIA
- if (rel->r_addend & 1)
- {
- if (local_got_refcounts[symtab_hdr->sh_info + r_symndx] > 0)
- local_got_refcounts[symtab_hdr->sh_info + r_symndx] -= 1;
- }
- else
-#endif
- if (local_got_refcounts[r_symndx] > 0)
- local_got_refcounts[r_symndx] -= 1;
- }
- break;
-
- case R_SH_FUNCDESC:
- if (h != NULL)
- sh_elf_hash_entry (h)->abs_funcdesc_refcount -= 1;
- else if (sh_elf_hash_table (info)->fdpic_p && !bfd_link_pic (info))
- sh_elf_hash_table (info)->srofixup->size -= 4;
-
- /* Fall through. */
-
- case R_SH_GOTOFFFUNCDESC:
- case R_SH_GOTOFFFUNCDESC20:
- if (h != NULL)
- sh_elf_hash_entry (h)->funcdesc.refcount -= 1;
- else
- local_funcdesc[r_symndx].refcount -= 1;
- break;
-
- case R_SH_DIR32:
- if (sh_elf_hash_table (info)->fdpic_p && !bfd_link_pic (info)
- && (sec->flags & SEC_ALLOC) != 0)
- sh_elf_hash_table (info)->srofixup->size -= 4;
- /* Fall thru */
-
- case R_SH_REL32:
- if (bfd_link_pic (info))
- break;
- /* Fall thru */
-
- case R_SH_PLT32:
-#ifdef INCLUDE_SHMEDIA
- case R_SH_PLT_LOW16:
- case R_SH_PLT_MEDLOW16:
- case R_SH_PLT_MEDHI16:
- case R_SH_PLT_HI16:
-#endif
- if (h != NULL)
- {
- if (h->plt.refcount > 0)
- h->plt.refcount -= 1;
- }
- break;
-
- case R_SH_GOTPLT32:
-#ifdef INCLUDE_SHMEDIA
- case R_SH_GOTPLT_LOW16:
- case R_SH_GOTPLT_MEDLOW16:
- case R_SH_GOTPLT_MEDHI16:
- case R_SH_GOTPLT_HI16:
- case R_SH_GOTPLT10BY4:
- case R_SH_GOTPLT10BY8:
-#endif
- if (h != NULL)
- {
- struct elf_sh_link_hash_entry *eh;
- eh = (struct elf_sh_link_hash_entry *) h;
- if (eh->gotplt_refcount > 0)
- {
- eh->gotplt_refcount -= 1;
- if (h->plt.refcount > 0)
- h->plt.refcount -= 1;
- }
-#ifdef INCLUDE_SHMEDIA
- else if (seen_stt_datalabel)
- {
- if (eh->datalabel_got.refcount > 0)
- eh->datalabel_got.refcount -= 1;
- }
-#endif
- else if (h->got.refcount > 0)
- h->got.refcount -= 1;
- }
- else if (local_got_refcounts != NULL)
- {
-#ifdef INCLUDE_SHMEDIA
- if (rel->r_addend & 1)
- {
- if (local_got_refcounts[symtab_hdr->sh_info + r_symndx] > 0)
- local_got_refcounts[symtab_hdr->sh_info + r_symndx] -= 1;
- }
- else
-#endif
- if (local_got_refcounts[r_symndx] > 0)
- local_got_refcounts[r_symndx] -= 1;
- }
- break;
-
- default:
- break;
- }
- }
-
- return TRUE;
-}
-
/* Copy the extra info we tack onto an elf_link_hash_entry. */
static void
@@ -7455,7 +7241,6 @@ sh_elf_encode_eh_address (bfd *abfd,
sh_elf_merge_private_data
#define elf_backend_gc_mark_hook sh_elf_gc_mark_hook
-#define elf_backend_gc_sweep_hook sh_elf_gc_sweep_hook
#define elf_backend_check_relocs sh_elf_check_relocs
#define elf_backend_copy_indirect_symbol \
sh_elf_copy_indirect_symbol
diff --git a/ld/emulparams/shelf.sh b/ld/emulparams/shelf.sh
index 83680a6..d3f4752 100644
--- a/ld/emulparams/shelf.sh
+++ b/ld/emulparams/shelf.sh
@@ -11,6 +11,9 @@ MACHINE=
TEMPLATE_NAME=elf32
GENERATE_SHLIB_SCRIPT=yes
EMBEDDED=yes
+# PR 17739. Delay checking relocs until after all files have
+# been opened and linker garbage collection has taken place.
+CHECK_RELOCS_AFTER_OPEN_INPUT=yes
# These are for compatibility with the COFF toolchain.
ENTRY=start
diff --git a/ld/emulparams/shelf32.sh b/ld/emulparams/shelf32.sh
index 966bd30..bf362c5 100644
--- a/ld/emulparams/shelf32.sh
+++ b/ld/emulparams/shelf32.sh
@@ -11,6 +11,9 @@ ALIGNMENT=8
TEMPLATE_NAME=elf32
GENERATE_SHLIB_SCRIPT=yes
EMBEDDED=yes
+# PR 17739. Delay checking relocs until after all files have
+# been opened and linker garbage collection has taken place.
+CHECK_RELOCS_AFTER_OPEN_INPUT=yes
DATA_START_SYMBOLS='PROVIDE (___data = .);'
diff --git a/ld/emulparams/shelf_nto.sh b/ld/emulparams/shelf_nto.sh
index c4d71aa..46efd87 100644
--- a/ld/emulparams/shelf_nto.sh
+++ b/ld/emulparams/shelf_nto.sh
@@ -9,3 +9,6 @@ TEMPLATE_NAME=elf32
GENERATE_SHLIB_SCRIPT=yes
TEXT_START_SYMBOLS='_btext = .;'
ENTRY=_start
+# PR 17739. Delay checking relocs until after all files have
+# been opened and linker garbage collection has taken place.
+CHECK_RELOCS_AFTER_OPEN_INPUT=yes
diff --git a/ld/emulparams/shelf_vxworks.sh b/ld/emulparams/shelf_vxworks.sh
index 77619cb..759ffac 100644
--- a/ld/emulparams/shelf_vxworks.sh
+++ b/ld/emulparams/shelf_vxworks.sh
@@ -14,6 +14,10 @@ TEMPLATE_NAME=elf32
GENERATE_SHLIB_SCRIPT=yes
ENTRY=__start
SYMPREFIX=_
+# PR 17739. Delay checking relocs until after all files have
+# been opened and linker garbage collection has taken place.
+CHECK_RELOCS_AFTER_OPEN_INPUT=yes
+
GOT=".got ${RELOCATING-0} : {
PROVIDE(__GLOBAL_OFFSET_TABLE_ = .);
*(.got.plt) *(.got) }"
diff --git a/ld/emulparams/shlelf32_linux.sh b/ld/emulparams/shlelf32_linux.sh
index 81aea39..0327e57 100644
--- a/ld/emulparams/shlelf32_linux.sh
+++ b/ld/emulparams/shlelf32_linux.sh
@@ -13,7 +13,9 @@ ALIGNMENT=8
TEMPLATE_NAME=elf32
GENERATE_SHLIB_SCRIPT=yes
GENERATE_PIE_SCRIPT=yes
-
+# PR 17739. Delay checking relocs until after all files have
+# been opened and linker garbage collection has taken place.
+CHECK_RELOCS_AFTER_OPEN_INPUT=yes
DATA_START_SYMBOLS='PROVIDE (___data = .);'
diff --git a/ld/emulparams/shlelf_linux.sh b/ld/emulparams/shlelf_linux.sh
index c14aae2..4e2a581 100644
--- a/ld/emulparams/shlelf_linux.sh
+++ b/ld/emulparams/shlelf_linux.sh
@@ -12,6 +12,9 @@ MACHINE=
TEMPLATE_NAME=elf32
GENERATE_SHLIB_SCRIPT=yes
GENERATE_PIE_SCRIPT=yes
+# PR 17739. Delay checking relocs until after all files have
+# been opened and linker garbage collection has taken place.
+CHECK_RELOCS_AFTER_OPEN_INPUT=yes
DATA_START_SYMBOLS='PROVIDE (__data_start = .);';
diff --git a/ld/emulparams/shlelf_nto.sh b/ld/emulparams/shlelf_nto.sh
index 16f6508..f8ffc13 100644
--- a/ld/emulparams/shlelf_nto.sh
+++ b/ld/emulparams/shlelf_nto.sh
@@ -9,3 +9,6 @@ TEMPLATE_NAME=elf32
GENERATE_SHLIB_SCRIPT=yes
TEXT_START_SYMBOLS='_btext = .;'
ENTRY=_start
+# PR 17739. Delay checking relocs until after all files have
+# been opened and linker garbage collection has taken place.
+CHECK_RELOCS_AFTER_OPEN_INPUT=yes
--
1.7.1

10
patches/binutils-2.27/0003-microblaze-pr21017.diff Normal file
View File

@@ -0,0 +1,10 @@
--- binutils-2.27/bfd/elf32-microblaze.c.orig 2017-01-02 15:44:42.110115295 -0500
+++ binutils-2.27/bfd/elf32-microblaze.c 2017-01-02 15:43:22.768999626 -0500
@@ -2399,6 +2399,7 @@
tls_type |= (TLS_TLS | TLS_LD);
dogottls:
sec->has_tls_reloc = 1;
+ case R_MICROBLAZE_GOTOFF_64:
case R_MICROBLAZE_GOT_64:
if (htab->sgot == NULL)
{

21
patches/binutils-2.27/0004-mips-pie-tls.diff Normal file
View File

@@ -0,0 +1,21 @@
diff -ur binutils-2.27.orig/bfd/elfxx-mips.c binutils-2.27/bfd/elfxx-mips.c
--- binutils-2.27.orig/bfd/elfxx-mips.c 2016-08-03 03:36:51.000000000 -0400
+++ binutils-2.27/bfd/elfxx-mips.c 2018-01-31 12:11:22.458824584 -0500
@@ -3242,7 +3242,7 @@
&& (!bfd_link_pic (info) || !SYMBOL_REFERENCES_LOCAL (info, h)))
indx = h->dynindx;
- if ((bfd_link_pic (info) || indx != 0)
+ if ((bfd_link_dll (info) || indx != 0)
&& (h == NULL
|| ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|| h->root.type != bfd_link_hash_undefweak))
@@ -3354,7 +3354,7 @@
if (entry->tls_initialized)
return;
- if ((bfd_link_pic (info) || indx != 0)
+ if ((bfd_link_dll (info) || indx != 0)
&& (h == NULL
|| ELF_ST_VISIBILITY (h->root.other) == STV_DEFAULT
|| h->root.type != bfd_link_hash_undefweak))

21
patches/binutils-2.27/0005-mips-reproducible.patch Normal file
View File

@@ -0,0 +1,21 @@
[PATCH] fix deterministic output for mips archiver
for historical reasons mips uses a slightly different archive format,
and when the --enable-deterministic-archives option was implemented,
it was only done for the generic archive format, but not for the one
used by mips.
Signed-off-by: John Spencer <maillist-binutils@barfooze.de>
--- binutils-2.24.90.org/bfd/archive64.c
+++ binutils-2.24.90/bfd/archive64.c
@@ -171,7 +171,8 @@
if (!_bfd_ar_sizepad (hdr.ar_size, sizeof (hdr.ar_size), mapsize))
return FALSE;
_bfd_ar_spacepad (hdr.ar_date, sizeof (hdr.ar_date), "%ld",
- time (NULL));
+ ((arch->flags & BFD_DETERMINISTIC_OUTPUT) == 0
+ ? time (NULL) : 0));
/* This, at least, is what Intel coff sets the values to.: */
_bfd_ar_spacepad (hdr.ar_uid, sizeof (hdr.ar_uid), "%ld", 0);
_bfd_ar_spacepad (hdr.ar_gid, sizeof (hdr.ar_gid), "%ld", 0);

83
patches/binutils-2.27/0006-arm-pie-tls.diff Normal file
View File

@@ -0,0 +1,83 @@
From 7d6e280a0f3b9978b0edb20173d067d071531a3d Mon Sep 17 00:00:00 2001
From: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date: Wed, 2 Oct 2019 19:46:46 +0100
Subject: [PATCH] [PR ld/22263][PR ld/25056] arm: Avoid dynamic TLS relocs in
PIE
Dynamic relocs are only needed in an executable for TLS symbols if
those are defined in an external module and even then TLS access
can be relaxed to use IE model instead of GD.
Several bfd_link_pic checks are turned into bfd_link_dll checks
to fix TLS handling in PIE, for the same fix some other targets
used !bfd_link_executable checks, but that includes relocatable
objects so dll seems safer (in most cases either should work, since
dynamic relocations are not applied in relocatable objects).
On arm* fixes
FAIL: Build pr22263-1
bfd/
2019-10-02 Szabolcs Nagy <szabolcs.nagy@arm.com>
PR ld/22263
PR ld/25056
* elf32-arm.c (elf32_arm_tls_transition): Use bfd_link_dll instead of
bfd_link_pic for TLS checks.
(elf32_arm_final_link_relocate): Likewise.
(allocate_dynrelocs_for_symbol): Likewise.
---
bfd/elf32-arm.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index bb53e039e3..451949d278 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -4914,7 +4914,7 @@ elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
{
int is_local = (h == NULL);
- if (bfd_link_pic (info)
+ if (bfd_link_dll (info)
|| (h && h->root.type == bfd_link_hash_undefweak))
return r_type;
@@ -11700,7 +11700,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
{
/* If we don't know the module number, create a relocation
for it. */
- if (bfd_link_pic (info))
+ if (bfd_link_dll (info))
{
Elf_Internal_Rela outrel;
@@ -11804,7 +11804,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
now, and emit any relocations. If both an IE GOT and a
GD GOT are necessary, we emit the GD first. */
- if ((bfd_link_pic (info) || indx != 0)
+ if ((bfd_link_dll (info) || indx != 0)
&& (h == NULL
|| (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
&& !resolved_to_zero)
@@ -11821,7 +11821,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
/* We should have relaxed, unless this is an undefined
weak symbol. */
BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
- || bfd_link_pic (info));
+ || bfd_link_dll (info));
BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
<= globals->root.sgotplt->size);
@@ -16494,7 +16494,7 @@ allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
indx = h->dynindx;
if (tls_type != GOT_NORMAL
- && (bfd_link_pic (info) || indx != 0)
+ && (bfd_link_dll (info) || indx != 0)
&& (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|| h->root.type != bfd_link_hash_undefweak))
{
--
2.17.1

16
patches/binutils-2.27/0007-arm-tlsdesc-64bithost.diff Normal file
View File

@@ -0,0 +1,16 @@
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index bb53e039e3..d52c046979 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -12027,9 +12027,9 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
unsigned long data, insn;
unsigned thumb;
- data = bfd_get_32 (input_bfd, hit_data);
+ data = bfd_get_signed_32 (input_bfd, hit_data);
thumb = data & 1;
- data &= ~1u;
+ data &= ~1ul;
if (thumb)
{

620
patches/binutils-2.32/0001-j2.diff Normal file
View File

@@ -0,0 +1,620 @@
diff -ur binutils-2.32.orig/bfd/archures.c binutils-2.32/bfd/archures.c
--- binutils-2.32.orig/bfd/archures.c 2019-01-19 11:01:32.000000000 -0500
+++ binutils-2.32/bfd/archures.c 2019-05-26 15:09:15.968501965 -0400
@@ -298,6 +298,8 @@
.#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
.#define bfd_mach_sh2a_or_sh4 0x2a3
.#define bfd_mach_sh2a_or_sh3e 0x2a4
+.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
+.#define bfd_mach_shj2 0x2c
.#define bfd_mach_sh2e 0x2e
.#define bfd_mach_sh3 0x30
.#define bfd_mach_sh3_nommu 0x31
Only in binutils-2.32/bfd: archures.c.orig
Only in binutils-2.32/bfd: archures.c.rej
diff -ur binutils-2.32.orig/bfd/bfd-in2.h binutils-2.32/bfd/bfd-in2.h
--- binutils-2.32.orig/bfd/bfd-in2.h 2019-01-19 11:01:32.000000000 -0500
+++ binutils-2.32/bfd/bfd-in2.h 2019-05-26 15:10:21.005775819 -0400
@@ -2197,6 +2197,8 @@
#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
#define bfd_mach_sh2a_or_sh4 0x2a3
#define bfd_mach_sh2a_or_sh3e 0x2a4
+#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
+#define bfd_mach_shj2 0x2c
#define bfd_mach_sh2e 0x2e
#define bfd_mach_sh3 0x30
#define bfd_mach_sh3_nommu 0x31
Only in binutils-2.32/bfd: bfd-in2.h.orig
Only in binutils-2.32/bfd: bfd-in2.h.rej
diff -ur binutils-2.32.orig/bfd/cpu-sh.c binutils-2.32/bfd/cpu-sh.c
--- binutils-2.32.orig/bfd/cpu-sh.c 2019-01-19 11:01:32.000000000 -0500
+++ binutils-2.32/bfd/cpu-sh.c 2019-05-26 15:13:00.461455381 -0400
@@ -43,7 +43,10 @@
#define SH2A_NOFPU_OR_SH4_NOMMU_NOFPU_NEXT arch_info_struct + 16
#define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17
#define SH2A_OR_SH4_NEXT arch_info_struct + 18
-#define SH2A_OR_SH3E_NEXT NULL
+#define SH2A_OR_SH3E_NEXT arch_info_struct + 19
+#define SHJ2_NEXT arch_info_struct + 20
+#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT NULL
+
static const bfd_arch_info_type arch_info_struct[] =
{
@@ -332,6 +335,36 @@
bfd_arch_default_fill,
SH2A_OR_SH3E_NEXT
},
+ {
+ 32, /* 32 bits in a word. */
+ 32, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+ bfd_arch_sh,
+ bfd_mach_shj2,
+ "sh", /* Architecture name. . */
+ "j2", /* Machine name. */
+ 1,
+ FALSE, /* Not the default. */
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
+ SHJ2_NEXT
+ },
+ {
+ 32, /* 32 bits in a word. */
+ 32, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+ bfd_arch_sh,
+ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu,
+ "sh", /* Architecture name. . */
+ "sh2a-or-sh3e-or-j2", /* Machine name. */
+ 1,
+ FALSE, /* Not the default. */
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
+ SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT
+ },
};
const bfd_arch_info_type bfd_sh_arch =
@@ -382,6 +415,8 @@
{ bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
{ bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
{ bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
+ { bfd_mach_shj2, arch_shj2, arch_shj2_up },
+ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
{ 0, 0, 0 } /* Terminator. */
};
Only in binutils-2.32/bfd: cpu-sh.c.orig
Only in binutils-2.32/bfd: cpu-sh.c.rej
diff -ur binutils-2.32.orig/binutils/readelf.c binutils-2.32/binutils/readelf.c
--- binutils-2.32.orig/binutils/readelf.c 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/binutils/readelf.c 2019-05-26 15:07:03.563950564 -0400
@@ -3528,6 +3528,8 @@
case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
+ case EF_SHJ2: strcat (buf, ", j2"); break;
+ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
default: strcat (buf, _(", unknown ISA")); break;
}
Only in binutils-2.32/binutils: readelf.c.orig
diff -ur binutils-2.32.orig/gas/config/tc-sh.c binutils-2.32/gas/config/tc-sh.c
--- binutils-2.32.orig/gas/config/tc-sh.c 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/config/tc-sh.c 2019-05-26 15:07:03.567950581 -0400
@@ -1251,6 +1251,8 @@
ptr++;
}
get_operand (&ptr, operand + 2);
+ if (strcmp (info->name,"cas") == 0)
+ operand[2].type = A_IND_0;
}
else
{
@@ -1790,7 +1792,10 @@
goto fail;
reg_m = 4;
break;
-
+ case A_IND_0:
+ if (user->reg != 0)
+ goto fail;
+ break;
default:
printf (_("unhandled %d\n"), arg);
goto fail;
Only in binutils-2.32/gas/config: tc-sh.c.orig
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2019-05-26 15:07:03.568950585 -0400
@@ -12,8 +12,6 @@
sh2a_nofpu_or_sh3_nommu:
! Instructions introduced into sh2a-nofpu-or-sh3-nommu
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
! Instructions inherited from ancestors: sh sh2
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2019-05-26 15:07:03.570950593 -0400
@@ -12,7 +12,7 @@
sh2a_nofpu_or_sh4_nommu_nofpu:
! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -119,8 +119,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2019-05-26 15:07:03.571950597 -0400
@@ -64,7 +64,7 @@
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -171,8 +171,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2019-05-26 15:07:03.572950601 -0400
@@ -13,7 +13,7 @@
! Instructions introduced into sh2a-or-sh3e
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -124,8 +124,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2019-05-26 15:07:03.574950610 -0400
@@ -39,7 +39,7 @@
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -150,8 +150,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a.s 2019-05-26 15:07:03.575950614 -0400
@@ -16,7 +16,7 @@
fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -140,8 +140,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3-dsp.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3-dsp.s 2019-05-26 15:07:03.577950622 -0400
@@ -12,7 +12,7 @@
sh3_dsp:
! Instructions introduced into sh3-dsp
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -152,8 +152,8 @@
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3-nommu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3-nommu.s 2019-05-26 15:07:03.578950626 -0400
@@ -26,7 +26,7 @@
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -133,8 +133,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3.s 2019-05-26 15:07:03.579950630 -0400
@@ -13,7 +13,7 @@
! Instructions introduced into sh3
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -128,8 +128,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3e.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3e.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3e.s 2019-05-26 15:07:03.581950639 -0400
@@ -12,7 +12,7 @@
sh3e:
! Instructions introduced into sh3e
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -132,8 +132,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nofpu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2019-05-26 15:07:03.582950643 -0400
@@ -12,7 +12,7 @@
sh4_nofpu:
! Instructions introduced into sh4-nofpu
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -136,8 +136,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2019-05-26 15:07:03.583950647 -0400
@@ -24,7 +24,7 @@
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -139,8 +139,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4.s 2019-05-26 15:07:03.585950655 -0400
@@ -17,7 +17,7 @@
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -145,8 +145,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2019-05-26 15:07:03.586950659 -0400
@@ -19,7 +19,7 @@
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -143,8 +143,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4a.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4a.s 2019-05-26 15:07:03.588950668 -0400
@@ -13,7 +13,7 @@
! Instructions introduced into sh4a
fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -147,8 +147,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4al-dsp.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2019-05-26 15:07:03.589950672 -0400
@@ -48,7 +48,7 @@
dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -202,8 +202,8 @@
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/include/elf/sh.h binutils-2.32/include/elf/sh.h
--- binutils-2.32.orig/include/elf/sh.h 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/include/elf/sh.h 2019-05-26 15:07:03.590950676 -0400
@@ -39,6 +39,7 @@
#define EF_SH2E 11
#define EF_SH4A 12
#define EF_SH2A 13
+#define EF_SHJ2 14
#define EF_SH4_NOFPU 16
#define EF_SH4A_NOFPU 17
@@ -50,6 +51,7 @@
#define EF_SH2A_SH3_NOFPU 22
#define EF_SH2A_SH4 23
#define EF_SH2A_SH3E 24
+#define EF_SH2A_SH3_SHJ2 25
/* This one can only mix in objects from other EF_SH5 objects. */
#define EF_SH5 10
@@ -72,7 +74,8 @@
/* EF_SH2E */ bfd_mach_sh2e , \
/* EF_SH4A */ bfd_mach_sh4a , \
/* EF_SH2A */ bfd_mach_sh2a , \
-/* 14, 15 */ 0, 0, \
+/* EF_SHJ2 */ bfd_mach_shj2 , \
+/* 15 */ 0, \
/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
@@ -81,7 +84,8 @@
/* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
/* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
/* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
+/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
+/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
/* Convert arch_sh* into EF_SH*. */
int sh_find_elf_flags (unsigned int arch_set);
diff -ur binutils-2.32.orig/opcodes/sh-dis.c binutils-2.32/opcodes/sh-dis.c
--- binutils-2.32.orig/opcodes/sh-dis.c 2019-01-19 11:01:34.000000000 -0500
+++ binutils-2.32/opcodes/sh-dis.c 2019-05-26 15:07:03.593950688 -0400
@@ -856,6 +856,9 @@
case XMTRX_M4:
fprintf_fn (stream, "xmtrx");
break;
+ case A_IND_0:
+ fprintf_fn (stream, "@r0");
+ break;
default:
abort ();
}
Only in binutils-2.32/opcodes: sh-dis.c.orig
diff -ur binutils-2.32.orig/opcodes/sh-opc.h binutils-2.32/opcodes/sh-opc.h
--- binutils-2.32.orig/opcodes/sh-opc.h 2019-01-19 11:01:34.000000000 -0500
+++ binutils-2.32/opcodes/sh-opc.h 2019-05-26 15:07:03.597950705 -0400
@@ -191,7 +191,8 @@
FPUL_N,
FPUL_M,
FPSCR_N,
- FPSCR_M
+ FPSCR_M,
+ A_IND_0
}
sh_arg_type;
@@ -215,9 +216,11 @@
#define arch_sh4_base (1 << 5)
#define arch_sh4a_base (1 << 6)
#define arch_sh2a_base (1 << 7)
-#define arch_sh_base_mask MASK (0, 7)
+#define arch_shj2_base (1 << 8)
+#define arch_sh2a_sh3_shj2_base (1 << 9)
+#define arch_sh_base_mask MASK (0, 9)
-/* Bits 8 ... 24 are currently free. */
+/* Bits 10 ... 24 are currently free. */
/* This is an annotation on instruction types, but we
abuse the arch field in instructions to denote it. */
@@ -255,6 +258,8 @@
#define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
#define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
#define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
+#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
@@ -319,7 +324,8 @@
#define arch_sh2_up (arch_sh2 \
| arch_sh2e_up \
| arch_sh2a_nofpu_or_sh3_nommu_up \
- | arch_sh_dsp_up)
+ | arch_sh_dsp_up \
+ | arch_shj2_up)
#define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
| arch_sh2a_or_sh3e_up \
@@ -345,6 +351,12 @@
#define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
| arch_sh4a_up \
| arch_sh4al_dsp_up)
+#define arch_shj2_up ( arch_shj2)
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
+ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
+ | arch_sh2a_or_sh3e_up \
+ | arch_sh3_nommu_up \
+ | arch_shj2_up)
/* Right branches. */
#define arch_sh2e_up (arch_sh2e \
@@ -713,9 +725,9 @@
/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
+/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
+/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
@@ -1193,7 +1205,7 @@
{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
-
+ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
{ 0, {0}, {0}, 0 }
};
Only in binutils-2.32/opcodes: sh-opc.h.orig

83
patches/binutils-2.32/0002-arm-pie-tls.diff Normal file
View File

@@ -0,0 +1,83 @@
From 7d6e280a0f3b9978b0edb20173d067d071531a3d Mon Sep 17 00:00:00 2001
From: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date: Wed, 2 Oct 2019 19:46:46 +0100
Subject: [PATCH] [PR ld/22263][PR ld/25056] arm: Avoid dynamic TLS relocs in
PIE
Dynamic relocs are only needed in an executable for TLS symbols if
those are defined in an external module and even then TLS access
can be relaxed to use IE model instead of GD.
Several bfd_link_pic checks are turned into bfd_link_dll checks
to fix TLS handling in PIE, for the same fix some other targets
used !bfd_link_executable checks, but that includes relocatable
objects so dll seems safer (in most cases either should work, since
dynamic relocations are not applied in relocatable objects).
On arm* fixes
FAIL: Build pr22263-1
bfd/
2019-10-02 Szabolcs Nagy <szabolcs.nagy@arm.com>
PR ld/22263
PR ld/25056
* elf32-arm.c (elf32_arm_tls_transition): Use bfd_link_dll instead of
bfd_link_pic for TLS checks.
(elf32_arm_final_link_relocate): Likewise.
(allocate_dynrelocs_for_symbol): Likewise.
---
bfd/elf32-arm.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index bb53e039e3..451949d278 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -4914,7 +4914,7 @@ elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
{
int is_local = (h == NULL);
- if (bfd_link_pic (info)
+ if (bfd_link_dll (info)
|| (h && h->root.type == bfd_link_hash_undefweak))
return r_type;
@@ -11700,7 +11700,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
{
/* If we don't know the module number, create a relocation
for it. */
- if (bfd_link_pic (info))
+ if (bfd_link_dll (info))
{
Elf_Internal_Rela outrel;
@@ -11804,7 +11804,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
now, and emit any relocations. If both an IE GOT and a
GD GOT are necessary, we emit the GD first. */
- if ((bfd_link_pic (info) || indx != 0)
+ if ((bfd_link_dll (info) || indx != 0)
&& (h == NULL
|| (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
&& !resolved_to_zero)
@@ -11821,7 +11821,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
/* We should have relaxed, unless this is an undefined
weak symbol. */
BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
- || bfd_link_pic (info));
+ || bfd_link_dll (info));
BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
<= globals->root.sgotplt->size);
@@ -16494,7 +16494,7 @@ allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
indx = h->dynindx;
if (tls_type != GOT_NORMAL
- && (bfd_link_pic (info) || indx != 0)
+ && (bfd_link_dll (info) || indx != 0)
&& (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|| h->root.type != bfd_link_hash_undefweak))
{
--
2.17.1

16
patches/binutils-2.32/0003-arm-tlsdesc-64bithost.diff Normal file
View File

@@ -0,0 +1,16 @@
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index bb53e039e3..d52c046979 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -12027,9 +12027,9 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
unsigned long data, insn;
unsigned thumb;
- data = bfd_get_32 (input_bfd, hit_data);
+ data = bfd_get_signed_32 (input_bfd, hit_data);
thumb = data & 1;
- data &= ~1u;
+ data &= ~1ul;
if (thumb)
{

55
patches/binutils-2.32/0004-arm-pr22269.diff Normal file
View File

@@ -0,0 +1,55 @@
From: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date: Thu, 9 Jan 2020 17:20:56 +0000 (+0000)
Subject: [PR ld/22269] arm: Avoid dynamic relocs for undefweak symbols in static PIE
X-Git-Url: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commitdiff_plain;h=6fbcfe4762c3732339cffd82426d00d35382b858;hp=c06868784d819a45c43947180c69e168aecaf368
[PR ld/22269] arm: Avoid dynamic relocs for undefweak symbols in static PIE
With static PIE linking undefined weak symbols are resolved to 0, so no
dynamic relocation is needed for them. The UNDEFWEAK_NO_DYNAMIC_RELOC
macro was introduced so this case can be handled easily, but it was not
applied consistently in the first attempt to fix ld/22269 for arm:
commit 95b03e4ad68e7a90f5096b47df595636344b783a
arm: Check UNDEFWEAK_NO_DYNAMIC_RELOC
This patch fixes spurious relative relocs in static PIE binaries against
GOT entries created for undefined weak symbols on arm*-*, this fixes
FAIL: pr22269-1 (static pie undefined weak)
bfd/ChangeLog:
Backported from master
2020-01-10 Szabolcs Nagy <szabolcs.nagy@arm.com>
PR ld/22269
* elf32-arm.c (elf32_arm_final_link_relocate): Use
UNDEFWEAK_NO_DYNAMIC_RELOC.
(allocate_dynrelocs_for_symbol): Likewise.
---
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index cce796d..21cf4b0 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -11572,8 +11572,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
if (dynreloc_st_type == STT_GNU_IFUNC)
outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
else if (bfd_link_pic (info)
- && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
- || h->root.type != bfd_link_hash_undefweak))
+ && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
else
{
@@ -16527,8 +16526,7 @@ allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
GOT entry's R_ARM_IRELATIVE relocation. */
elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
else if (bfd_link_pic (info)
- && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
- || h->root.type != bfd_link_hash_undefweak))
+ && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
/* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
else if (htab->fdpic_p && tls_type == GOT_NORMAL)

620
patches/binutils-2.33.1/0001-j2.diff Normal file
View File

@@ -0,0 +1,620 @@
diff -ur binutils-2.32.orig/bfd/archures.c binutils-2.32/bfd/archures.c
--- binutils-2.32.orig/bfd/archures.c 2019-01-19 11:01:32.000000000 -0500
+++ binutils-2.32/bfd/archures.c 2019-05-26 15:09:15.968501965 -0400
@@ -298,6 +298,8 @@
.#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
.#define bfd_mach_sh2a_or_sh4 0x2a3
.#define bfd_mach_sh2a_or_sh3e 0x2a4
+.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
+.#define bfd_mach_shj2 0x2c
.#define bfd_mach_sh2e 0x2e
.#define bfd_mach_sh3 0x30
.#define bfd_mach_sh3_nommu 0x31
Only in binutils-2.32/bfd: archures.c.orig
Only in binutils-2.32/bfd: archures.c.rej
diff -ur binutils-2.32.orig/bfd/bfd-in2.h binutils-2.32/bfd/bfd-in2.h
--- binutils-2.32.orig/bfd/bfd-in2.h 2019-01-19 11:01:32.000000000 -0500
+++ binutils-2.32/bfd/bfd-in2.h 2019-05-26 15:10:21.005775819 -0400
@@ -2197,6 +2197,8 @@
#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
#define bfd_mach_sh2a_or_sh4 0x2a3
#define bfd_mach_sh2a_or_sh3e 0x2a4
+#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
+#define bfd_mach_shj2 0x2c
#define bfd_mach_sh2e 0x2e
#define bfd_mach_sh3 0x30
#define bfd_mach_sh3_nommu 0x31
Only in binutils-2.32/bfd: bfd-in2.h.orig
Only in binutils-2.32/bfd: bfd-in2.h.rej
diff -ur binutils-2.32.orig/bfd/cpu-sh.c binutils-2.32/bfd/cpu-sh.c
--- binutils-2.32.orig/bfd/cpu-sh.c 2019-01-19 11:01:32.000000000 -0500
+++ binutils-2.32/bfd/cpu-sh.c 2019-05-26 15:13:00.461455381 -0400
@@ -43,7 +43,10 @@
#define SH2A_NOFPU_OR_SH4_NOMMU_NOFPU_NEXT arch_info_struct + 16
#define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17
#define SH2A_OR_SH4_NEXT arch_info_struct + 18
-#define SH2A_OR_SH3E_NEXT NULL
+#define SH2A_OR_SH3E_NEXT arch_info_struct + 19
+#define SHJ2_NEXT arch_info_struct + 20
+#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT NULL
+
static const bfd_arch_info_type arch_info_struct[] =
{
@@ -332,6 +335,36 @@
bfd_arch_default_fill,
SH2A_OR_SH3E_NEXT
},
+ {
+ 32, /* 32 bits in a word. */
+ 32, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+ bfd_arch_sh,
+ bfd_mach_shj2,
+ "sh", /* Architecture name. . */
+ "j2", /* Machine name. */
+ 1,
+ FALSE, /* Not the default. */
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
+ SHJ2_NEXT
+ },
+ {
+ 32, /* 32 bits in a word. */
+ 32, /* 32 bits in an address. */
+ 8, /* 8 bits in a byte. */
+ bfd_arch_sh,
+ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu,
+ "sh", /* Architecture name. . */
+ "sh2a-or-sh3e-or-j2", /* Machine name. */
+ 1,
+ FALSE, /* Not the default. */
+ bfd_default_compatible,
+ bfd_default_scan,
+ bfd_arch_default_fill,
+ SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT
+ },
};
const bfd_arch_info_type bfd_sh_arch =
@@ -382,6 +415,8 @@
{ bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
{ bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
{ bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
+ { bfd_mach_shj2, arch_shj2, arch_shj2_up },
+ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
{ 0, 0, 0 } /* Terminator. */
};
Only in binutils-2.32/bfd: cpu-sh.c.orig
Only in binutils-2.32/bfd: cpu-sh.c.rej
diff -ur binutils-2.32.orig/binutils/readelf.c binutils-2.32/binutils/readelf.c
--- binutils-2.32.orig/binutils/readelf.c 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/binutils/readelf.c 2019-05-26 15:07:03.563950564 -0400
@@ -3528,6 +3528,8 @@
case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
+ case EF_SHJ2: strcat (buf, ", j2"); break;
+ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
default: strcat (buf, _(", unknown ISA")); break;
}
Only in binutils-2.32/binutils: readelf.c.orig
diff -ur binutils-2.32.orig/gas/config/tc-sh.c binutils-2.32/gas/config/tc-sh.c
--- binutils-2.32.orig/gas/config/tc-sh.c 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/config/tc-sh.c 2019-05-26 15:07:03.567950581 -0400
@@ -1251,6 +1251,8 @@
ptr++;
}
get_operand (&ptr, operand + 2);
+ if (strcmp (info->name,"cas") == 0)
+ operand[2].type = A_IND_0;
}
else
{
@@ -1790,7 +1792,10 @@
goto fail;
reg_m = 4;
break;
-
+ case A_IND_0:
+ if (user->reg != 0)
+ goto fail;
+ break;
default:
printf (_("unhandled %d\n"), arg);
goto fail;
Only in binutils-2.32/gas/config: tc-sh.c.orig
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2019-05-26 15:07:03.568950585 -0400
@@ -12,8 +12,6 @@
sh2a_nofpu_or_sh3_nommu:
! Instructions introduced into sh2a-nofpu-or-sh3-nommu
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
! Instructions inherited from ancestors: sh sh2
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2019-05-26 15:07:03.570950593 -0400
@@ -12,7 +12,7 @@
sh2a_nofpu_or_sh4_nommu_nofpu:
! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -119,8 +119,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2019-05-26 15:07:03.571950597 -0400
@@ -64,7 +64,7 @@
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -171,8 +171,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2019-05-26 15:07:03.572950601 -0400
@@ -13,7 +13,7 @@
! Instructions introduced into sh2a-or-sh3e
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -124,8 +124,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2019-05-26 15:07:03.574950610 -0400
@@ -39,7 +39,7 @@
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -150,8 +150,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a.s 2019-05-26 15:07:03.575950614 -0400
@@ -16,7 +16,7 @@
fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -140,8 +140,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3-dsp.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3-dsp.s 2019-05-26 15:07:03.577950622 -0400
@@ -12,7 +12,7 @@
sh3_dsp:
! Instructions introduced into sh3-dsp
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -152,8 +152,8 @@
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3-nommu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3-nommu.s 2019-05-26 15:07:03.578950626 -0400
@@ -26,7 +26,7 @@
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -133,8 +133,8 @@
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3.s 2019-05-26 15:07:03.579950630 -0400
@@ -13,7 +13,7 @@
! Instructions introduced into sh3
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -128,8 +128,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3e.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3e.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3e.s 2019-05-26 15:07:03.581950639 -0400
@@ -12,7 +12,7 @@
sh3e:
! Instructions introduced into sh3e
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -132,8 +132,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nofpu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2019-05-26 15:07:03.582950643 -0400
@@ -12,7 +12,7 @@
sh4_nofpu:
! Instructions introduced into sh4-nofpu
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -136,8 +136,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2019-05-26 15:07:03.583950647 -0400
@@ -24,7 +24,7 @@
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -139,8 +139,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4.s 2019-05-26 15:07:03.585950655 -0400
@@ -17,7 +17,7 @@
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -145,8 +145,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2019-05-26 15:07:03.586950659 -0400
@@ -19,7 +19,7 @@
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -143,8 +143,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4a.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4a.s 2019-05-26 15:07:03.588950668 -0400
@@ -13,7 +13,7 @@
! Instructions introduced into sh4a
fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -147,8 +147,8 @@
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4al-dsp.s
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2019-05-26 15:07:03.589950672 -0400
@@ -48,7 +48,7 @@
dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
@@ -202,8 +202,8 @@
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
diff -ur binutils-2.32.orig/include/elf/sh.h binutils-2.32/include/elf/sh.h
--- binutils-2.32.orig/include/elf/sh.h 2019-01-19 11:01:33.000000000 -0500
+++ binutils-2.32/include/elf/sh.h 2019-05-26 15:07:03.590950676 -0400
@@ -39,6 +39,7 @@
#define EF_SH2E 11
#define EF_SH4A 12
#define EF_SH2A 13
+#define EF_SHJ2 14
#define EF_SH4_NOFPU 16
#define EF_SH4A_NOFPU 17
@@ -50,6 +51,7 @@
#define EF_SH2A_SH3_NOFPU 22
#define EF_SH2A_SH4 23
#define EF_SH2A_SH3E 24
+#define EF_SH2A_SH3_SHJ2 25
/* This one can only mix in objects from other EF_SH5 objects. */
#define EF_SH5 10
@@ -72,7 +74,8 @@
/* EF_SH2E */ bfd_mach_sh2e , \
/* EF_SH4A */ bfd_mach_sh4a , \
/* EF_SH2A */ bfd_mach_sh2a , \
-/* 14, 15 */ 0, 0, \
+/* EF_SHJ2 */ bfd_mach_shj2 , \
+/* 15 */ 0, \
/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
@@ -81,7 +84,8 @@
/* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
/* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
/* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
+/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
+/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
/* Convert arch_sh* into EF_SH*. */
int sh_find_elf_flags (unsigned int arch_set);
diff -ur binutils-2.32.orig/opcodes/sh-dis.c binutils-2.32/opcodes/sh-dis.c
--- binutils-2.32.orig/opcodes/sh-dis.c 2019-01-19 11:01:34.000000000 -0500
+++ binutils-2.32/opcodes/sh-dis.c 2019-05-26 15:07:03.593950688 -0400
@@ -856,6 +856,9 @@
case XMTRX_M4:
fprintf_fn (stream, "xmtrx");
break;
+ case A_IND_0:
+ fprintf_fn (stream, "@r0");
+ break;
default:
abort ();
}
Only in binutils-2.32/opcodes: sh-dis.c.orig
diff -ur binutils-2.32.orig/opcodes/sh-opc.h binutils-2.32/opcodes/sh-opc.h
--- binutils-2.32.orig/opcodes/sh-opc.h 2019-01-19 11:01:34.000000000 -0500
+++ binutils-2.32/opcodes/sh-opc.h 2019-05-26 15:07:03.597950705 -0400
@@ -191,7 +191,8 @@
FPUL_N,
FPUL_M,
FPSCR_N,
- FPSCR_M
+ FPSCR_M,
+ A_IND_0
}
sh_arg_type;
@@ -215,9 +216,11 @@
#define arch_sh4_base (1 << 5)
#define arch_sh4a_base (1 << 6)
#define arch_sh2a_base (1 << 7)
-#define arch_sh_base_mask MASK (0, 7)
+#define arch_shj2_base (1 << 8)
+#define arch_sh2a_sh3_shj2_base (1 << 9)
+#define arch_sh_base_mask MASK (0, 9)
-/* Bits 8 ... 24 are currently free. */
+/* Bits 10 ... 24 are currently free. */
/* This is an annotation on instruction types, but we
abuse the arch field in instructions to denote it. */
@@ -255,6 +258,8 @@
#define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
#define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
#define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
+#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
@@ -319,7 +324,8 @@
#define arch_sh2_up (arch_sh2 \
| arch_sh2e_up \
| arch_sh2a_nofpu_or_sh3_nommu_up \
- | arch_sh_dsp_up)
+ | arch_sh_dsp_up \
+ | arch_shj2_up)
#define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
| arch_sh2a_or_sh3e_up \
@@ -345,6 +351,12 @@
#define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
| arch_sh4a_up \
| arch_sh4al_dsp_up)
+#define arch_shj2_up ( arch_shj2)
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
+ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
+ | arch_sh2a_or_sh3e_up \
+ | arch_sh3_nommu_up \
+ | arch_shj2_up)
/* Right branches. */
#define arch_sh2e_up (arch_sh2e \
@@ -713,9 +725,9 @@
/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
+/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
+/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
@@ -1193,7 +1205,7 @@
{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
-
+ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
{ 0, {0}, {0}, 0 }
};
Only in binutils-2.32/opcodes: sh-opc.h.orig

249
patches/binutils-2.33.1/0002-or1k-32bithost-1.diff Normal file
View File

@@ -0,0 +1,249 @@
From: Stafford Horne <shorne@gmail.com>
To: GNU Binutils <binutils@sourceware.org>
Cc: Openrisc <openrisc@lists.librecores.org>, dalias@libc.org, Stafford Horne <shorne@gmail.com>
Subject: [PATCH 1/2] or1k: Remove 64-bit support, it's not used and it breaks 32-bit hosts
Date: Wed, 11 Dec 2019 06:49:05 +0900
Reported by Rich Felker when building on 32-bit hosts. Backwards jump
negative offsets were not calculated correctly due to improper 32-bit
to 64-bit zero-extension. The 64-bit fields are present because we
are mixing 32-bit and 64-bit architectures in our cpu descriptions.
Removing 64-bit fixes the issue. We don't use 64-bit, there is an architecture
spec for 64-bit but no implementations or simulators. My thought is if
we need them in the future we should do the proper work to support both
32-bit and 64-bit implementations co-existing then.
cpu/ChangeLog:
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
PR 25184
* or1k.cpu (arch or1k): Remove or64 and or64nd machs.
(ORBIS-MACHS, ORFPX32-MACHS): Remove pmacros.
(cpu or1k64bf, mach or64, mach or64nd): Remove definitions.
* or1kcommon.cpu (h-fdr): Remove hardware.
* or1korfpx.cpu (rDDF, rADF, rBDF): Remove operand definitions.
(float-regreg-insn): Remove lf- mnemonic -d instruction pattern.
(float-setflag-insn-base): Remove lf-sf mnemonic -d pattern.
(float-cust-insn): Remove "lf-cust" cust-num "-d" pattern.
(lf-rem-d, lf-itof-d, lf-ftoi-d, lf-madd-d): Remove.
---
cpu/or1k.cpu | 35 +++----------------------
cpu/or1kcommon.cpu | 14 ----------
cpu/or1korfpx.cpu | 64 ----------------------------------------------
3 files changed, 3 insertions(+), 110 deletions(-)
diff --git a/cpu/or1k.cpu b/cpu/or1k.cpu
index b796862d1b..9784f7a0fa 100644
--- a/cpu/or1k.cpu
+++ b/cpu/or1k.cpu
@@ -31,7 +31,7 @@
(comment "OpenRISC 1000")
(default-alignment aligned)
(insn-lsb0? #t)
- (machs or32 or32nd or64 or64nd)
+ (machs or32 or32nd)
(isas openrisc)
)
@@ -44,10 +44,8 @@
)
(define-pmacro OR32-MACHS or32,or32nd)
-(define-pmacro OR64-MACHS or64,or64nd)
-(define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd)
-(define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd)
-(define-pmacro ORFPX64-MACHS or64,or64nd)
+(define-pmacro ORBIS-MACHS or32,or32nd)
+(define-pmacro ORFPX32-MACHS or32,or32nd)
(define-pmacro ORFPX64A32-MACHS or32,or32nd) ; float64 for 32-bit machs
(define-attr
@@ -100,33 +98,6 @@
)
)
-(if (keep-mach? (or64 or64nd))
- (begin
- (define-cpu
- (name or1k64bf)
- (comment "OpenRISC 1000 64-bit CPU family")
- (insn-endian big)
- (data-endian big)
- (word-bitsize 64)
- (file-transform "64")
- )
-
- (define-mach
- (name or64)
- (comment "Generic OpenRISC 1000 64-bit CPU")
- (cpu or1k64bf)
- (bfd-name "or1k64")
- )
-
- (define-mach
- (name or64nd)
- (comment "Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot")
- (cpu or1k64bf)
- (bfd-name "or1k64nd")
- )
- )
- )
-
(include "or1kcommon.cpu")
(include "or1korbis.cpu")
(include "or1korfpx.cpu")
diff --git a/cpu/or1kcommon.cpu b/cpu/or1kcommon.cpu
index 65154407df..9f102c93a1 100644
--- a/cpu/or1kcommon.cpu
+++ b/cpu/or1kcommon.cpu
@@ -114,20 +114,6 @@
(set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0))))
)
-;
-; Hardware: virtual registerts for FPU (double precision)
-; mapped to GPRs
-;
-(define-hardware
- (name h-fdr)
- (comment "or64 floating point registers (double, virtual)")
- (attrs VIRTUAL (MACH ORFPX64-MACHS))
- (type register DF (32))
- (indices keyword "" REG-INDICES)
- (get (index) (subword DF (trunc DI (reg h-gpr index)) 0))
- (set (index newval) (set UDI (reg h-gpr index) (zext UDI (subword DI newval 0))))
- )
-
;
; Register pairs are offset by 2 for registers r16 and above. This is to
; be able to allow registers to be call saved in GCC across function calls.
diff --git a/cpu/or1korfpx.cpu b/cpu/or1korfpx.cpu
index f43522f2e6..0bd469cff5 100644
--- a/cpu/or1korfpx.cpu
+++ b/cpu/or1korfpx.cpu
@@ -84,10 +84,6 @@
(dnop rASF "source register A (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r2)
(dnop rBSF "source register B (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r3)
-(dnop rDDF "or64 destination register (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
-(dnop rADF "or64 source register A (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r2)
-(dnop rBDF "or64 source register B (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r3)
-
(define-pmacro (double-field-and-ops mnemonic reg offbit op-comment)
(begin
(define-multi-ifield
@@ -152,14 +148,6 @@
(set SF rDSF (mnemonic SF rASF rBSF))
()
)
- (dni (.sym lf- mnemonic -d)
- (.str "lf." mnemonic ".d reg/reg/reg")
- ((MACH ORFPX64-MACHS))
- (.str "lf." mnemonic ".d $rDDF,$rADF,$rBDF")
- (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D))
- (set DF rDDF (mnemonic DF rADF rBDF))
- ()
- )
(dni (.sym lf- mnemonic -d32)
(.str "lf." mnemonic ".d regpair/regpair/regpair")
((MACH ORFPX64A32-MACHS))
@@ -185,15 +173,6 @@
()
)
-(dni lf-rem-d
- "lf.rem.d reg/reg/reg"
- ((MACH ORFPX64-MACHS))
- "lf.rem.d $rDDF,$rADF,$rBDF"
- (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_D)
- (set DF rDDF (rem DF rADF rBDF))
- ()
- )
-
(dni lf-rem-d32
"lf.rem.d regpair/regpair/regpair"
((MACH ORFPX64A32-MACHS))
@@ -221,15 +200,6 @@
()
)
-(dni lf-itof-d
- "lf.itof.d reg/reg"
- ((MACH ORFPX64-MACHS))
- "lf.itof.d $rDDF,$rA"
- (+ OPC_FLOAT rDDF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D)
- (set DF rDDF (float DF (get-rounding-mode) rA))
- ()
- )
-
(dni lf-itof-d32
"lf.itof.d regpair/regpair"
((MACH ORFPX64A32-MACHS))
@@ -248,15 +218,6 @@
()
)
-(dni lf-ftoi-d
- "lf.ftoi.d reg/reg"
- ((MACH ORFPX64-MACHS))
- "lf.ftoi.d $rD,$rADF"
- (+ OPC_FLOAT rD rADF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_D)
- (set WI rD (fix WI (get-rounding-mode) rADF))
- ()
- )
-
(dni lf-ftoi-d32
"lf.ftoi.d regpair/regpair"
((MACH ORFPX64A32-MACHS))
@@ -276,14 +237,6 @@
(symantics rtx-mnemonic SF rASF rBSF)
()
)
- (dni (.sym lf-sf mnemonic -d)
- (.str "lf.sf" mnemonic ".d reg/reg")
- ((MACH ORFPX64-MACHS))
- (.str "lf.sf" mnemonic ".d $rADF,$rBDF")
- (+ OPC_FLOAT (f-r1 0) rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
- (symantics rtx-mnemonic DF rADF rBDF)
- ()
- )
(dni (.sym lf-sf mnemonic -d32)
(.str "lf.sf" mnemonic ".d regpair/regpair")
((MACH ORFPX64A32-MACHS))
@@ -336,15 +289,6 @@
()
)
-(dni lf-madd-d
- "lf.madd.d reg/reg/reg"
- ((MACH ORFPX64-MACHS))
- "lf.madd.d $rDDF,$rADF,$rBDF"
- (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_D)
- (set DF rDDF (add DF (mul DF rADF rBDF) rDDF))
- ()
- )
-
(dni lf-madd-d32
"lf.madd.d regpair/regpair/regpair"
((MACH ORFPX64A32-MACHS))
@@ -364,14 +308,6 @@
(nop)
()
)
- (dni (.sym "lf-cust" cust-num "-d")
- (.str "lf.cust" cust-num ".d")
- ((MACH ORFPX64-MACHS))
- (.str "lf.cust" cust-num ".d")
- (+ OPC_FLOAT (f-resv-25-5 0) rADF rBDF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D"))
- (nop)
- ()
- )
(dni (.sym "lf-cust" cust-num "-d32")
(.str "lf.cust" cust-num ".d")
((MACH ORFPX64A32-MACHS))
--
2.21.0

4308
patches/binutils-2.33.1/0003-or1k-32bithost-2.diff Normal file
View File

File diff suppressed because it is too large Load Diff

55
patches/binutils-2.33.1/0004-arm-pr22269.diff Normal file
View File

@@ -0,0 +1,55 @@
From: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date: Thu, 9 Jan 2020 17:20:56 +0000 (+0000)
Subject: [PR ld/22269] arm: Avoid dynamic relocs for undefweak symbols in static PIE
X-Git-Url: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commitdiff_plain;h=6fbcfe4762c3732339cffd82426d00d35382b858;hp=c06868784d819a45c43947180c69e168aecaf368
[PR ld/22269] arm: Avoid dynamic relocs for undefweak symbols in static PIE
With static PIE linking undefined weak symbols are resolved to 0, so no
dynamic relocation is needed for them. The UNDEFWEAK_NO_DYNAMIC_RELOC
macro was introduced so this case can be handled easily, but it was not
applied consistently in the first attempt to fix ld/22269 for arm:
commit 95b03e4ad68e7a90f5096b47df595636344b783a
arm: Check UNDEFWEAK_NO_DYNAMIC_RELOC
This patch fixes spurious relative relocs in static PIE binaries against
GOT entries created for undefined weak symbols on arm*-*, this fixes
FAIL: pr22269-1 (static pie undefined weak)
bfd/ChangeLog:
Backported from master
2020-01-10 Szabolcs Nagy <szabolcs.nagy@arm.com>
PR ld/22269
* elf32-arm.c (elf32_arm_final_link_relocate): Use
UNDEFWEAK_NO_DYNAMIC_RELOC.
(allocate_dynrelocs_for_symbol): Likewise.
---
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index cce796d..21cf4b0 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -11572,8 +11572,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
if (dynreloc_st_type == STT_GNU_IFUNC)
outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
else if (bfd_link_pic (info)
- && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
- || h->root.type != bfd_link_hash_undefweak))
+ && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
else
{
@@ -16527,8 +16526,7 @@ allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
GOT entry's R_ARM_IRELATIVE relocation. */
elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
else if (bfd_link_pic (info)
- && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
- || h->root.type != bfd_link_hash_undefweak))
+ && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
/* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
else if (htab->fdpic_p && tls_type == GOT_NORMAL)

377
patches/binutils-397a64b3/0001-staticpie.diff Normal file
View File

@@ -0,0 +1,377 @@
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index bd4b576..41803c2 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -13786,7 +13786,7 @@ elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-bfin.c b/bfd/elf32-bfin.c
index 49ef360..8346d57 100644
--- a/bfd/elf32-bfin.c
+++ b/bfd/elf32-bfin.c
@@ -4257,7 +4257,7 @@ elf32_bfinfdpic_size_dynamic_sections (bfd *output_bfd,
if (htab->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-cris.c b/bfd/elf32-cris.c
index 3031173..5b40524 100644
--- a/bfd/elf32-cris.c
+++ b/bfd/elf32-cris.c
@@ -3764,7 +3764,7 @@ elf_cris_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-frv.c b/bfd/elf32-frv.c
index b55a7ab..ef72c23 100644
--- a/bfd/elf32-frv.c
+++ b/bfd/elf32-frv.c
@@ -5444,7 +5444,7 @@ elf32_frvfdpic_size_dynamic_sections (bfd *output_bfd,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-hppa.c b/bfd/elf32-hppa.c
index 41bf5c5..62c7cf6 100644
--- a/bfd/elf32-hppa.c
+++ b/bfd/elf32-hppa.c
@@ -2215,7 +2215,7 @@ elf32_hppa_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (htab->etab.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
sec = bfd_get_linker_section (dynobj, ".interp");
if (sec == NULL)
diff --git a/bfd/elf32-i370.c b/bfd/elf32-i370.c
index 7fba4d1..458f694 100644
--- a/bfd/elf32-i370.c
+++ b/bfd/elf32-i370.c
@@ -594,7 +594,7 @@ i370_elf_size_dynamic_sections (bfd *output_bfd,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-i386.c b/bfd/elf32-i386.c
index 7642d0f..b0844c8 100644
--- a/bfd/elf32-i386.c
+++ b/bfd/elf32-i386.c
@@ -2834,7 +2834,7 @@ elf_i386_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info)
if (htab->elf.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
if (s == NULL)
diff --git a/bfd/elf32-m32r.c b/bfd/elf32-m32r.c
index 155d079..a2e3c7c 100644
--- a/bfd/elf32-m32r.c
+++ b/bfd/elf32-m32r.c
@@ -2170,7 +2170,7 @@ m32r_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (htab->root.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-m68k.c b/bfd/elf32-m68k.c
index 10d2fcb..489f3f1 100644
--- a/bfd/elf32-m68k.c
+++ b/bfd/elf32-m68k.c
@@ -3257,7 +3257,7 @@ elf_m68k_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-ppc.c b/bfd/elf32-ppc.c
index 8415f1e..5597051 100644
--- a/bfd/elf32-ppc.c
+++ b/bfd/elf32-ppc.c
@@ -6191,7 +6191,7 @@ ppc_elf_size_dynamic_sections (bfd *output_bfd,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (htab->elf.dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-s390.c b/bfd/elf32-s390.c
index de37ca4..a1e628c 100644
--- a/bfd/elf32-s390.c
+++ b/bfd/elf32-s390.c
@@ -2039,7 +2039,7 @@ elf_s390_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (htab->elf.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
if (s == NULL)
diff --git a/bfd/elf32-sh.c b/bfd/elf32-sh.c
index 012ee4e..a51453f 100644
--- a/bfd/elf32-sh.c
+++ b/bfd/elf32-sh.c
@@ -3349,7 +3349,7 @@ sh_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (htab->root.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-vax.c b/bfd/elf32-vax.c
index 6089e8c..893ea8d 100644
--- a/bfd/elf32-vax.c
+++ b/bfd/elf32-vax.c
@@ -1124,7 +1124,7 @@ elf_vax_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info)
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf32-xtensa.c b/bfd/elf32-xtensa.c
index 73538cd..37ea5da 100644
--- a/bfd/elf32-xtensa.c
+++ b/bfd/elf32-xtensa.c
@@ -1637,7 +1637,7 @@ elf_xtensa_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
&& htab->sgotloc != NULL);
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
if (s == NULL)
diff --git a/bfd/elf64-alpha.c b/bfd/elf64-alpha.c
index f67b0af..1973cd0 100644
--- a/bfd/elf64-alpha.c
+++ b/bfd/elf64-alpha.c
@@ -2877,7 +2877,7 @@ elf64_alpha_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf64-hppa.c b/bfd/elf64-hppa.c
index 6f40b88..3b628b4 100644
--- a/bfd/elf64-hppa.c
+++ b/bfd/elf64-hppa.c
@@ -1558,7 +1558,7 @@ elf64_hppa_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info)
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
sec = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (sec != NULL);
diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c
index 8cff990..851845f 100644
--- a/bfd/elf64-ppc.c
+++ b/bfd/elf64-ppc.c
@@ -9748,7 +9748,7 @@ ppc64_elf_size_dynamic_sections (bfd *output_bfd,
if (htab->elf.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
if (s == NULL)
diff --git a/bfd/elf64-s390.c b/bfd/elf64-s390.c
index 2e505f3..406bb66 100644
--- a/bfd/elf64-s390.c
+++ b/bfd/elf64-s390.c
@@ -1989,7 +1989,7 @@ elf_s390_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
if (htab->elf.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
if (s == NULL)
diff --git a/bfd/elf64-sh64.c b/bfd/elf64-sh64.c
index e460895..d920598 100644
--- a/bfd/elf64-sh64.c
+++ b/bfd/elf64-sh64.c
@@ -3404,7 +3404,7 @@ sh64_elf64_size_dynamic_sections (bfd *output_bfd,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elf64-x86-64.c b/bfd/elf64-x86-64.c
index f15d33e..870aadf 100644
--- a/bfd/elf64-x86-64.c
+++ b/bfd/elf64-x86-64.c
@@ -3181,7 +3181,7 @@ elf_x86_64_size_dynamic_sections (bfd *output_bfd,
if (htab->elf.dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
if (s == NULL)
diff --git a/bfd/elflink.c b/bfd/elflink.c
index 7f04271..5b3438d 100644
--- a/bfd/elflink.c
+++ b/bfd/elflink.c
@@ -246,7 +246,7 @@ _bfd_elf_link_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
/* A dynamically linked executable has a .interp section, but a
shared library does not. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_make_section_anyway_with_flags (abfd, ".interp",
flags | SEC_READONLY);
@@ -5763,7 +5763,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
bfd_boolean all_defined;
*sinterpptr = bfd_get_section_by_name (dynobj, ".interp");
- BFD_ASSERT (*sinterpptr != NULL || !info->executable);
+ BFD_ASSERT (*sinterpptr != NULL || !info->executable || info->nointerp);
if (soname != NULL)
{
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index be1e59a..329dec3 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -9579,7 +9579,7 @@ _bfd_mips_elf_size_dynamic_sections (bfd *output_bfd,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/bfd/elfxx-sparc.c b/bfd/elfxx-sparc.c
index 9bb71a9..db0d4f1 100644
--- a/bfd/elfxx-sparc.c
+++ b/bfd/elfxx-sparc.c
@@ -2559,7 +2559,7 @@ _bfd_sparc_elf_size_dynamic_sections (bfd *output_bfd,
if (elf_hash_table (info)->dynamic_sections_created)
{
/* Set the contents of the .interp section to the interpreter. */
- if (info->executable)
+ if (info->executable && !info->nointerp)
{
s = bfd_get_linker_section (dynobj, ".interp");
BFD_ASSERT (s != NULL);
diff --git a/include/bfdlink.h b/include/bfdlink.h
index 797a465..cf533dd 100644
--- a/include/bfdlink.h
+++ b/include/bfdlink.h
@@ -433,6 +433,9 @@ struct bfd_link_info
/* TRUE if BND prefix in PLT entries is always generated. */
unsigned int bndplt: 1;
+ /* TRUE if generation of .interp/PT_INTERP should be suppressed. */
+ unsigned int nointerp: 1;
+
/* Char that may appear as the first char of a symbol, but should be
skipped (like symbol_leading_char) when looking up symbols in
wrap_hash. Used by PowerPC Linux for 'dot' symbols. */
diff --git a/ld/ld.texinfo b/ld/ld.texinfo
index cf3b586..1e5e5cf 100644
--- a/ld/ld.texinfo
+++ b/ld/ld.texinfo
@@ -1426,6 +1426,13 @@ generating dynamically linked ELF executables. The default dynamic
linker is normally correct; don't use this unless you know what you are
doing.
+@kindex --no-dynamic-linker
+@item --no-dynamic-linker
+When producing an executable file, omit the request for a dynamic
+linker to be used at load-time. This is only meaningful for ELF
+executables that contain dynamic relocations, and usually requires
+entry point code that is capable of processing these relocations.
+
@kindex --fatal-warnings
@kindex --no-fatal-warnings
@item --fatal-warnings
diff --git a/ld/lexsup.c b/ld/lexsup.c
index 59bd14f..8b57f84 100644
--- a/ld/lexsup.c
+++ b/ld/lexsup.c
@@ -33,6 +33,7 @@ enum option_values
OPTION_DEFSYM,
OPTION_DEMANGLE,
OPTION_DYNAMIC_LINKER,
+ OPTION_NO_DYNAMIC_LINKER,
OPTION_SYSROOT,
OPTION_EB,
OPTION_EL,
diff --git a/ld/lexsup.c b/ld/lexsup.c
index 777d6e2..1b992f7 100644
--- a/ld/lexsup.c
+++ b/ld/lexsup.c
@@ -138,6 +138,9 @@ static const struct ld_option ld_options[] =
{ {"dynamic-linker", required_argument, NULL, OPTION_DYNAMIC_LINKER},
'I', N_("PROGRAM"), N_("Set PROGRAM as the dynamic linker to use"),
TWO_DASHES },
+ { {"no-dynamic-linker", no_argument, NULL, OPTION_NO_DYNAMIC_LINKER},
+ '\0', NULL, N_("Produce an executable with no program interpreter header"),
+ TWO_DASHES },
{ {"library", required_argument, NULL, 'l'},
'l', N_("LIBNAME"), N_("Search for library LIBNAME"), TWO_DASHES },
{ {"library-path", required_argument, NULL, 'L'},
@@ -762,6 +765,10 @@ parse_args (unsigned argc, char **argv)
case 'I': /* Used on Solaris. */
case OPTION_DYNAMIC_LINKER:
command_line.interpreter = optarg;
+ link_info.nointerp = 0;
+ break;
+ case OPTION_NO_DYNAMIC_LINKER:
+ link_info.nointerp = 1;
break;
case OPTION_SYSROOT:
/* Already handled in ldmain.c. */

18
patches/binutils-397a64b3/0006-noinfo.diff Normal file
View File

@@ -0,0 +1,18 @@
The binutils build notices that makeinfo is missing, but fails anyway, breaking
the build. Make it stop.
The "info" file format is obsolete (similar to "gopher"), was never used
by anyone but the FSF, and failed to even replace man pages (which are
now available in HTML).
--- binutils-2.18/missing 2005-07-13 20:24:56.000000000 -0500
+++ binutils-2.18/missing 2008-08-11 02:05:47.000000000 -0500
@@ -299,7 +299,7 @@
fi
# If the file does not exist, the user really needs makeinfo;
# let's fail without touching anything.
- test -f $file || exit 1
+ test -f $file || exit 0
touch $file
;;

11
patches/binutils-397a64b3/0007-shpcrel.diff Normal file
View File

@@ -0,0 +1,11 @@
--- binutils-397a64b3.orig//gas/config/tc-sh.c 2015-08-11 01:29:26.000000000 +0000
+++ binutils-397a64b3/gas/config/tc-sh.c 2015-11-02 23:17:03.931462591 +0000
@@ -4491,6 +4496,8 @@ sh_parse_name (char const *name,
reloc_type = BFD_RELOC_SH_TLS_LE_32;
else if ((next_end = sh_end_of_match (next + 1, "DTPOFF")))
reloc_type = BFD_RELOC_SH_TLS_LDO_32;
+ else if ((next_end = sh_end_of_match (next + 1, "PCREL")))
+ reloc_type = BFD_RELOC_32_PCREL;
else
goto no_suffix;

14
patches/gcc-10.3.0/0001-ssp_nonshared.diff Normal file
View File

@@ -0,0 +1,14 @@
diff --git a/gcc/gcc.c b/gcc/gcc.c
index 9f790db0daf..e6887590ae2 100644
--- a/gcc/gcc.c
+++ b/gcc/gcc.c
@@ -877,7 +877,8 @@ proper position among the other output files. */
#ifndef LINK_SSP_SPEC
#ifdef TARGET_LIBC_PROVIDES_SSP
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
- "|fstack-protector-strong|fstack-protector-explicit:}"
+ "|fstack-protector-strong|fstack-protector-explicit" \
+ ":-lssp_nonshared}"
#else
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
"|fstack-protector-strong|fstack-protector-explicit" \

30
patches/gcc-10.3.0/0002-posix_memalign.diff Normal file
View File

@@ -0,0 +1,30 @@
diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h
index 87344d9383f..ece428df487 100644
--- a/gcc/config/i386/pmm_malloc.h
+++ b/gcc/config/i386/pmm_malloc.h
@@ -27,12 +27,13 @@
#include <stdlib.h>
/* We can't depend on <stdlib.h> since the prototype of posix_memalign
- may not be visible. */
+ may not be visible and we can't pollute the namespace either. */
#ifndef __cplusplus
-extern int posix_memalign (void **, size_t, size_t);
+extern int _mm_posix_memalign (void **, size_t, size_t)
#else
-extern "C" int posix_memalign (void **, size_t, size_t) throw ();
+extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw ()
#endif
+__asm__("posix_memalign");
static __inline void *
_mm_malloc (size_t __size, size_t __alignment)
@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment)
return malloc (__size);
if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4))
__alignment = sizeof (void *);
- if (posix_memalign (&__ptr, __alignment, __size) == 0)
+ if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0)
return __ptr;
else
return NULL;

346
patches/gcc-10.3.0/0003-j2.diff Normal file
View File

@@ -0,0 +1,346 @@
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 6fcdd771d4c..839a60d866e 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -547,7 +547,7 @@ s390*-*-*)
extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h"
;;
# Note the 'l'; we need to be able to match e.g. "shle" or "shl".
-sh[123456789lbe]*-*-* | sh-*-*)
+sh[123456789lbej]*-*-* | sh-*-*)
cpu_type=sh
extra_options="${extra_options} fused-madd.opt"
extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o"
@@ -3149,18 +3149,18 @@ s390x-ibm-tpf*)
extra_options="${extra_options} s390/tpf.opt"
tmake_file="${tmake_file} s390/t-s390"
;;
-sh-*-elf* | sh[12346l]*-*-elf* | \
- sh-*-linux* | sh[2346lbe]*-*-linux* | \
+sh-*-elf* | sh[12346lj]*-*-elf* | \
+ sh-*-linux* | sh[2346lbej]*-*-linux* | \
sh-*-netbsdelf* | shl*-*-netbsdelf*)
tmake_file="${tmake_file} sh/t-sh sh/t-elf"
if test x${with_endian} = x; then
case ${target} in
- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;;
+ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;;
shbe-*-* | sheb-*-*) with_endian=big,little ;;
sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;;
shl* | sh*-*-linux* | \
sh-superh-elf) with_endian=little,big ;;
- sh[1234]*-*-*) with_endian=big ;;
+ sh[j1234]*-*-*) with_endian=big ;;
*) with_endian=big,little ;;
esac
fi
@@ -3227,6 +3227,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;;
sh2a*) sh_cpu_target=sh2a ;;
sh2e*) sh_cpu_target=sh2e ;;
+ shj2*) sh_cpu_target=shj2;;
sh2*) sh_cpu_target=sh2 ;;
*) sh_cpu_target=sh1 ;;
esac
@@ -3248,7 +3249,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
- sh3e | sh3 | sh2e | sh2 | sh1) ;;
+ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;;
"") sh_cpu_default=${sh_cpu_target} ;;
*) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
esac
@@ -3257,9 +3258,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
case ${target} in
sh[1234]*) sh_multilibs=${sh_cpu_target} ;;
sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;;
+ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;;
sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;;
- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
+ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;;
esac
if test x$with_fp = xno; then
sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
@@ -3274,7 +3275,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
m1 | m2 | m2e | m3 | m3e | \
m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \
- m2a | m2a-single | m2a-single-only | m2a-nofpu)
+ m2a | m2a-single | m2a-single-only | m2a-nofpu | \
+ mj2)
# TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
# It is passed to MULTIILIB_OPTIONS verbatim.
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
@@ -3291,7 +3293,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
done
TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
if test x${enable_incomplete_targets} = xyes ; then
- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1"
+ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1"
fi
tm_file="$tm_file ./sysroot-suffix.h"
tmake_file="$tmake_file t-sysroot-suffix"
@@ -5105,6 +5107,8 @@ case "${target}" in
;;
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
;;
+ mj2)
+ ;;
*)
echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2
echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
@@ -5315,7 +5319,7 @@ case ${target} in
tmake_file="${cpu_type}/t-${cpu_type} ${tmake_file}"
;;
- sh[123456ble]*-*-* | sh-*-*)
+ sh[123456blej]*-*-* | sh-*-*)
c_target_objs="${c_target_objs} sh-c.o"
cxx_target_objs="${cxx_target_objs} sh-c.o"
;;
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 84c0ea025b4..f15552af011 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -686,6 +686,7 @@ parse_validate_atomic_model_option (const char* str)
model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
model_names[sh_atomic_model::soft_imask] = "soft-imask";
+ model_names[sh_atomic_model::hard_cas] = "hard-cas";
const char* model_cdef_names[sh_atomic_model::num_models];
model_cdef_names[sh_atomic_model::none] = "NONE";
@@ -693,6 +694,7 @@ parse_validate_atomic_model_option (const char* str)
model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
+ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS";
sh_atomic_model ret;
ret.type = sh_atomic_model::none;
@@ -771,6 +773,9 @@ got_mode_name:;
if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
err_ret ("cannot use atomic model %s in user mode", ret.name);
+ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2)
+ err_ret ("atomic model %s is only available J2 targets", ret.name);
+
return ret;
#undef err_ret
@@ -827,6 +832,8 @@ sh_option_override (void)
sh_cpu = PROCESSOR_SH2E;
if (TARGET_SH2A)
sh_cpu = PROCESSOR_SH2A;
+ if (TARGET_SHJ2)
+ sh_cpu = PROCESSOR_SHJ2;
if (TARGET_SH3)
sh_cpu = PROCESSOR_SH3;
if (TARGET_SH3E)
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index 8ab5455505c..6ffed6da403 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -85,6 +85,7 @@ extern int code_for_indirect_jump_scratch;
#define SUPPORT_SH4_SINGLE 1
#define SUPPORT_SH2A 1
#define SUPPORT_SH2A_SINGLE 1
+#define SUPPORT_SHJ2 1
#endif
#define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
@@ -117,6 +118,7 @@ extern int code_for_indirect_jump_scratch;
#define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
#define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
#define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
+#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2)
#if SUPPORT_SH1
#define SUPPORT_SH2 1
@@ -124,6 +126,7 @@ extern int code_for_indirect_jump_scratch;
#if SUPPORT_SH2
#define SUPPORT_SH3 1
#define SUPPORT_SH2A_NOFPU 1
+#define SUPPORT_SHJ2 1
#endif
#if SUPPORT_SH3
#define SUPPORT_SH4_NOFPU 1
@@ -156,7 +159,7 @@ extern int code_for_indirect_jump_scratch;
#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
| MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
| MASK_HARD_SH4 | MASK_FPU_SINGLE \
- | MASK_FPU_SINGLE_ONLY)
+ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2)
/* This defaults us to big-endian. */
#ifndef TARGET_ENDIAN_DEFAULT
@@ -231,7 +234,8 @@ extern int code_for_indirect_jump_scratch;
%{m2a-single:--isa=sh2a} \
%{m2a-single-only:--isa=sh2a} \
%{m2a-nofpu:--isa=sh2a-nofpu} \
-%{m4al:-dsp}"
+%{m4al:-dsp} \
+%{mj2:-isa=j2}"
#define ASM_SPEC SH_ASM_SPEC
@@ -347,6 +351,7 @@ struct sh_atomic_model
hard_llcs,
soft_tcb,
soft_imask,
+ hard_cas,
num_models
};
@@ -390,6 +395,9 @@ extern const sh_atomic_model& selected_atomic_model (void);
#define TARGET_ATOMIC_SOFT_IMASK \
(selected_atomic_model ().type == sh_atomic_model::soft_imask)
+#define TARGET_ATOMIC_HARD_CAS \
+ (selected_atomic_model ().type == sh_atomic_model::hard_cas)
+
#endif // __cplusplus
#define SUBTARGET_OVERRIDE_OPTIONS (void) 0
@@ -1484,7 +1492,7 @@ extern bool current_function_interrupt;
/* Nonzero if the target supports dynamic shift instructions
like shad and shld. */
-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
+#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2)
/* The cost of using the dynamic shift insns (shad, shld) are the same
if they are available. If they are not available a library function will
@@ -1747,6 +1755,7 @@ enum processor_type {
PROCESSOR_SH2,
PROCESSOR_SH2E,
PROCESSOR_SH2A,
+ PROCESSOR_SHJ2,
PROCESSOR_SH3,
PROCESSOR_SH3E,
PROCESSOR_SH4,
diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
index 908603b92e1..e6108dabbc6 100644
--- a/gcc/config/sh/sh.opt
+++ b/gcc/config/sh/sh.opt
@@ -65,6 +65,10 @@ m2e
Target RejectNegative Condition(SUPPORT_SH2E)
Generate SH2e code.
+mj2
+Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2)
+Generate J2 code.
+
m3
Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
Generate SH3 code.
diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md
index 25f3b695d2f..55119386a18 100644
--- a/gcc/config/sh/sync.md
+++ b/gcc/config/sh/sync.md
@@ -240,6 +240,9 @@
|| (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem,
exp_val, new_val);
+ else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode)
+ atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem,
+ exp_val, new_val);
else if (TARGET_ATOMIC_SOFT_GUSA)
atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem,
exp_val, new_val);
@@ -306,6 +309,57 @@
}
[(set_attr "length" "14")])
+(define_expand "atomic_compare_and_swapsi_cas"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "r")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{
+ rtx mem = gen_rtx_REG (SImode, 0);
+ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0)));
+ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3]));
+ DONE;
+})
+
+(define_insn "shj2_cas"
+ [(set (match_operand:SI 0 "register_operand" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "register_operand" "=r")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "0")]
+ UNSPECV_CMPXCHG_1))
+ (set (reg:SI T_REG)
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))]
+ "TARGET_ATOMIC_HARD_CAS"
+ "cas.l %2,%0,@%1"
+ [(set_attr "length" "2")]
+)
+
+(define_expand "atomic_compare_and_swapqi_cas"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "arith_operand" "rI08")
+ (match_operand:SI 3 "arith_operand" "rI08")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{FAIL;}
+)
+
+(define_expand "atomic_compare_and_swaphi_cas"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "arith_operand" "rI08")
+ (match_operand:SI 3 "arith_operand" "rI08")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{FAIL;}
+)
+
;; The QIHImode llcs patterns modify the address register of the memory
;; operand. In order to express that, we have to open code the memory
;; operand. Initially the insn is expanded like every other atomic insn
diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh
index a402359be72..dbd0bf992bf 100644
--- a/gcc/config/sh/t-sh
+++ b/gcc/config/sh/t-sh
@@ -50,7 +50,8 @@ MULTILIB_MATCHES = $(shell \
m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \
m2a-single,m2a-single-only \
m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
- m4,m4-100,m4-200,m4-300,m4a; do \
+ m4,m4-100,m4-200,m4-300,m4a \
+ mj2; do \
subst= ; \
for lib in `echo $$abi|tr , ' '` ; do \
if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \
@@ -63,9 +64,9 @@ MULTILIB_MATCHES = $(shell \
# SH1 and SH2A support big endian only.
ifeq ($(DEFAULT_ENDIAN),ml)
-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
else
-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
endif
MULTILIB_OSDIRNAMES = \
@@ -87,7 +88,8 @@ MULTILIB_OSDIRNAMES = \
m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \
m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \
m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \
- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al
+ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \
+ mj2=!j2
$(out_object_file): gt-sh.h
gt-sh.h : s-gtype ; @true

92
patches/gcc-10.3.0/0004-static-pie.diff Normal file
View File

@@ -0,0 +1,92 @@
diff --git a/gcc/common.opt b/gcc/common.opt
index ec5235c3a41..dcee05500ba 100644
--- a/gcc/common.opt
+++ b/gcc/common.opt
@@ -3401,11 +3401,11 @@ Driver
no-pie
Driver RejectNegative Negative(shared)
-Don't create a dynamically linked position independent executable.
+Don't create a position independent executable.
pie
Driver RejectNegative Negative(no-pie)
-Create a dynamically linked position independent executable.
+Create a position independent executable.
static-pie
Driver RejectNegative Negative(pie)
diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h
index ff2e880b1fa..bafde149202 100644
--- a/gcc/config/gnu-user.h
+++ b/gcc/config/gnu-user.h
@@ -51,13 +51,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define GNU_USER_TARGET_STARTFILE_SPEC \
"%{shared:; \
pg|p|profile:%{static-pie:grcrt1.o%s;:gcrt1.o%s}; \
- static:crt1.o%s; \
- static-pie:rcrt1.o%s; \
+ static|static-pie:%{" PIE_SPEC ":rcrt1.o%s;:crt1.o%s}; \
" PIE_SPEC ":Scrt1.o%s; \
:crt1.o%s} " \
GNU_USER_TARGET_CRTI " \
- %{static:crtbeginT.o%s; \
- shared|static-pie|" PIE_SPEC ":crtbeginS.o%s; \
+ %{shared|" PIE_SPEC ":crtbeginS.o%s; \
+ static:crtbeginT.o%s; \
:crtbegin.o%s} \
%{fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_start_preinit.o%s; \
@@ -73,11 +72,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
GNU userspace "finalizer" file, `crtn.o'. */
#define GNU_USER_TARGET_ENDFILE_SPEC \
- "%{!static:%{fvtable-verify=none:%s; \
+ "%{static|static-pie:; \
+ fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_end_preinit.o%s; \
- fvtable-verify=std:vtv_end.o%s}} \
- %{static:crtend.o%s; \
- shared|static-pie|" PIE_SPEC ":crtendS.o%s; \
+ fvtable-verify=std:vtv_end.o%s} \
+ %{shared|" PIE_SPEC ":crtendS.o%s; \
:crtend.o%s} " \
GNU_USER_TARGET_CRTN " " \
CRTOFFLOADEND
@@ -106,7 +105,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define LIB_SPEC GNU_USER_TARGET_LIB_SPEC
#if defined(HAVE_LD_EH_FRAME_HDR)
-#define LINK_EH_SPEC "%{!static|static-pie:--eh-frame-hdr} "
+#define LINK_EH_SPEC "%{!static|" PIE_SPEC ":--eh-frame-hdr} "
#endif
#define GNU_USER_TARGET_LINK_GCC_C_SEQUENCE_SPEC \
diff --git a/gcc/gcc.c b/gcc/gcc.c
index e6887590ae2..df6e3965f13 100644
--- a/gcc/gcc.c
+++ b/gcc/gcc.c
@@ -907,7 +907,7 @@ proper position among the other output files. */
#define NO_FPIE_AND_FPIC_SPEC NO_FPIE_SPEC "|" NO_FPIC_SPEC
#define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;"
#else
-#define PIE_SPEC "pie"
+#define PIE_SPEC "pie|static-pie"
#define FPIE1_SPEC "fpie"
#define NO_FPIE1_SPEC FPIE1_SPEC ":;"
#define FPIE2_SPEC "fPIE"
@@ -931,12 +931,12 @@ proper position among the other output files. */
#ifndef LINK_PIE_SPEC
#ifdef HAVE_LD_PIE
#ifndef LD_PIE_SPEC
-#define LD_PIE_SPEC "-pie"
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}"
#endif
#else
#define LD_PIE_SPEC ""
#endif
-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
+#define LINK_PIE_SPEC "%{shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
#endif
#ifndef LINK_BUILDID_SPEC

30
patches/gcc-10.3.0/0005-libstdc-futex-time64.diff Normal file
View File

@@ -0,0 +1,30 @@
diff --git a/libstdc++-v3/src/c++11/futex.cc b/libstdc++-v3/src/c++11/futex.cc
index 698737d9b21..230d32574c6 100644
--- a/libstdc++-v3/src/c++11/futex.cc
+++ b/libstdc++-v3/src/c++11/futex.cc
@@ -46,13 +46,23 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
namespace
{
+#if defined(SYS_futex_time64) && SYS_futex_time64 != SYS_futex
+ typedef struct
+ {
+ long tv_sec;
+ long tv_nsec;
+ } sys_timespec;
+#else
+ typedef struct timespec sys_timespec;
+#endif
+
// Return the relative duration from (now_s + now_ns) to (abs_s + abs_ns)
// as a timespec.
- struct timespec
+ sys_timespec
relative_timespec(chrono::seconds abs_s, chrono::nanoseconds abs_ns,
time_t now_s, long now_ns)
{
- struct timespec rt;
+ sys_timespec rt;
// Did we already time out?
if (now_s > abs_s.count())

20
patches/gcc-10.3.0/0006-m68k-sqrt.diff Normal file
View File

@@ -0,0 +1,20 @@
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 8e35357ea23..65c8b10b3eb 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -4174,13 +4174,13 @@
(define_expand "sqrt<mode>2"
[(set (match_operand:FP 0 "nonimmediate_operand" "")
(sqrt:FP (match_operand:FP 1 "general_operand" "")))]
- "TARGET_HARD_FLOAT"
+ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU"
"")
(define_insn "sqrt<mode>2_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
- "TARGET_68881"
+ "TARGET_68881 && TARGET_68040"
{
if (FP_REG_P (operands[1]))
return "f<FP:round>sqrt%.x %1,%0";

14
patches/gcc-11.2.0/0001-ssp_nonshared.diff Normal file
View File

@@ -0,0 +1,14 @@
diff --git a/gcc/gcc.c b/gcc/gcc.c
index 7837553958b..3c81c5798d8 100644
--- a/gcc/gcc.c
+++ b/gcc/gcc.c
@@ -980,7 +980,8 @@ proper position among the other output files. */
#ifndef LINK_SSP_SPEC
#ifdef TARGET_LIBC_PROVIDES_SSP
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
- "|fstack-protector-strong|fstack-protector-explicit:}"
+ "|fstack-protector-strong|fstack-protector-explicit" \
+ ":-lssp_nonshared}"
#else
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
"|fstack-protector-strong|fstack-protector-explicit" \

30
patches/gcc-11.2.0/0002-posix_memalign.diff Normal file
View File

@@ -0,0 +1,30 @@
diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h
index 1b0bfe37852..d7b2b19bb3c 100644
--- a/gcc/config/i386/pmm_malloc.h
+++ b/gcc/config/i386/pmm_malloc.h
@@ -27,12 +27,13 @@
#include <stdlib.h>
/* We can't depend on <stdlib.h> since the prototype of posix_memalign
- may not be visible. */
+ may not be visible and we can't pollute the namespace either. */
#ifndef __cplusplus
-extern int posix_memalign (void **, size_t, size_t);
+extern int _mm_posix_memalign (void **, size_t, size_t)
#else
-extern "C" int posix_memalign (void **, size_t, size_t) throw ();
+extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw ()
#endif
+__asm__("posix_memalign");
static __inline void *
_mm_malloc (size_t __size, size_t __alignment)
@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment)
return malloc (__size);
if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4))
__alignment = sizeof (void *);
- if (posix_memalign (&__ptr, __alignment, __size) == 0)
+ if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0)
return __ptr;
else
return NULL;

346
patches/gcc-11.2.0/0003-j2.diff Normal file
View File

@@ -0,0 +1,346 @@
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 357b0bed067..528add999f2 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -556,7 +556,7 @@ s390*-*-*)
extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h"
;;
# Note the 'l'; we need to be able to match e.g. "shle" or "shl".
-sh[123456789lbe]*-*-* | sh-*-*)
+sh[123456789lbej]*-*-* | sh-*-*)
cpu_type=sh
extra_options="${extra_options} fused-madd.opt"
extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o"
@@ -3202,18 +3202,18 @@ s390x-ibm-tpf*)
extra_options="${extra_options} s390/tpf.opt"
tmake_file="${tmake_file} s390/t-s390"
;;
-sh-*-elf* | sh[12346l]*-*-elf* | \
- sh-*-linux* | sh[2346lbe]*-*-linux* | \
+sh-*-elf* | sh[12346lj]*-*-elf* | \
+ sh-*-linux* | sh[2346lbej]*-*-linux* | \
sh-*-netbsdelf* | shl*-*-netbsdelf*)
tmake_file="${tmake_file} sh/t-sh sh/t-elf"
if test x${with_endian} = x; then
case ${target} in
- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;;
+ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;;
shbe-*-* | sheb-*-*) with_endian=big,little ;;
sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;;
shl* | sh*-*-linux* | \
sh-superh-elf) with_endian=little,big ;;
- sh[1234]*-*-*) with_endian=big ;;
+ sh[j1234]*-*-*) with_endian=big ;;
*) with_endian=big,little ;;
esac
fi
@@ -3280,6 +3280,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;;
sh2a*) sh_cpu_target=sh2a ;;
sh2e*) sh_cpu_target=sh2e ;;
+ shj2*) sh_cpu_target=shj2;;
sh2*) sh_cpu_target=sh2 ;;
*) sh_cpu_target=sh1 ;;
esac
@@ -3301,7 +3302,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
- sh3e | sh3 | sh2e | sh2 | sh1) ;;
+ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;;
"") sh_cpu_default=${sh_cpu_target} ;;
*) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
esac
@@ -3310,9 +3311,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
case ${target} in
sh[1234]*) sh_multilibs=${sh_cpu_target} ;;
sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;;
+ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;;
sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;;
- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
+ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;;
esac
if test x$with_fp = xno; then
sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
@@ -3327,7 +3328,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
m1 | m2 | m2e | m3 | m3e | \
m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \
- m2a | m2a-single | m2a-single-only | m2a-nofpu)
+ m2a | m2a-single | m2a-single-only | m2a-nofpu | \
+ mj2)
# TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
# It is passed to MULTIILIB_OPTIONS verbatim.
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
@@ -3344,7 +3346,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
done
TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
if test x${enable_incomplete_targets} = xyes ; then
- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1"
+ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1"
fi
tm_file="$tm_file ./sysroot-suffix.h"
tmake_file="$tmake_file t-sysroot-suffix"
@@ -5175,6 +5177,8 @@ case "${target}" in
;;
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
;;
+ mj2)
+ ;;
*)
echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2
echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
@@ -5385,7 +5389,7 @@ case ${target} in
tmake_file="${cpu_type}/t-${cpu_type} ${tmake_file}"
;;
- sh[123456ble]*-*-* | sh-*-*)
+ sh[123456blej]*-*-* | sh-*-*)
c_target_objs="${c_target_objs} sh-c.o"
cxx_target_objs="${cxx_target_objs} sh-c.o"
;;
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 1564109c942..798c1c1c1a3 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -686,6 +686,7 @@ parse_validate_atomic_model_option (const char* str)
model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
model_names[sh_atomic_model::soft_imask] = "soft-imask";
+ model_names[sh_atomic_model::hard_cas] = "hard-cas";
const char* model_cdef_names[sh_atomic_model::num_models];
model_cdef_names[sh_atomic_model::none] = "NONE";
@@ -693,6 +694,7 @@ parse_validate_atomic_model_option (const char* str)
model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
+ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS";
sh_atomic_model ret;
ret.type = sh_atomic_model::none;
@@ -771,6 +773,9 @@ got_mode_name:;
if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
err_ret ("cannot use atomic model %s in user mode", ret.name);
+ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2)
+ err_ret ("atomic model %s is only available J2 targets", ret.name);
+
return ret;
#undef err_ret
@@ -827,6 +832,8 @@ sh_option_override (void)
sh_cpu = PROCESSOR_SH2E;
if (TARGET_SH2A)
sh_cpu = PROCESSOR_SH2A;
+ if (TARGET_SHJ2)
+ sh_cpu = PROCESSOR_SHJ2;
if (TARGET_SH3)
sh_cpu = PROCESSOR_SH3;
if (TARGET_SH3E)
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index d2280e2ffe6..3a54a896721 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -85,6 +85,7 @@ extern int code_for_indirect_jump_scratch;
#define SUPPORT_SH4_SINGLE 1
#define SUPPORT_SH2A 1
#define SUPPORT_SH2A_SINGLE 1
+#define SUPPORT_SHJ2 1
#endif
#define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
@@ -117,6 +118,7 @@ extern int code_for_indirect_jump_scratch;
#define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
#define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
#define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
+#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2)
#if SUPPORT_SH1
#define SUPPORT_SH2 1
@@ -124,6 +126,7 @@ extern int code_for_indirect_jump_scratch;
#if SUPPORT_SH2
#define SUPPORT_SH3 1
#define SUPPORT_SH2A_NOFPU 1
+#define SUPPORT_SHJ2 1
#endif
#if SUPPORT_SH3
#define SUPPORT_SH4_NOFPU 1
@@ -156,7 +159,7 @@ extern int code_for_indirect_jump_scratch;
#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
| MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
| MASK_HARD_SH4 | MASK_FPU_SINGLE \
- | MASK_FPU_SINGLE_ONLY)
+ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2)
/* This defaults us to big-endian. */
#ifndef TARGET_ENDIAN_DEFAULT
@@ -231,7 +234,8 @@ extern int code_for_indirect_jump_scratch;
%{m2a-single:--isa=sh2a} \
%{m2a-single-only:--isa=sh2a} \
%{m2a-nofpu:--isa=sh2a-nofpu} \
-%{m4al:-dsp}"
+%{m4al:-dsp} \
+%{mj2:-isa=j2}"
#define ASM_SPEC SH_ASM_SPEC
@@ -347,6 +351,7 @@ struct sh_atomic_model
hard_llcs,
soft_tcb,
soft_imask,
+ hard_cas,
num_models
};
@@ -390,6 +395,9 @@ extern const sh_atomic_model& selected_atomic_model (void);
#define TARGET_ATOMIC_SOFT_IMASK \
(selected_atomic_model ().type == sh_atomic_model::soft_imask)
+#define TARGET_ATOMIC_HARD_CAS \
+ (selected_atomic_model ().type == sh_atomic_model::hard_cas)
+
#endif // __cplusplus
#define SUBTARGET_OVERRIDE_OPTIONS (void) 0
@@ -1484,7 +1492,7 @@ extern bool current_function_interrupt;
/* Nonzero if the target supports dynamic shift instructions
like shad and shld. */
-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
+#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2)
/* The cost of using the dynamic shift insns (shad, shld) are the same
if they are available. If they are not available a library function will
@@ -1747,6 +1755,7 @@ enum processor_type {
PROCESSOR_SH2,
PROCESSOR_SH2E,
PROCESSOR_SH2A,
+ PROCESSOR_SHJ2,
PROCESSOR_SH3,
PROCESSOR_SH3E,
PROCESSOR_SH4,
diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
index b4755a812f3..0989a1c18da 100644
--- a/gcc/config/sh/sh.opt
+++ b/gcc/config/sh/sh.opt
@@ -65,6 +65,10 @@ m2e
Target RejectNegative Condition(SUPPORT_SH2E)
Generate SH2e code.
+mj2
+Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2)
+Generate J2 code.
+
m3
Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
Generate SH3 code.
diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md
index 2b43f8edb86..118fc5d06db 100644
--- a/gcc/config/sh/sync.md
+++ b/gcc/config/sh/sync.md
@@ -240,6 +240,9 @@
|| (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem,
exp_val, new_val);
+ else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode)
+ atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem,
+ exp_val, new_val);
else if (TARGET_ATOMIC_SOFT_GUSA)
atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem,
exp_val, new_val);
@@ -306,6 +309,57 @@
}
[(set_attr "length" "14")])
+(define_expand "atomic_compare_and_swapsi_cas"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "r")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{
+ rtx mem = gen_rtx_REG (SImode, 0);
+ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0)));
+ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3]));
+ DONE;
+})
+
+(define_insn "shj2_cas"
+ [(set (match_operand:SI 0 "register_operand" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "register_operand" "=r")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "0")]
+ UNSPECV_CMPXCHG_1))
+ (set (reg:SI T_REG)
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))]
+ "TARGET_ATOMIC_HARD_CAS"
+ "cas.l %2,%0,@%1"
+ [(set_attr "length" "2")]
+)
+
+(define_expand "atomic_compare_and_swapqi_cas"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "arith_operand" "rI08")
+ (match_operand:SI 3 "arith_operand" "rI08")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{FAIL;}
+)
+
+(define_expand "atomic_compare_and_swaphi_cas"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "arith_operand" "rI08")
+ (match_operand:SI 3 "arith_operand" "rI08")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{FAIL;}
+)
+
;; The QIHImode llcs patterns modify the address register of the memory
;; operand. In order to express that, we have to open code the memory
;; operand. Initially the insn is expanded like every other atomic insn
diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh
index 888f8ff7f25..29fd6ae45fd 100644
--- a/gcc/config/sh/t-sh
+++ b/gcc/config/sh/t-sh
@@ -50,7 +50,8 @@ MULTILIB_MATCHES = $(shell \
m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \
m2a-single,m2a-single-only \
m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
- m4,m4-100,m4-200,m4-300,m4a; do \
+ m4,m4-100,m4-200,m4-300,m4a \
+ mj2; do \
subst= ; \
for lib in `echo $$abi|tr , ' '` ; do \
if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \
@@ -63,9 +64,9 @@ MULTILIB_MATCHES = $(shell \
# SH1 and SH2A support big endian only.
ifeq ($(DEFAULT_ENDIAN),ml)
-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
else
-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
endif
MULTILIB_OSDIRNAMES = \
@@ -87,7 +88,8 @@ MULTILIB_OSDIRNAMES = \
m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \
m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \
m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \
- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al
+ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \
+ mj2=!j2
$(out_object_file): gt-sh.h
gt-sh.h : s-gtype ; @true

92
patches/gcc-11.2.0/0004-static-pie.diff Normal file
View File

@@ -0,0 +1,92 @@
diff --git a/gcc/common.opt b/gcc/common.opt
index a75b44ee47e..7c564818b49 100644
--- a/gcc/common.opt
+++ b/gcc/common.opt
@@ -3473,11 +3473,11 @@ Driver
no-pie
Driver RejectNegative Negative(shared)
-Don't create a dynamically linked position independent executable.
+Don't create a position independent executable.
pie
Driver RejectNegative Negative(no-pie)
-Create a dynamically linked position independent executable.
+Create a position independent executable.
static-pie
Driver RejectNegative Negative(pie)
diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h
index 5ebbf42a13d..bb907d8e89a 100644
--- a/gcc/config/gnu-user.h
+++ b/gcc/config/gnu-user.h
@@ -51,13 +51,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define GNU_USER_TARGET_STARTFILE_SPEC \
"%{shared:; \
pg|p|profile:%{static-pie:grcrt1.o%s;:gcrt1.o%s}; \
- static:crt1.o%s; \
- static-pie:rcrt1.o%s; \
+ static|static-pie:%{" PIE_SPEC ":rcrt1.o%s;:crt1.o%s}; \
" PIE_SPEC ":Scrt1.o%s; \
:crt1.o%s} " \
GNU_USER_TARGET_CRTI " \
- %{static:crtbeginT.o%s; \
- shared|static-pie|" PIE_SPEC ":crtbeginS.o%s; \
+ %{shared|" PIE_SPEC ":crtbeginS.o%s; \
+ static:crtbeginT.o%s; \
:crtbegin.o%s} \
%{fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_start_preinit.o%s; \
@@ -73,11 +72,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
GNU userspace "finalizer" file, `crtn.o'. */
#define GNU_USER_TARGET_ENDFILE_SPEC \
- "%{!static:%{fvtable-verify=none:%s; \
+ "%{static|static-pie:; \
+ fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_end_preinit.o%s; \
- fvtable-verify=std:vtv_end.o%s}} \
- %{static:crtend.o%s; \
- shared|static-pie|" PIE_SPEC ":crtendS.o%s; \
+ fvtable-verify=std:vtv_end.o%s} \
+ %{shared|" PIE_SPEC ":crtendS.o%s; \
:crtend.o%s} " \
GNU_USER_TARGET_CRTN " " \
CRTOFFLOADEND
@@ -106,7 +105,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define LIB_SPEC GNU_USER_TARGET_LIB_SPEC
#if defined(HAVE_LD_EH_FRAME_HDR)
-#define LINK_EH_SPEC "%{!static|static-pie:--eh-frame-hdr} "
+#define LINK_EH_SPEC "%{!static|" PIE_SPEC ":--eh-frame-hdr} "
#endif
#define GNU_USER_TARGET_LINK_GCC_C_SEQUENCE_SPEC \
diff --git a/gcc/gcc.c b/gcc/gcc.c
index 3c81c5798d8..cd96eac5d12 100644
--- a/gcc/gcc.c
+++ b/gcc/gcc.c
@@ -1010,7 +1010,7 @@ proper position among the other output files. */
#define NO_FPIE_AND_FPIC_SPEC NO_FPIE_SPEC "|" NO_FPIC_SPEC
#define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;"
#else
-#define PIE_SPEC "pie"
+#define PIE_SPEC "pie|static-pie"
#define FPIE1_SPEC "fpie"
#define NO_FPIE1_SPEC FPIE1_SPEC ":;"
#define FPIE2_SPEC "fPIE"
@@ -1034,12 +1034,12 @@ proper position among the other output files. */
#ifndef LINK_PIE_SPEC
#ifdef HAVE_LD_PIE
#ifndef LD_PIE_SPEC
-#define LD_PIE_SPEC "-pie"
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}"
#endif
#else
#define LD_PIE_SPEC ""
#endif
-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
+#define LINK_PIE_SPEC "%{shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
#endif
#ifndef LINK_BUILDID_SPEC

20
patches/gcc-11.2.0/0005-m68k-sqrt.diff Normal file
View File

@@ -0,0 +1,20 @@
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 59a456cd496..dbfddea41bd 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -4174,13 +4174,13 @@
(define_expand "sqrt<mode>2"
[(set (match_operand:FP 0 "nonimmediate_operand" "")
(sqrt:FP (match_operand:FP 1 "general_operand" "")))]
- "TARGET_HARD_FLOAT"
+ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU"
"")
(define_insn "sqrt<mode>2_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
- "TARGET_68881"
+ "TARGET_68881 && TARGET_68040"
{
if (FP_REG_P (operands[1]))
return "f<FP:round>sqrt%.x %1,%0";

360
patches/gcc-4.2.1/0001-musl.diff Normal file
View File

@@ -0,0 +1,360 @@
diff --git a/config.sub b/config.sub
index fab0aa3..b83660a 100755
--- a/config.sub
+++ b/config.sub
@@ -120,7 +120,7 @@ esac
# Here we must recognize all the valid KERNEL-OS combinations.
maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'`
case $maybe_os in
- nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | \
+ nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | linux-musl* | \
uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | \
storm-chaos* | os2-emx* | rtmk-nova*)
os=-$maybe_os
@@ -1211,7 +1211,7 @@ case $os in
| -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \
| -chorusos* | -chorusrdb* \
| -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \
- | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* \
+ | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* | -linux-musl* \
| -uxpv* | -beos* | -mpeix* | -udk* \
| -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \
| -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \
diff --git a/fixincludes/mkfixinc.sh b/fixincludes/mkfixinc.sh
index ef048f7..f1cb8a5 100755
--- a/fixincludes/mkfixinc.sh
+++ b/fixincludes/mkfixinc.sh
@@ -28,7 +28,8 @@ case $machine in
powerpc-*-eabi* | \
powerpc-*-rtems* | \
powerpcle-*-eabisim* | \
- powerpcle-*-eabi* )
+ powerpcle-*-eabi* | \
+ *-musl* )
# IF there is no include fixing,
# THEN create a no-op fixer and exit
(echo "#! /bin/sh" ; echo "exit 0" ) > ${target}
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 9a142e2..25136b7 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -468,11 +468,14 @@ case ${target} in
esac
tmake_file="t-slibgcc-elf-ver t-linux"
case ${target} in
+ *-*-*musl*)
+ tm_defines="${tm_defines} UCLIBC_DEFAULT=0 MUSL_DEFAULT=1"
+ ;;
*-*-*uclibc*)
- tm_defines="${tm_defines} UCLIBC_DEFAULT=1"
+ tm_defines="${tm_defines} UCLIBC_DEFAULT=1 MUSL_DEFAULT=0"
;;
*)
- tm_defines="${tm_defines} UCLIBC_DEFAULT=0"
+ tm_defines="${tm_defines} UCLIBC_DEFAULT=0 MUSL_DEFAULT=0"
;;
esac
# Assume that glibc or uClibc are being used and so __cxa_atexit is provided.
diff --git a/gcc/config/arm/linux-eabi.h b/gcc/config/arm/linux-eabi.h
index 6612f74..f2ce735 100644
--- a/gcc/config/arm/linux-eabi.h
+++ b/gcc/config/arm/linux-eabi.h
@@ -55,6 +55,23 @@
#undef GLIBC_DYNAMIC_LINKER
#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.3"
+/* For ARM musl currently supports four dynamic linkers:
+ - ld-musl-arm.so.1 - for the EABI-derived soft-float ABI
+ - ld-musl-armhf.so.1 - for the EABI-derived hard-float ABI
+ - ld-musl-armeb.so.1 - for the EABI-derived soft-float ABI, EB
+ - ld-musl-armebhf.so.1 - for the EABI-derived hard-float ABI, EB
+ musl does not support the legacy OABI mode.
+ All the dynamic linkers live in /lib.
+ We default to soft-float, EL. */
+#undef MUSL_DYNAMIC_LINKER
+#if TARGET_BIG_ENDIAN_DEFAULT
+#define MUSL_DYNAMIC_LINKER_E "%{mlittle-endian:;:eb}"
+#else
+#define MUSL_DYNAMIC_LINKER_E "%{mbig-endian:eb}"
+#endif
+#define MUSL_DYNAMIC_LINKER \
+ "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}.so.1"
+
/* At this point, bpabi.h will have clobbered LINK_SPEC. We want to
use the GNU/Linux version, not the generic BPABI version. */
#undef LINK_SPEC
diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h
index 7eb2395..213b586 100644
--- a/gcc/config/i386/linux.h
+++ b/gcc/config/i386/linux.h
@@ -103,6 +103,9 @@ Boston, MA 02110-1301, USA. */
#define LINK_EMULATION "elf_i386"
#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+#undef MUSL_DYNAMIC_LINKER
+#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-i386.so.1"
+
#undef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS \
{ "link_emulation", LINK_EMULATION },\
diff --git a/gcc/config/i386/linux64.h b/gcc/config/i386/linux64.h
index cc8ed16..f0f025e 100644
--- a/gcc/config/i386/linux64.h
+++ b/gcc/config/i386/linux64.h
@@ -52,6 +52,13 @@ Boston, MA 02110-1301, USA. */
#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
+#undef MUSL_DYNAMIC_LINKER32
+#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-i386.so.1"
+#undef MUSL_DYNAMIC_LINKER64
+#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-x86_64.so.1"
+#undef MUSL_DYNAMIC_LINKERX32
+#define MUSL_DYNAMIC_LINKERX32 "/lib/ld-musl-x32.so.1"
+
#undef LINK_SPEC
#define LINK_SPEC "%{!m32:-m elf_x86_64} %{m32:-m elf_i386} \
%{shared:-shared} \
diff --git a/gcc/config/linux.h b/gcc/config/linux.h
index 59e3e85..1967b46 100644
--- a/gcc/config/linux.h
+++ b/gcc/config/linux.h
@@ -102,10 +102,12 @@ Boston, MA 02110-1301, USA. */
/* Determine which dynamic linker to use depending on whether GLIBC or
uClibc is the default C library and whether -muclibc or -mglibc has
been passed to change the default. */
-#if UCLIBC_DEFAULT
-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:%{muclibc:%e-mglibc and -muclibc used together}" G ";:" U "}"
+#if MUSL_DEFAULT
+#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";muclibc:" U ";:" M "}"
+#elif UCLIBC_DEFAULT
+#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";mmusl:" M ";:" U "}"
#else
-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:%{mglibc:%e-mglibc and -muclibc used together}" U ";:" G "}"
+#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mmusl:" M ";muclibc:" U ";:" G "}"
#endif
/* For most targets the following definitions suffice;
@@ -115,15 +117,89 @@ Boston, MA 02110-1301, USA. */
#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
+/* Should be redefined for each target that supports musl. */
+#define MUSL_DYNAMIC_LINKER "/dev/null"
+#define MUSL_DYNAMIC_LINKER32 "/dev/null"
+#define MUSL_DYNAMIC_LINKER64 "/dev/null"
+#define MUSL_DYNAMIC_LINKERX32 "/dev/null"
+
#define LINUX_DYNAMIC_LINKER \
- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER)
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER, MUSL_DYNAMIC_LINKER)
#define LINUX_DYNAMIC_LINKER32 \
- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32)
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32, MUSL_DYNAMIC_LINKER32)
#define LINUX_DYNAMIC_LINKER64 \
- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64)
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64, MUSL_DYNAMIC_LINKER64)
/* Determine whether the entire c99 runtime
is present in the runtime library. */
#define TARGET_C99_FUNCTIONS (OPTION_GLIBC)
#define TARGET_POSIX_IO
+
+/* musl avoids problematic includes by rearranging the include directories.
+ * Unfortunately, this is mostly duplicated from cppdefault.c */
+#if MUSL_DEFAULT
+#define INCLUDE_DEFAULTS_MUSL_GPP \
+ { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, 0, 0 }, \
+ { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, 0, 1 }, \
+ { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, 0, 0 },
+
+#ifdef LOCAL_INCLUDE_DIR
+#define INCLUDE_DEFAULTS_MUSL_LOCAL \
+ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, \
+ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 },
+#else
+#define INCLUDE_DEFAULTS_MUSL_LOCAL
+#endif
+
+#ifdef PREFIX_INCLUDE_DIR
+#define INCLUDE_DEFAULTS_MUSL_PREFIX \
+ { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0},
+#else
+#define INCLUDE_DEFAULTS_MUSL_PREFIX
+#endif
+
+#ifdef CROSS_INCLUDE_DIR
+#define INCLUDE_DEFAULTS_MUSL_CROSS \
+ { CROSS_INCLUDE_DIR, "GCC", 0, 0, 0, 0},
+#else
+#define INCLUDE_DEFAULTS_MUSL_CROSS
+#endif
+
+#ifdef TOOL_INCLUDE_DIR
+#define INCLUDE_DEFAULTS_MUSL_TOOL \
+ { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1, 0, 0},
+#else
+#define INCLUDE_DEFAULTS_MUSL_TOOL
+#endif
+
+#ifdef NATIVE_SYSTEM_HEADER_DIR
+#define INCLUDE_DEFAULTS_MUSL_NATIVE \
+ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 }, \
+ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 0 },
+#else
+#define INCLUDE_DEFAULTS_MUSL_NATIVE
+#endif
+
+#if defined (CROSS_DIRECTORY_STRUCTURE) && !defined (TARGET_SYSTEM_ROOT)
+# undef INCLUDE_DEFAULTS_MUSL_LOCAL
+# define INCLUDE_DEFAULTS_MUSL_LOCAL
+# undef INCLUDE_DEFAULTS_MUSL_NATIVE
+# define INCLUDE_DEFAULTS_MUSL_NATIVE
+#else
+# undef INCLUDE_DEFAULTS_MUSL_CROSS
+# define INCLUDE_DEFAULTS_MUSL_CROSS
+#endif
+
+#undef INCLUDE_DEFAULTS
+#define INCLUDE_DEFAULTS \
+ { \
+ INCLUDE_DEFAULTS_MUSL_GPP \
+ INCLUDE_DEFAULTS_MUSL_PREFIX \
+ INCLUDE_DEFAULTS_MUSL_CROSS \
+ INCLUDE_DEFAULTS_MUSL_TOOL \
+ INCLUDE_DEFAULTS_MUSL_NATIVE \
+ { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 }, \
+ { 0, 0, 0, 0, 0, 0 } \
+ }
+#endif
diff --git a/gcc/config/linux.opt b/gcc/config/linux.opt
index 3f615bb..31fb21b 100644
--- a/gcc/config/linux.opt
+++ b/gcc/config/linux.opt
@@ -27,3 +27,7 @@ Use uClibc instead of GNU libc
mglibc
Target RejectNegative Report InverseMask(UCLIBC, GLIBC) Var(linux_uclibc) VarExists
Use GNU libc instead of uClibc
+
+mmusl
+Target RejectNegative Report Var(linux_musl)
+Use musl C library
diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h
index ff268d4..97bfc38 100644
--- a/gcc/config/mips/linux.h
+++ b/gcc/config/mips/linux.h
@@ -179,3 +179,9 @@ Boston, MA 02110-1301, USA. */
%{profile:-lc_p} %{!profile: -lc}}"
#define MD_UNWIND_SUPPORT "config/mips/linux-unwind.h"
+
+#undef MUSL_DYNAMIC_LINKER32
+#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-mips%{EL:el}%{msoft-float:-sf}.so.1"
+#undef MUSL_DYNAMIC_LINKER64
+#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-mips64%{EL:el}%{msoft-float:-sf}.so.1"
+#define MUSL_DYNAMIC_LINKERN32 "/lib/ld-musl-mipsn32%{EL:el}%{msoft-float:-sf}.so.1"
diff --git a/gcc/config/sh/linux-unwind.h b/gcc/config/sh/linux-unwind.h
index de84a77..98d1661 100644
--- a/gcc/config/sh/linux-unwind.h
+++ b/gcc/config/sh/linux-unwind.h
@@ -80,10 +80,10 @@ shmedia_fallback_frame_state (struct _Unwind_Context *context,
&& (*(unsigned long *) (pc+11) == 0x6ff0fff0))
{
struct rt_sigframe {
- struct siginfo *pinfo;
+ siginfo_t *pinfo;
void *puc;
- struct siginfo info;
- struct ucontext uc;
+ siginfo_t info;
+ ucontext_t uc;
} *rt_ = context->cfa;
/* The void * cast is necessary to avoid an aliasing warning.
The aliasing warning is correct, but should not be a problem
@@ -179,8 +179,8 @@ sh_fallback_frame_state (struct _Unwind_Context *context,
&& (*(unsigned short *) (pc+14) == 0x00ad))))
{
struct rt_sigframe {
- struct siginfo info;
- struct ucontext uc;
+ siginfo_t info;
+ ucontext_t uc;
} *rt_ = context->cfa;
/* The void * cast is necessary to avoid an aliasing warning.
The aliasing warning is correct, but should not be a problem
diff --git a/gcc/config/sh/linux.h b/gcc/config/sh/linux.h
index 94c3166..306a08c 100644
--- a/gcc/config/sh/linux.h
+++ b/gcc/config/sh/linux.h
@@ -48,6 +48,29 @@ Boston, MA 02110-1301, USA. */
#define TARGET_ASM_FILE_END file_end_indicate_exec_stack
+#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
+#define MUSL_DYNAMIC_LINKER_E "%{mb:eb}"
+#else
+#define MUSL_DYNAMIC_LINKER_E "%{!ml:eb}"
+#endif
+
+#if TARGET_CPU_DEFAULT & ( MASK_HARD_SH2A_DOUBLE | MASK_SH4 )
+/* "-nofpu" if any nofpu option is specified */
+#define MUSL_DYNAMIC_LINKER_FP \
+ "%{m1|m2|m2a-nofpu|m3|m4-nofpu|m4-100-nofpu|m4-200-nofpu|m4-300-nofpu|" \
+ "m4-340|m4-400|m4-500|m4al|m5-32media-nofpu|m5-64media-nofpu|" \
+ "m5-compact-nofpu:-nofpu}"
+#else
+/* "-nofpu" if none of the hard fpu options are specified */
+#define MUSL_DYNAMIC_LINKER_FP \
+ "%{m2a|m4|m4-100|m4-200|m4-300|m4a|m5-32media|m5-64media|m5-compact:;:-nofpu}"
+#endif
+
+#undef MUSL_DYNAMIC_LINKER
+#define MUSL_DYNAMIC_LINKER \
+ "/lib/ld-musl-sh" MUSL_DYNAMIC_LINKER_E MUSL_DYNAMIC_LINKER_FP \
+ "%{mfdpic:-fdpic}.so.1"
+
#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
#undef SUBTARGET_LINK_EMUL_SUFFIX
diff --git a/gcc/unwind-dw2-fde-glibc.c b/gcc/unwind-dw2-fde-glibc.c
index 25bf2bb..59f7615 100644
--- a/gcc/unwind-dw2-fde-glibc.c
+++ b/gcc/unwind-dw2-fde-glibc.c
@@ -49,7 +49,7 @@
#include "gthr.h"
#if !defined(inhibit_libc) && defined(HAVE_LD_EH_FRAME_HDR) \
- && (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ > 2) \
+ && (!defined(__GLIBC__) || __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ > 2) \
|| (__GLIBC__ == 2 && __GLIBC_MINOR__ == 2 && defined(DT_CONFIG)))
#ifndef __RELOC_POINTER
diff --git a/libstdc++-v3/config/os/generic/os_defines.h b/libstdc++-v3/config/os/generic/os_defines.h
index bcc533c..a9bfded 100644
--- a/libstdc++-v3/config/os/generic/os_defines.h
+++ b/libstdc++-v3/config/os/generic/os_defines.h
@@ -38,4 +38,9 @@
// System-specific #define, typedefs, corrections, etc, go here. This
// file will come before all others.
+// Disable the weak reference logic in gthr.h for os/generic because it
+// is broken on every platform unless there is implementation specific
+// workaround in gthr-posix.h and at link-time for static linking.
+#define _GLIBCXX_GTHREAD_USE_WEAK 0
+
#endif
diff --git a/libstdc++-v3/configure.host b/libstdc++-v3/configure.host
index 441eb4c..37e80ab 100644
--- a/libstdc++-v3/configure.host
+++ b/libstdc++-v3/configure.host
@@ -210,6 +210,9 @@ case "${host_os}" in
freebsd*)
os_include_dir="os/bsd/freebsd"
;;
+ linux-musl*)
+ os_include_dir="os/generic"
+ ;;
gnu* | linux* | kfreebsd*-gnu | knetbsd*-gnu)
if [ "$uclibc" = "yes" ]; then
os_include_dir="os/uclibc"

62
patches/gcc-4.2.1/0002-weakbugs.diff Normal file
View File

@@ -0,0 +1,62 @@
diff --git a/gcc/cgraph.c b/gcc/cgraph.c
index fcdc02e..db04afd 100644
--- a/gcc/cgraph.c
+++ b/gcc/cgraph.c
@@ -1169,7 +1169,7 @@ cgraph_function_body_availability (struct cgraph_node *node)
inline and offline) having same side effect characteristics as
good optimization is what this optimization is about. */
- else if (!(*targetm.binds_local_p) (node->decl)
+ else if ((DECL_WEAK (node->decl) || !(*targetm.binds_local_p) (node->decl))
&& !DECL_COMDAT (node->decl) && !DECL_EXTERNAL (node->decl))
avail = AVAIL_OVERWRITABLE;
else avail = AVAIL_AVAILABLE;
@@ -1190,7 +1190,8 @@ cgraph_variable_initializer_availability (struct cgraph_varpool_node *node)
/* If the variable can be overwritten, return OVERWRITABLE. Takes
care of at least two notable extensions - the COMDAT variables
used to share template instantiations in C++. */
- if (!(*targetm.binds_local_p) (node->decl) && !DECL_COMDAT (node->decl))
+ if ((DECL_WEAK (node->decl) || !(*targetm.binds_local_p) (node->decl))
+ && !DECL_COMDAT (node->decl))
return AVAIL_OVERWRITABLE;
return AVAIL_AVAILABLE;
}
diff --git a/gcc/ipa-inline.c b/gcc/ipa-inline.c
index 84ef830..73d9fcc 100644
--- a/gcc/ipa-inline.c
+++ b/gcc/ipa-inline.c
@@ -300,7 +300,7 @@ cgraph_default_inline_p (struct cgraph_node *n, const char **reason)
if (n->inline_decl)
decl = n->inline_decl;
- if (!DECL_INLINE (decl))
+ if (!DECL_INLINE (decl) || DECL_WEAK (decl))
{
if (reason)
*reason = N_("function not inlinable");
diff --git a/gcc/ipa-pure-const.c b/gcc/ipa-pure-const.c
index fdaff50..1bfd577 100644
--- a/gcc/ipa-pure-const.c
+++ b/gcc/ipa-pure-const.c
@@ -512,7 +512,7 @@ analyze_function (struct cgraph_node *fn)
/* If this function does not return normally or does not bind local,
do not touch this unless it has been marked as const or pure by the
front end. */
- if (TREE_THIS_VOLATILE (decl)
+ if (TREE_THIS_VOLATILE (decl) || DECL_WEAK (decl)
|| !targetm.binds_local_p (decl))
{
l->pure_const_state = IPA_NEITHER;
diff --git a/gcc/tree-inline.c b/gcc/tree-inline.c
index 1c0b79b..5a3ba7e 100644
--- a/gcc/tree-inline.c
+++ b/gcc/tree-inline.c
@@ -1522,6 +1522,8 @@ inlinable_function_p (tree fn)
else if (!DECL_INLINE (fn) && !flag_unit_at_a_time)
inlinable = false;
+ else if (DECL_WEAK (fn))
+ inlinable = false;
else if (inline_forbidden_p (fn))
{
/* See if we should warn about uninlinable functions. Previously,

79
patches/gcc-4.2.1/0003-shbitrot.diff Normal file
View File

@@ -0,0 +1,79 @@
diff --git a/config.sub b/config.sub
index b83660a..b81ad9a 100755
--- a/config.sub
+++ b/config.sub
@@ -277,7 +277,7 @@ case $basic_machine in
| powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \
| pyramid \
| score \
- | sh | sh[1234] | sh[24]a | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
+ | sh | sh[1234] | sh[24]a | sh[23]e | sh[1234]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
| sh64 | sh64le \
| sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \
| sparcv8 | sparcv9 | sparcv9b | sparcv9v \
@@ -358,7 +358,7 @@ case $basic_machine in
| powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \
| pyramid-* \
| romp-* | rs6000-* \
- | sh-* | sh[1234]-* | sh[24]a-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \
+ | sh-* | sh[1234]-* | sh[24]a-* | sh[23]e-* | sh[1234]eb-* | sheb-* | shbe-* \
| shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \
| sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \
| sparclite-* \
@@ -1127,7 +1127,7 @@ case $basic_machine in
we32k)
basic_machine=we32k-att
;;
- sh[1234] | sh[24]a | sh[34]eb | sh[1234]le | sh[23]ele)
+ sh[1234] | sh[24]a | sh[1234]eb | sh[1234]le | sh[23]ele)
basic_machine=sh-unknown
;;
sparc | sparcv8 | sparcv9 | sparcv9b | sparcv9v)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 25136b7..3779369 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -1967,7 +1967,7 @@ score-*-elf)
;;
sh-*-elf* | sh[12346l]*-*-elf* | sh*-*-kaos* | \
sh-*-symbianelf* | sh[12346l]*-*-symbianelf* | \
- sh-*-linux* | sh[346lbe]*-*-linux* | \
+ sh-*-linux* | sh[12346lbe]*-*-linux* | \
sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \
sh64-*-netbsd* | sh64l*-*-netbsd*)
tmake_file="${tmake_file} sh/t-sh sh/t-elf"
@@ -2911,7 +2911,7 @@ case "${target}" in
esac
;;
- sh[123456ble]-*-* | sh-*-*)
+ sh[123456ble]*-*-* | sh-*-*)
supported_defaults="cpu"
case "`echo $with_cpu | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ_ abcdefghijklmnopqrstuvwxyz- | sed s/sh/m/`" in
"" | m1 | m2 | m2e | m3 | m3e | m4 | m4-single | m4-single-only | m4-nofpu )
diff --git a/gcc/configure b/gcc/configure
index a248d39..c12f091 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -14564,7 +14564,7 @@ foo: .long 25
tls_first_minor=14
tls_as_opt="-m64 -Aesame --fatal-warnings"
;;
- sh-*-* | sh[34]-*-*)
+ sh-*-* | sh[123456789lbe]*-*-*)
conftest_s='
.section ".tdata","awT",@progbits
foo: .long 25
diff --git a/gcc/configure.ac b/gcc/configure.ac
index b6c394c..1414f9e 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -2538,7 +2538,7 @@ foo: .long 25
tls_first_minor=14
tls_as_opt="-m64 -Aesame --fatal-warnings"
;;
- sh-*-* | sh[34]-*-*)
+ sh-*-* | sh[123456789lbe]*-*-*)
conftest_s='
.section ".tdata","awT",@progbits
foo: .long 25

28
patches/gcc-4.2.1/0005-staticpie.diff Normal file
View File

@@ -0,0 +1,28 @@
diff --git a/gcc/config/linux.h b/gcc/config/linux.h
index 1967b46..39f8cb4 100644
--- a/gcc/config/linux.h
+++ b/gcc/config/linux.h
@@ -41,8 +41,8 @@ Boston, MA 02110-1301, USA. */
#undef STARTFILE_SPEC
#if defined HAVE_LD_PIE
#define STARTFILE_SPEC \
- "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \
- crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s}"
+ "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:%{static:rcrt1.o%s;:Scrt1.o%s};:crt1.o%s}} \
+ crti.o%s %{shared|pie:crtbeginS.o%s;static:crtbeginT.o%s;:crtbegin.o%s}"
#else
#define STARTFILE_SPEC \
"%{!shared: %{pg|p|profile:gcrt1.o%s;:crt1.o%s}} \
diff --git a/gcc/gcc.c b/gcc/gcc.c
index 0b5ee4b..41d17a5 100644
--- a/gcc/gcc.c
+++ b/gcc/gcc.c
@@ -684,7 +684,7 @@ proper position among the other output files. */
#ifndef LINK_PIE_SPEC
#ifdef HAVE_LD_PIE
-#define LINK_PIE_SPEC "%{pie:-pie} "
+#define LINK_PIE_SPEC "%{pie:-pie %{static:--no-dynamic-linker}} "
#else
#define LINK_PIE_SPEC "%{pie:} "
#endif

39
patches/gcc-4.2.1/0006-defaultpie.diff Normal file
View File

@@ -0,0 +1,39 @@
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 3779369..a6d95ca 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -3101,6 +3101,12 @@ case ${target} in
;;
esac
+case "x${enable_default_pie}" in
+xyes)
+ tm_defines="${tm_defines} ENABLE_DEFAULT_PIE"
+ ;;
+esac
+
t=
all_defaults="abi cpu arch tune schedule float mode fpu divide"
for option in $all_defaults
diff --git a/gcc/gcc.c b/gcc/gcc.c
index 41d17a5..b9bbcb6 100644
--- a/gcc/gcc.c
+++ b/gcc/gcc.c
@@ -846,8 +846,16 @@ static const char *const multilib_defaults_raw[] = MULTILIB_DEFAULTS;
#define GOMP_SELF_SPECS "%{fopenmp: -pthread}"
#endif
+#ifndef PIE_SELF_SPECS
+#ifdef ENABLE_DEFAULT_PIE
+#define PIE_SELF_SPECS "%{shared|pie|r|nostdlib|nopie|no-pie:;:-pie} %{fpic|fPIC|fpie|fPIE|fno-pic|fno-PIC|fno-pie|fno-PIE|D__KERNEL__:;:-fPIE}"
+#else
+#define PIE_SELF_SPECS ""
+#endif
+#endif
+
static const char *const driver_self_specs[] = {
- DRIVER_SELF_SPECS, GOMP_SELF_SPECS
+ DRIVER_SELF_SPECS, GOMP_SELF_SPECS, PIE_SELF_SPECS
};
#ifndef OPTION_DEFAULT_SPECS

13
patches/gcc-4.2.1/0008-crossbug.diff Normal file
View File

@@ -0,0 +1,13 @@
diff --git a/Makefile.in b/Makefile.in
index 218d8fa..45c1764 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -208,7 +208,7 @@ BASE_TARGET_EXPORTS = \
RANLIB="$(RANLIB_FOR_TARGET)"; export RANLIB; \
STRIP="$(STRIP_FOR_TARGET)"; export STRIP; \
WINDRES="$(WINDRES_FOR_TARGET)"; export WINDRES; \
- $(RPATH_ENVVAR)=`echo "$(HOST_LIB_PATH)$(TARGET_LIB_PATH)$$$(RPATH_ENVVAR)" | sed 's,::*,:,g;s,^:*,,;s,:*$$,,'`; export $(RPATH_ENVVAR);
+ $(RPATH_ENVVAR)=`echo "$(HOST_LIB_PATH)$$$(RPATH_ENVVAR)" | sed 's,::*,:,g;s,^:*,,;s,:*$$,,'`; export $(RPATH_ENVVAR);
RAW_CXX_TARGET_EXPORTS = \
$(BASE_TARGET_EXPORTS) \

15
patches/gcc-4.2.1/0009-shdiv.diff Normal file
View File

@@ -0,0 +1,15 @@
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index fc4e1f2..1a4cf00 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -649,10 +649,6 @@ do { \
/* ??? Should we use the integer SHmedia function instead? */ \
else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) \
sh_div_strategy = SH_DIV_CALL_FP; \
- /* SH1 .. SH3 cores often go into small-footprint systems, so \
- default to the smallest implementation available. */ \
- else if (TARGET_SH2) /* ??? EXPERIMENTAL */ \
- sh_div_strategy = SH_DIV_CALL_TABLE; \
else \
sh_div_strategy = SH_DIV_CALL_DIV1; \
} \

53
patches/gcc-4.2.1/0010-gnuinline.diff Normal file
View File

@@ -0,0 +1,53 @@
diff --git a/gcc/toplev.c b/gcc/toplev.c
index 53fcdfe..85f8504 100644
--- a/gcc/toplev.c
+++ b/gcc/toplev.c
@@ -533,6 +533,7 @@ read_integral_parameter (const char *p, const char *pname, const int defval)
#if GCC_VERSION < 3004 || !defined (__cplusplus)
+#if 0
/* Given X, an unsigned number, return the largest int Y such that 2**Y <= X.
If X is 0, return -1. */
@@ -582,6 +583,7 @@ exact_log2 (unsigned HOST_WIDE_INT x)
return floor_log2 (x);
#endif
}
+#endif
#endif /* GCC_VERSION < 3004 || !defined (__cplusplus) */
diff --git a/gcc/toplev.h b/gcc/toplev.h
index c935f7e..c8d4bb2 100644
--- a/gcc/toplev.h
+++ b/gcc/toplev.h
@@ -152,10 +152,10 @@ extern void decode_d_option (const char *);
extern bool fast_math_flags_set_p (void);
/* Return log2, or -1 if not exact. */
-extern int exact_log2 (unsigned HOST_WIDE_INT);
+//extern int exact_log2 (unsigned HOST_WIDE_INT);
/* Return floor of log2, with -1 for zero. */
-extern int floor_log2 (unsigned HOST_WIDE_INT);
+//extern int floor_log2 (unsigned HOST_WIDE_INT);
/* Inline versions of the above for speed. */
#if GCC_VERSION >= 3004
@@ -170,13 +170,13 @@ extern int floor_log2 (unsigned HOST_WIDE_INT);
# define CTZ_HWI __builtin_ctz
# endif
-extern inline int
+static inline int
floor_log2 (unsigned HOST_WIDE_INT x)
{
return x ? HOST_BITS_PER_WIDE_INT - 1 - (int) CLZ_HWI (x) : -1;
}
-extern inline int
+static inline int
exact_log2 (unsigned HOST_WIDE_INT x)
{
return x == (x & -x) && x ? (int) CTZ_HWI (x) : -1;

36
patches/gcc-4.2.1/0011-inhibitlibc.diff Normal file
View File

@@ -0,0 +1,36 @@
diff -ru gcc-core/gcc/config/sh/linux-unwind.h gcc-core/gcc/config/sh/linux-unwind.h
--- gcc-core/gcc/config/sh/linux-unwind.h 2005-06-28 20:45:37.000000000 -0500
+++ gcc-core/gcc/config/sh/linux-unwind.h 2008-02-06 17:41:12.000000000 -0600
@@ -26,6 +26,8 @@
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
+#ifndef inhibit_libc
+
/* Do code reading to identify a signal frame, and set the frame
state data appropriately. See unwind-dw2.c for the structs. */
@@ -249,3 +251,5 @@
return _URC_NO_REASON;
}
#endif /* defined (__SH5__) */
+
+#endif
diff -ru gcc-core/gcc/config/alpha/linux-unwind.h gcc-core2/gcc/config/alpha/linux-unwind.h
--- gcc-core/gcc/config/alpha/linux-unwind.h 2005-06-24 20:22:41.000000000 -0500
+++ gcc-core2/gcc/config/alpha/linux-unwind.h 2010-01-10 20:05:56.000000000 -0600
@@ -26,6 +26,8 @@
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
+#ifndef inhibit_libc
+
/* Do code reading to identify a signal frame, and set the frame
state data appropriately. See unwind-dw2.c for the structs. */
@@ -80,3 +82,5 @@
fs->retaddr_column = 64;
return _URC_NO_REASON;
}
+
+#endif

10
patches/gcc-4.2.1/0012-shletls.diff Normal file
View File

@@ -0,0 +1,10 @@
--- gcc-4.2.1/gcc/config/sh/sh.c.orig 2015-11-06 04:41:52.683021006 +0000
+++ gcc-4.2.1/gcc/config/sh/sh.c 2015-11-06 04:42:00.643020520 +0000
@@ -8343,6 +8343,7 @@ nonpic_symbol_mentioned_p (rtx x)
|| XINT (x, 1) == UNSPEC_GOTPLT
|| XINT (x, 1) == UNSPEC_GOTTPOFF
|| XINT (x, 1) == UNSPEC_DTPOFF
+ || XINT (x, 1) == UNSPEC_TPOFF
|| XINT (x, 1) == UNSPEC_PLT))
return 0;

892
patches/gcc-5.3.0/0001-musl.diff Normal file
View File

@@ -0,0 +1,892 @@
diff --git a/fixincludes/mkfixinc.sh b/fixincludes/mkfixinc.sh
index 6653fed..0d96c8c 100755
--- a/fixincludes/mkfixinc.sh
+++ b/fixincludes/mkfixinc.sh
@@ -19,7 +19,8 @@ case $machine in
powerpc-*-eabi* | \
powerpc-*-rtems* | \
powerpcle-*-eabisim* | \
- powerpcle-*-eabi* )
+ powerpcle-*-eabi* | \
+ *-musl* )
# IF there is no include fixing,
# THEN create a no-op fixer and exit
(echo "#! /bin/sh" ; echo "exit 0" ) > ${target}
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 3ede69b..d9eb8cf 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -575,7 +575,7 @@ case ${target} in
esac
# Common C libraries.
-tm_defines="$tm_defines LIBC_GLIBC=1 LIBC_UCLIBC=2 LIBC_BIONIC=3"
+tm_defines="$tm_defines LIBC_GLIBC=1 LIBC_UCLIBC=2 LIBC_BIONIC=3 LIBC_MUSL=4"
# 32-bit x86 processors supported by --with-arch=. Each processor
# MUST be separated by exactly one space.
@@ -720,6 +720,9 @@ case ${target} in
*-*-*uclibc*)
tm_defines="$tm_defines DEFAULT_LIBC=LIBC_UCLIBC"
;;
+ *-*-*musl*)
+ tm_defines="$tm_defines DEFAULT_LIBC=LIBC_MUSL"
+ ;;
*)
tm_defines="$tm_defines DEFAULT_LIBC=LIBC_GLIBC"
;;
diff --git a/gcc/config/aarch64/aarch64-linux.h b/gcc/config/aarch64/aarch64-linux.h
index ba7fc3b..1600a32 100644
--- a/gcc/config/aarch64/aarch64-linux.h
+++ b/gcc/config/aarch64/aarch64-linux.h
@@ -23,6 +23,9 @@
#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
+#undef MUSL_DYNAMIC_LINKER
+#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
+
#undef ASAN_CC1_SPEC
#define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
diff --git a/gcc/config/alpha/linux.h b/gcc/config/alpha/linux.h
index c567f43..475ea06 100644
--- a/gcc/config/alpha/linux.h
+++ b/gcc/config/alpha/linux.h
@@ -61,10 +61,14 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC)
#define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC)
#define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC)
+#undef OPTION_MUSL
+#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL)
#else
#define OPTION_GLIBC (linux_libc == LIBC_GLIBC)
#define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC)
#define OPTION_BIONIC (linux_libc == LIBC_BIONIC)
+#undef OPTION_MUSL
+#define OPTION_MUSL (linux_libc == LIBC_MUSL)
#endif
/* Determine what functions are present at the runtime;
diff --git a/gcc/config/arm/linux-eabi.h b/gcc/config/arm/linux-eabi.h
index e9d65dc..f12e6bd 100644
--- a/gcc/config/arm/linux-eabi.h
+++ b/gcc/config/arm/linux-eabi.h
@@ -77,6 +77,23 @@
%{mfloat-abi=soft*:" GLIBC_DYNAMIC_LINKER_SOFT_FLOAT "} \
%{!mfloat-abi=*:" GLIBC_DYNAMIC_LINKER_DEFAULT "}"
+/* For ARM musl currently supports four dynamic linkers:
+ - ld-musl-arm.so.1 - for the EABI-derived soft-float ABI
+ - ld-musl-armhf.so.1 - for the EABI-derived hard-float ABI
+ - ld-musl-armeb.so.1 - for the EABI-derived soft-float ABI, EB
+ - ld-musl-armebhf.so.1 - for the EABI-derived hard-float ABI, EB
+ musl does not support the legacy OABI mode.
+ All the dynamic linkers live in /lib.
+ We default to soft-float, EL. */
+#undef MUSL_DYNAMIC_LINKER
+#if TARGET_BIG_ENDIAN_DEFAULT
+#define MUSL_DYNAMIC_LINKER_E "%{mlittle-endian:;:eb}"
+#else
+#define MUSL_DYNAMIC_LINKER_E "%{mbig-endian:eb}"
+#endif
+#define MUSL_DYNAMIC_LINKER \
+ "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}.so.1"
+
/* At this point, bpabi.h will have clobbered LINK_SPEC. We want to
use the GNU/Linux version, not the generic BPABI version. */
#undef LINK_SPEC
diff --git a/gcc/config/glibc-stdint.h b/gcc/config/glibc-stdint.h
index 3fc67dc..98f4f04 100644
--- a/gcc/config/glibc-stdint.h
+++ b/gcc/config/glibc-stdint.h
@@ -22,6 +22,12 @@ a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
+/* Systems using musl libc should use this header and make sure
+ OPTION_MUSL is defined correctly before using the TYPE macros. */
+#ifndef OPTION_MUSL
+#define OPTION_MUSL 0
+#endif
+
#define SIG_ATOMIC_TYPE "int"
#define INT8_TYPE "signed char"
@@ -43,12 +49,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define UINT_LEAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "long long unsigned int")
#define INT_FAST8_TYPE "signed char"
-#define INT_FAST16_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "int")
-#define INT_FAST32_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "int")
+#define INT_FAST16_TYPE (LONG_TYPE_SIZE == 64 && !OPTION_MUSL ? "long int" : "int")
+#define INT_FAST32_TYPE (LONG_TYPE_SIZE == 64 && !OPTION_MUSL ? "long int" : "int")
#define INT_FAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "long long int")
#define UINT_FAST8_TYPE "unsigned char"
-#define UINT_FAST16_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "unsigned int")
-#define UINT_FAST32_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "unsigned int")
+#define UINT_FAST16_TYPE (LONG_TYPE_SIZE == 64 && !OPTION_MUSL ? "long unsigned int" : "unsigned int")
+#define UINT_FAST32_TYPE (LONG_TYPE_SIZE == 64 && !OPTION_MUSL ? "long unsigned int" : "unsigned int")
#define UINT_FAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "long long unsigned int")
#define INTPTR_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "int")
diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h
index a100963..385aefd 100644
--- a/gcc/config/i386/linux.h
+++ b/gcc/config/i386/linux.h
@@ -21,3 +21,6 @@ along with GCC; see the file COPYING3. If not see
#define GNU_USER_LINK_EMULATION "elf_i386"
#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+
+#undef MUSL_DYNAMIC_LINKER
+#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-i386.so.1"
diff --git a/gcc/config/i386/linux64.h b/gcc/config/i386/linux64.h
index a27d3be..e300480 100644
--- a/gcc/config/i386/linux64.h
+++ b/gcc/config/i386/linux64.h
@@ -30,3 +30,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2"
+
+#undef MUSL_DYNAMIC_LINKER32
+#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-i386.so.1"
+#undef MUSL_DYNAMIC_LINKER64
+#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-x86_64.so.1"
+#undef MUSL_DYNAMIC_LINKERX32
+#define MUSL_DYNAMIC_LINKERX32 "/lib/ld-musl-x32.so.1"
diff --git a/gcc/config/linux.h b/gcc/config/linux.h
index 857389a..7bc87ab 100644
--- a/gcc/config/linux.h
+++ b/gcc/config/linux.h
@@ -32,10 +32,14 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC)
#define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC)
#define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC)
+#undef OPTION_MUSL
+#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL)
#else
#define OPTION_GLIBC (linux_libc == LIBC_GLIBC)
#define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC)
#define OPTION_BIONIC (linux_libc == LIBC_BIONIC)
+#undef OPTION_MUSL
+#define OPTION_MUSL (linux_libc == LIBC_MUSL)
#endif
#define GNU_USER_TARGET_OS_CPP_BUILTINS() \
@@ -50,21 +54,25 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
} while (0)
/* Determine which dynamic linker to use depending on whether GLIBC or
- uClibc or Bionic is the default C library and whether
- -muclibc or -mglibc or -mbionic has been passed to change the default. */
+ uClibc or Bionic or musl is the default C library and whether
+ -muclibc or -mglibc or -mbionic or -mmusl has been passed to change
+ the default. */
-#define CHOOSE_DYNAMIC_LINKER1(LIBC1, LIBC2, LIBC3, LD1, LD2, LD3) \
- "%{" LIBC2 ":" LD2 ";:%{" LIBC3 ":" LD3 ";:" LD1 "}}"
+#define CHOOSE_DYNAMIC_LINKER1(LIBC1, LIBC2, LIBC3, LIBC4, LD1, LD2, LD3, LD4) \
+ "%{" LIBC2 ":" LD2 ";:%{" LIBC3 ":" LD3 ";:%{" LIBC4 ":" LD4 ";:" LD1 "}}}"
#if DEFAULT_LIBC == LIBC_GLIBC
-#define CHOOSE_DYNAMIC_LINKER(G, U, B) \
- CHOOSE_DYNAMIC_LINKER1 ("mglibc", "muclibc", "mbionic", G, U, B)
+#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \
+ CHOOSE_DYNAMIC_LINKER1 ("mglibc", "muclibc", "mbionic", "mmusl", G, U, B, M)
#elif DEFAULT_LIBC == LIBC_UCLIBC
-#define CHOOSE_DYNAMIC_LINKER(G, U, B) \
- CHOOSE_DYNAMIC_LINKER1 ("muclibc", "mglibc", "mbionic", U, G, B)
+#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \
+ CHOOSE_DYNAMIC_LINKER1 ("muclibc", "mglibc", "mbionic", "mmusl", U, G, B, M)
#elif DEFAULT_LIBC == LIBC_BIONIC
-#define CHOOSE_DYNAMIC_LINKER(G, U, B) \
- CHOOSE_DYNAMIC_LINKER1 ("mbionic", "mglibc", "muclibc", B, G, U)
+#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \
+ CHOOSE_DYNAMIC_LINKER1 ("mbionic", "mglibc", "muclibc", "mmusl", B, G, U, M)
+#elif DEFAULT_LIBC == LIBC_MUSL
+#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \
+ CHOOSE_DYNAMIC_LINKER1 ("mmusl", "mglibc", "muclibc", "mbionic", M, G, U, B)
#else
#error "Unsupported DEFAULT_LIBC"
#endif /* DEFAULT_LIBC */
@@ -81,24 +89,100 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
#define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
#define BIONIC_DYNAMIC_LINKERX32 "/system/bin/linkerx32"
+/* Should be redefined for each target that supports musl. */
+#define MUSL_DYNAMIC_LINKER "/dev/null"
+#define MUSL_DYNAMIC_LINKER32 "/dev/null"
+#define MUSL_DYNAMIC_LINKER64 "/dev/null"
+#define MUSL_DYNAMIC_LINKERX32 "/dev/null"
#define GNU_USER_DYNAMIC_LINKER \
CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER, \
- BIONIC_DYNAMIC_LINKER)
+ BIONIC_DYNAMIC_LINKER, MUSL_DYNAMIC_LINKER)
#define GNU_USER_DYNAMIC_LINKER32 \
CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32, \
- BIONIC_DYNAMIC_LINKER32)
+ BIONIC_DYNAMIC_LINKER32, MUSL_DYNAMIC_LINKER32)
#define GNU_USER_DYNAMIC_LINKER64 \
CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64, \
- BIONIC_DYNAMIC_LINKER64)
+ BIONIC_DYNAMIC_LINKER64, MUSL_DYNAMIC_LINKER64)
#define GNU_USER_DYNAMIC_LINKERX32 \
CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKERX32, UCLIBC_DYNAMIC_LINKERX32, \
- BIONIC_DYNAMIC_LINKERX32)
+ BIONIC_DYNAMIC_LINKERX32, MUSL_DYNAMIC_LINKERX32)
/* Whether we have Bionic libc runtime */
#undef TARGET_HAS_BIONIC
#define TARGET_HAS_BIONIC (OPTION_BIONIC)
+/* musl avoids problematic includes by rearranging the include directories.
+ * Unfortunately, this is mostly duplicated from cppdefault.c */
+#if DEFAULT_LIBC == LIBC_MUSL
+#define INCLUDE_DEFAULTS_MUSL_GPP \
+ { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, \
+ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, \
+ { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, \
+ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 }, \
+ { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, \
+ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 },
+
+#ifdef LOCAL_INCLUDE_DIR
+#define INCLUDE_DEFAULTS_MUSL_LOCAL \
+ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, \
+ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 },
+#else
+#define INCLUDE_DEFAULTS_MUSL_LOCAL
+#endif
+
+#ifdef PREFIX_INCLUDE_DIR
+#define INCLUDE_DEFAULTS_MUSL_PREFIX \
+ { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0},
+#else
+#define INCLUDE_DEFAULTS_MUSL_PREFIX
+#endif
+
+#ifdef CROSS_INCLUDE_DIR
+#define INCLUDE_DEFAULTS_MUSL_CROSS \
+ { CROSS_INCLUDE_DIR, "GCC", 0, 0, 0, 0},
+#else
+#define INCLUDE_DEFAULTS_MUSL_CROSS
+#endif
+
+#ifdef TOOL_INCLUDE_DIR
+#define INCLUDE_DEFAULTS_MUSL_TOOL \
+ { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1, 0, 0},
+#else
+#define INCLUDE_DEFAULTS_MUSL_TOOL
+#endif
+
+#ifdef NATIVE_SYSTEM_HEADER_DIR
+#define INCLUDE_DEFAULTS_MUSL_NATIVE \
+ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 }, \
+ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 0 },
+#else
+#define INCLUDE_DEFAULTS_MUSL_NATIVE
+#endif
+
+#if defined (CROSS_DIRECTORY_STRUCTURE) && !defined (TARGET_SYSTEM_ROOT)
+# undef INCLUDE_DEFAULTS_MUSL_LOCAL
+# define INCLUDE_DEFAULTS_MUSL_LOCAL
+# undef INCLUDE_DEFAULTS_MUSL_NATIVE
+# define INCLUDE_DEFAULTS_MUSL_NATIVE
+#else
+# undef INCLUDE_DEFAULTS_MUSL_CROSS
+# define INCLUDE_DEFAULTS_MUSL_CROSS
+#endif
+
+#undef INCLUDE_DEFAULTS
+#define INCLUDE_DEFAULTS \
+ { \
+ INCLUDE_DEFAULTS_MUSL_GPP \
+ INCLUDE_DEFAULTS_MUSL_PREFIX \
+ INCLUDE_DEFAULTS_MUSL_CROSS \
+ INCLUDE_DEFAULTS_MUSL_TOOL \
+ INCLUDE_DEFAULTS_MUSL_NATIVE \
+ { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 }, \
+ { 0, 0, 0, 0, 0, 0 } \
+ }
+#endif
+
#if (DEFAULT_LIBC == LIBC_UCLIBC) && defined (SINGLE_LIBC) /* uClinux */
/* This is a *uclinux* target. We don't define below macros to normal linux
versions, because doing so would require *uclinux* targets to include
diff --git a/gcc/config/linux.opt b/gcc/config/linux.opt
index c054338..ef055a7 100644
--- a/gcc/config/linux.opt
+++ b/gcc/config/linux.opt
@@ -28,5 +28,9 @@ Target Report RejectNegative Var(linux_libc,LIBC_GLIBC) Negative(muclibc)
Use GNU C library
muclibc
-Target Report RejectNegative Var(linux_libc,LIBC_UCLIBC) Negative(mbionic)
+Target Report RejectNegative Var(linux_libc,LIBC_UCLIBC) Negative(mmusl)
Use uClibc C library
+
+mmusl
+Target Report RejectNegative Var(linux_libc,LIBC_MUSL) Negative(mbionic)
+Use musl C library
diff --git a/gcc/config/microblaze/linux.h b/gcc/config/microblaze/linux.h
index 655a70f..a8a3f3e 100644
--- a/gcc/config/microblaze/linux.h
+++ b/gcc/config/microblaze/linux.h
@@ -28,10 +28,20 @@
#undef TLS_NEEDS_GOT
#define TLS_NEEDS_GOT 1
-#define DYNAMIC_LINKER "/lib/ld.so.1"
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+
+#if TARGET_BIG_ENDIAN_DEFAULT == 0 /* LE */
+#define MUSL_DYNAMIC_LINKER_E "%{mbig-endian:;:el}"
+#else
+#define MUSL_DYNAMIC_LINKER_E "%{mlittle-endian:el}"
+#endif
+
+#undef MUSL_DYNAMIC_LINKER
+#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-microblaze" MUSL_DYNAMIC_LINKER_E ".so.1"
+
#undef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS \
- { "dynamic_linker", DYNAMIC_LINKER }
+ { "dynamic_linker", GNU_USER_DYNAMIC_LINKER }
#undef LINK_SPEC
#define LINK_SPEC "%{shared:-shared} \
diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h
index 91df261..fb358e2 100644
--- a/gcc/config/mips/linux.h
+++ b/gcc/config/mips/linux.h
@@ -37,7 +37,13 @@ along with GCC; see the file COPYING3. If not see
#define UCLIBC_DYNAMIC_LINKERN32 \
"%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}"
+#undef MUSL_DYNAMIC_LINKER32
+#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-mips%{EL:el}%{msoft-float:-sf}.so.1"
+#undef MUSL_DYNAMIC_LINKER64
+#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-mips64%{EL:el}%{msoft-float:-sf}.so.1"
+#define MUSL_DYNAMIC_LINKERN32 "/lib/ld-musl-mipsn32%{EL:el}%{msoft-float:-sf}.so.1"
+
#define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
#define GNU_USER_DYNAMIC_LINKERN32 \
CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKERN32, UCLIBC_DYNAMIC_LINKERN32, \
- BIONIC_DYNAMIC_LINKERN32)
+ BIONIC_DYNAMIC_LINKERN32, MUSL_DYNAMIC_LINKERN32)
diff --git a/gcc/config/rs6000/linux.h b/gcc/config/rs6000/linux.h
index fe0ebd6..a68ff69 100644
--- a/gcc/config/rs6000/linux.h
+++ b/gcc/config/rs6000/linux.h
@@ -30,10 +30,14 @@
#define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC)
#define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC)
#define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC)
+#undef OPTION_MUSL
+#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL)
#else
#define OPTION_GLIBC (linux_libc == LIBC_GLIBC)
#define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC)
#define OPTION_BIONIC (linux_libc == LIBC_BIONIC)
+#undef OPTION_MUSL
+#define OPTION_MUSL (linux_libc == LIBC_MUSL)
#endif
/* Determine what functions are present at the runtime;
diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h
index 0879e7e..6a7d435 100644
--- a/gcc/config/rs6000/linux64.h
+++ b/gcc/config/rs6000/linux64.h
@@ -299,10 +299,14 @@ extern int dot_symbols;
#define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC)
#define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC)
#define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC)
+#undef OPTION_MUSL
+#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL)
#else
#define OPTION_GLIBC (linux_libc == LIBC_GLIBC)
#define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC)
#define OPTION_BIONIC (linux_libc == LIBC_BIONIC)
+#undef OPTION_MUSL
+#define OPTION_MUSL (linux_libc == LIBC_MUSL)
#endif
/* Determine what functions are present at the runtime;
@@ -365,17 +369,23 @@ extern int dot_symbols;
#endif
#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
+#define MUSL_DYNAMIC_LINKER32 \
+ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"
+#define MUSL_DYNAMIC_LINKER64 \
+ "/lib/ld-musl-powerpc64" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"
#if DEFAULT_LIBC == LIBC_UCLIBC
-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
+#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";:%{mmusl:" M ";:" U "}}"
#elif DEFAULT_LIBC == LIBC_GLIBC
-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:" U ";:" G "}"
+#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{muclibc:" U ";:%{mmusl:" M ";:" G "}}"
+#elif DEFAULT_LIBC == LIBC_MUSL
+#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";:%{muclibc:" U ";:" M "}}"
#else
#error "Unsupported DEFAULT_LIBC"
#endif
#define GNU_USER_DYNAMIC_LINKER32 \
- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32)
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32, MUSL_DYNAMIC_LINKER32)
#define GNU_USER_DYNAMIC_LINKER64 \
- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64)
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64, MUSL_DYNAMIC_LINKER64)
#undef DEFAULT_ASM_ENDIAN
#if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
diff --git a/gcc/config/rs6000/secureplt.h b/gcc/config/rs6000/secureplt.h
index b463463..77edf2a 100644
--- a/gcc/config/rs6000/secureplt.h
+++ b/gcc/config/rs6000/secureplt.h
@@ -18,3 +18,4 @@ along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define CC1_SECURE_PLT_DEFAULT_SPEC "-msecure-plt"
+#define LINK_SECURE_PLT_DEFAULT_SPEC "--secure-plt"
diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
index 9917c2f..68365de 100644
--- a/gcc/config/rs6000/sysv4.h
+++ b/gcc/config/rs6000/sysv4.h
@@ -537,6 +537,9 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN)
#ifndef CC1_SECURE_PLT_DEFAULT_SPEC
#define CC1_SECURE_PLT_DEFAULT_SPEC ""
#endif
+#ifndef LINK_SECURE_PLT_DEFAULT_SPEC
+#define LINK_SECURE_PLT_DEFAULT_SPEC ""
+#endif
/* Pass -G xxx to the compiler. */
#undef CC1_SPEC
@@ -574,7 +577,8 @@
%{R*} \
%(link_shlib) \
%{!T*: %(link_start) } \
-%(link_os)"
+%(link_os) \
+%{!mbss-plt: %{!msecure-plt: %(link_secure_plt_default)}}"
/* Shared libraries are not default. */
#define LINK_SHLIB_SPEC "\
@@ -762,17 +766,23 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN)
#define LINK_START_LINUX_SPEC ""
+#define MUSL_DYNAMIC_LINKER_E ENDIAN_SELECT("","le","")
+
#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
+#define MUSL_DYNAMIC_LINKER \
+ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"
#if DEFAULT_LIBC == LIBC_UCLIBC
-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
+#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";:%{mmusl:" M ";:" U "}}"
+#elif DEFAULT_LIBC == LIBC_MUSL
+#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";:%{muclibc:" U ";:" M "}}"
#elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC
-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:" U ";:" G "}"
+#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{muclibc:" U ";:%{mmusl:" M ";:" G "}}"
#else
#error "Unsupported DEFAULT_LIBC"
#endif
#define GNU_USER_DYNAMIC_LINKER \
- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER)
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER, MUSL_DYNAMIC_LINKER)
#define LINK_OS_LINUX_SPEC "-m elf32ppclinux %{!shared: %{!static: \
%{rdynamic:-export-dynamic} \
@@ -895,6 +905,7 @@ ncrtn.o%s"
{ "link_os_openbsd", LINK_OS_OPENBSD_SPEC }, \
{ "link_os_default", LINK_OS_DEFAULT_SPEC }, \
{ "cc1_secure_plt_default", CC1_SECURE_PLT_DEFAULT_SPEC }, \
+ { "link_secure_plt_default", LINK_SECURE_PLT_DEFAULT_SPEC }, \
{ "cpp_os_ads", CPP_OS_ADS_SPEC }, \
{ "cpp_os_yellowknife", CPP_OS_YELLOWKNIFE_SPEC }, \
{ "cpp_os_mvme", CPP_OS_MVME_SPEC }, \
@@ -949,3 +960,72 @@ ncrtn.o%s"
/* This target uses the sysv4.opt file. */
#define TARGET_USES_SYSV4_OPT 1
+/* Include order changes for musl, same as in generic linux.h. */
+#if DEFAULT_LIBC == LIBC_MUSL
+#define INCLUDE_DEFAULTS_MUSL_GPP \
+ { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, \
+ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, \
+ { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, \
+ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 }, \
+ { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, \
+ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 },
+
+#ifdef LOCAL_INCLUDE_DIR
+#define INCLUDE_DEFAULTS_MUSL_LOCAL \
+ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, \
+ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 },
+#else
+#define INCLUDE_DEFAULTS_MUSL_LOCAL
+#endif
+
+#ifdef PREFIX_INCLUDE_DIR
+#define INCLUDE_DEFAULTS_MUSL_PREFIX \
+ { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0},
+#else
+#define INCLUDE_DEFAULTS_MUSL_PREFIX
+#endif
+
+#ifdef CROSS_INCLUDE_DIR
+#define INCLUDE_DEFAULTS_MUSL_CROSS \
+ { CROSS_INCLUDE_DIR, "GCC", 0, 0, 0, 0},
+#else
+#define INCLUDE_DEFAULTS_MUSL_CROSS
+#endif
+
+#ifdef TOOL_INCLUDE_DIR
+#define INCLUDE_DEFAULTS_MUSL_TOOL \
+ { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1, 0, 0},
+#else
+#define INCLUDE_DEFAULTS_MUSL_TOOL
+#endif
+
+#ifdef NATIVE_SYSTEM_HEADER_DIR
+#define INCLUDE_DEFAULTS_MUSL_NATIVE \
+ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 }, \
+ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 0 },
+#else
+#define INCLUDE_DEFAULTS_MUSL_NATIVE
+#endif
+
+#if defined (CROSS_DIRECTORY_STRUCTURE) && !defined (TARGET_SYSTEM_ROOT)
+# undef INCLUDE_DEFAULTS_MUSL_LOCAL
+# define INCLUDE_DEFAULTS_MUSL_LOCAL
+# undef INCLUDE_DEFAULTS_MUSL_NATIVE
+# define INCLUDE_DEFAULTS_MUSL_NATIVE
+#else
+# undef INCLUDE_DEFAULTS_MUSL_CROSS
+# define INCLUDE_DEFAULTS_MUSL_CROSS
+#endif
+
+#undef INCLUDE_DEFAULTS
+#define INCLUDE_DEFAULTS \
+ { \
+ INCLUDE_DEFAULTS_MUSL_GPP \
+ INCLUDE_DEFAULTS_MUSL_PREFIX \
+ INCLUDE_DEFAULTS_MUSL_CROSS \
+ INCLUDE_DEFAULTS_MUSL_TOOL \
+ INCLUDE_DEFAULTS_MUSL_NATIVE \
+ { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 }, \
+ { 0, 0, 0, 0, 0, 0 } \
+ }
+#endif
diff --git a/gcc/config/rs6000/sysv4le.h b/gcc/config/rs6000/sysv4le.h
index 7b1d6a1..064323c 100644
--- a/gcc/config/rs6000/sysv4le.h
+++ b/gcc/config/rs6000/sysv4le.h
@@ -35,3 +35,5 @@
/* Little-endian PowerPC64 Linux uses the ELF v2 ABI by default. */
#define LINUX64_DEFAULT_ABI_ELFv2
+#undef MUSL_DYNAMIC_LINKER_E
+#define MUSL_DYNAMIC_LINKER_E ENDIAN_SELECT("","le","le")
diff --git a/gcc/config/sh/linux.h b/gcc/config/sh/linux.h
index 0f5d614..4c167c6 100644
--- a/gcc/config/sh/linux.h
+++ b/gcc/config/sh/linux.h
@@ -43,6 +43,29 @@ along with GCC; see the file COPYING3. If not see
#define TARGET_ASM_FILE_END file_end_indicate_exec_stack
+#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
+#define MUSL_DYNAMIC_LINKER_E "%{mb:eb}"
+#else
+#define MUSL_DYNAMIC_LINKER_E "%{!ml:eb}"
+#endif
+
+#if TARGET_CPU_DEFAULT & ( MASK_HARD_SH2A_DOUBLE | MASK_SH4 )
+/* "-nofpu" if any nofpu option is specified */
+#define MUSL_DYNAMIC_LINKER_FP \
+ "%{m1|m2|m2a-nofpu|m3|m4-nofpu|m4-100-nofpu|m4-200-nofpu|m4-300-nofpu|" \
+ "m4-340|m4-400|m4-500|m4al|m5-32media-nofpu|m5-64media-nofpu|" \
+ "m5-compact-nofpu:-nofpu}"
+#else
+/* "-nofpu" if none of the hard fpu options are specified */
+#define MUSL_DYNAMIC_LINKER_FP \
+ "%{m2a|m4|m4-100|m4-200|m4-300|m4a|m5-32media|m5-64media|m5-compact:;:-nofpu}"
+#endif
+
+#undef MUSL_DYNAMIC_LINKER
+#define MUSL_DYNAMIC_LINKER \
+ "/lib/ld-musl-sh" MUSL_DYNAMIC_LINKER_E MUSL_DYNAMIC_LINKER_FP \
+ "%{mfdpic:-fdpic}.so.1"
+
#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
#undef SUBTARGET_LINK_EMUL_SUFFIX
diff --git a/gcc/configure b/gcc/configure
index 0037240..66aab9f 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -27742,6 +27742,9 @@ if test "${gcc_cv_libc_provides_ssp+set}" = set; then :
else
gcc_cv_libc_provides_ssp=no
case "$target" in
+ *-*-musl*)
+ # All versions of musl provide stack protector
+ gcc_cv_libc_provides_ssp=yes;;
*-*-linux* | *-*-kfreebsd*-gnu | *-*-knetbsd*-gnu)
# glibc 2.4 and later provides __stack_chk_fail and
# either __stack_chk_guard, or TLS access to stack guard canary.
@@ -27774,6 +27777,7 @@ fi
# <http://gcc.gnu.org/ml/gcc/2008-10/msg00130.html>) and for now
# simply assert that glibc does provide this, which is true for all
# realistically usable GNU/Hurd configurations.
+ # All supported versions of musl provide it as well
gcc_cv_libc_provides_ssp=yes;;
*-*-darwin* | *-*-freebsd*)
ac_fn_c_check_func "$LINENO" "__stack_chk_fail" "ac_cv_func___stack_chk_fail"
@@ -27870,6 +27874,9 @@ case "$target" in
gcc_cv_target_dl_iterate_phdr=no
fi
;;
+ *-linux-musl*)
+ gcc_cv_target_dl_iterate_phdr=yes
+ ;;
esac
if test x$gcc_cv_target_dl_iterate_phdr = xyes; then
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 6f38ba1..b81960c 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -5229,6 +5229,9 @@ AC_CACHE_CHECK(__stack_chk_fail in target C library,
gcc_cv_libc_provides_ssp,
[gcc_cv_libc_provides_ssp=no
case "$target" in
+ *-*-musl*)
+ # All versions of musl provide stack protector
+ gcc_cv_libc_provides_ssp=yes;;
*-*-linux* | *-*-kfreebsd*-gnu | *-*-knetbsd*-gnu)
# glibc 2.4 and later provides __stack_chk_fail and
# either __stack_chk_guard, or TLS access to stack guard canary.
@@ -5255,6 +5258,7 @@ AC_CACHE_CHECK(__stack_chk_fail in target C library,
# <http://gcc.gnu.org/ml/gcc/2008-10/msg00130.html>) and for now
# simply assert that glibc does provide this, which is true for all
# realistically usable GNU/Hurd configurations.
+ # All supported versions of musl provide it as well
gcc_cv_libc_provides_ssp=yes;;
*-*-darwin* | *-*-freebsd*)
AC_CHECK_FUNC(__stack_chk_fail,[gcc_cv_libc_provides_ssp=yes],
@@ -5328,6 +5332,9 @@ case "$target" in
gcc_cv_target_dl_iterate_phdr=no
fi
;;
+ *-linux-musl*)
+ gcc_cv_target_dl_iterate_phdr=yes
+ ;;
esac
GCC_TARGET_TEMPLATE([TARGET_DL_ITERATE_PHDR])
if test x$gcc_cv_target_dl_iterate_phdr = xyes; then
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index f84a199..ee9765b 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -667,7 +667,7 @@ Objective-C and Objective-C++ Dialects}.
-mcpu=@var{cpu}}
@emph{GNU/Linux Options}
-@gccoptlist{-mglibc -muclibc -mbionic -mandroid @gol
+@gccoptlist{-mglibc -muclibc -mmusl -mbionic -mandroid @gol
-tno-android-cc -tno-android-ld}
@emph{H8/300 Options}
@@ -15324,13 +15324,19 @@ These @samp{-m} options are defined for GNU/Linux targets:
@item -mglibc
@opindex mglibc
Use the GNU C library. This is the default except
-on @samp{*-*-linux-*uclibc*} and @samp{*-*-linux-*android*} targets.
+on @samp{*-*-linux-*uclibc*}, @samp{*-*-linux-*musl*} and
+@samp{*-*-linux-*android*} targets.
@item -muclibc
@opindex muclibc
Use uClibc C library. This is the default on
@samp{*-*-linux-*uclibc*} targets.
+@item -mmusl
+@opindex mmusl
+Use the musl C library. This is the default on
+@samp{*-*-linux-*musl*} targets.
+
@item -mbionic
@opindex mbionic
Use Bionic C library. This is the default on
diff --git a/libcilkrts/runtime/os-unix.c b/libcilkrts/runtime/os-unix.c
index cb582dd..e43d7d5 100644
--- a/libcilkrts/runtime/os-unix.c
+++ b/libcilkrts/runtime/os-unix.c
@@ -51,6 +51,7 @@
#if defined __linux__
# include <sys/sysinfo.h>
# include <sys/syscall.h>
+# include <sched.h>
#elif defined __APPLE__
# include <sys/sysctl.h>
// Uses sysconf(_SC_NPROCESSORS_ONLN) in verbose output
@@ -400,28 +401,19 @@ COMMON_SYSDEP void __cilkrts_sleep(void)
COMMON_SYSDEP void __cilkrts_yield(void)
{
-#if __APPLE__ || __FreeBSD__ || __VXWORKS__
- // On MacOS, call sched_yield to yield quantum. I'm not sure why we
- // don't do this on Linux also.
- sched_yield();
-#elif defined(__DragonFly__)
- // On DragonFly BSD, call sched_yield to yield quantum.
- sched_yield();
-#elif defined(__MIC__)
+#if defined(__MIC__)
// On MIC, pthread_yield() really trashes things. Arch's measurements
// showed that calling _mm_delay_32() (or doing nothing) was a better
// option. Delaying 1024 clock cycles is a reasonable compromise between
// giving up the processor and latency starting up when work becomes
// available
_mm_delay_32(1024);
-#elif defined(__ANDROID__) || (defined(__sun__) && defined(__svr4__))
- // On Android and Solaris, call sched_yield to yield quantum. I'm not
- // sure why we don't do this on Linux also.
- sched_yield();
-#else
- // On Linux, call pthread_yield (which in turn will call sched_yield)
- // to yield quantum.
+#elif defined(__sun__) && !defined(__svr4__)
+ // On old SunOS call pthread_yield to yield a quantum.
pthread_yield();
+#else
+ // On other platforms call sched_yield to yield a quantum.
+ sched_yield();
#endif
}
diff --git a/libgcc/unwind-dw2-fde-dip.c b/libgcc/unwind-dw2-fde-dip.c
index e1e566b..137dced 100644
--- a/libgcc/unwind-dw2-fde-dip.c
+++ b/libgcc/unwind-dw2-fde-dip.c
@@ -59,6 +59,12 @@
#if !defined(inhibit_libc) && defined(HAVE_LD_EH_FRAME_HDR) \
&& defined(TARGET_DL_ITERATE_PHDR) \
+ && defined(__linux__)
+# define USE_PT_GNU_EH_FRAME
+#endif
+
+#if !defined(inhibit_libc) && defined(HAVE_LD_EH_FRAME_HDR) \
+ && defined(TARGET_DL_ITERATE_PHDR) \
&& (defined(__DragonFly__) || defined(__FreeBSD__))
# define ElfW __ElfN
# define USE_PT_GNU_EH_FRAME
diff --git a/libgfortran/acinclude.m4 b/libgfortran/acinclude.m4
index ba890f9..30b8b1a6 100644
--- a/libgfortran/acinclude.m4
+++ b/libgfortran/acinclude.m4
@@ -100,7 +100,7 @@ void foo (void);
[Define to 1 if the target supports #pragma weak])
fi
case "$host" in
- *-*-darwin* | *-*-hpux* | *-*-cygwin* | *-*-mingw* )
+ *-*-darwin* | *-*-hpux* | *-*-cygwin* | *-*-mingw* | *-*-musl* )
AC_DEFINE(GTHREAD_USE_WEAK, 0,
[Define to 0 if the target shouldn't use #pragma weak])
;;
diff --git a/libgfortran/configure b/libgfortran/configure
index e1592f7..07542e1 100755
--- a/libgfortran/configure
+++ b/libgfortran/configure
@@ -26447,7 +26447,7 @@ $as_echo "#define SUPPORTS_WEAK 1" >>confdefs.h
fi
case "$host" in
- *-*-darwin* | *-*-hpux* | *-*-cygwin* | *-*-mingw* )
+ *-*-darwin* | *-*-hpux* | *-*-cygwin* | *-*-mingw* | *-*-musl* )
$as_echo "#define GTHREAD_USE_WEAK 0" >>confdefs.h
diff --git a/libitm/config/arm/hwcap.cc b/libitm/config/arm/hwcap.cc
index a1c2cfd..ea8f023 100644
--- a/libitm/config/arm/hwcap.cc
+++ b/libitm/config/arm/hwcap.cc
@@ -40,7 +40,7 @@ int GTM_hwcap HIDDEN = 0
#ifdef __linux__
#include <unistd.h>
-#include <sys/fcntl.h>
+#include <fcntl.h>
#include <elf.h>
static void __attribute__((constructor))
diff --git a/libitm/config/linux/x86/tls.h b/libitm/config/linux/x86/tls.h
index e731ab7..54ad8b6 100644
--- a/libitm/config/linux/x86/tls.h
+++ b/libitm/config/linux/x86/tls.h
@@ -25,16 +25,19 @@
#ifndef LIBITM_X86_TLS_H
#define LIBITM_X86_TLS_H 1
-#if defined(__GLIBC_PREREQ) && __GLIBC_PREREQ(2, 10)
+#if defined(__GLIBC_PREREQ)
+#if __GLIBC_PREREQ(2, 10)
/* Use slots in the TCB head rather than __thread lookups.
GLIBC has reserved words 10 through 13 for TM. */
#define HAVE_ARCH_GTM_THREAD 1
#define HAVE_ARCH_GTM_THREAD_DISP 1
#endif
+#endif
#include "config/generic/tls.h"
-#if defined(__GLIBC_PREREQ) && __GLIBC_PREREQ(2, 10)
+#if defined(__GLIBC_PREREQ)
+#if __GLIBC_PREREQ(2, 10)
namespace GTM HIDDEN {
#ifdef __x86_64__
@@ -101,5 +104,6 @@ static inline void set_abi_disp(struct abi_dispatch *x)
} // namespace GTM
#endif /* >= GLIBC 2.10 */
+#endif
#endif // LIBITM_X86_TLS_H
diff --git a/libstdc++-v3/config/os/generic/os_defines.h b/libstdc++-v3/config/os/generic/os_defines.h
index 45bf52a..103ec0e 100644
--- a/libstdc++-v3/config/os/generic/os_defines.h
+++ b/libstdc++-v3/config/os/generic/os_defines.h
@@ -33,4 +33,9 @@
// System-specific #define, typedefs, corrections, etc, go here. This
// file will come before all others.
+// Disable the weak reference logic in gthr.h for os/generic because it
+// is broken on every platform unless there is implementation specific
+// workaround in gthr-posix.h and at link-time for static linking.
+#define _GLIBCXX_GTHREAD_USE_WEAK 0
+
#endif
diff --git a/libstdc++-v3/configure.host b/libstdc++-v3/configure.host
index 640199c..106134e 100644
--- a/libstdc++-v3/configure.host
+++ b/libstdc++-v3/configure.host
@@ -273,6 +273,9 @@ case "${host_os}" in
freebsd*)
os_include_dir="os/bsd/freebsd"
;;
+ linux-musl*)
+ os_include_dir="os/generic"
+ ;;
gnu* | linux* | kfreebsd*-gnu | knetbsd*-gnu)
if [ "$uclibc" = "yes" ]; then
os_include_dir="os/uclibc"

138
patches/gcc-5.3.0/0002-pr66609.diff Normal file
View File

@@ -0,0 +1,138 @@
--- a/gcc/config/sh/sh-protos.h
+++ a/gcc/config/sh/sh-protos.h
@@ -159,6 +159,7 @@ extern int sh_eval_treg_value (rtx op);
extern HOST_WIDE_INT sh_disp_addr_displacement (rtx mem_op);
extern int sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a);
extern bool sh_movsf_ie_ra_split_p (rtx, rtx, rtx);
+extern void sh_expand_sym_label2reg (rtx, rtx, rtx, bool);
/* Result value of sh_find_set_of_reg. */
struct set_of_reg
--- a/gcc/config/sh/sh.c
+++ a/gcc/config/sh/sh.c
@@ -1604,6 +1604,10 @@ sh_asm_output_addr_const_extra (FILE *file, rtx x)
output_addr_const (file, XVECEXP (x, 0, 0));
fputs ("@GOTPLT", file);
break;
+ case UNSPEC_PCREL:
+ output_addr_const (file, XVECEXP (x, 0, 0));
+ fputs ("@PCREL", file);
+ break;
case UNSPEC_DTPOFF:
output_addr_const (file, XVECEXP (x, 0, 0));
fputs ("@DTPOFF", file);
@@ -10441,6 +10445,7 @@ nonpic_symbol_mentioned_p (rtx x)
|| XINT (x, 1) == UNSPEC_DTPOFF
|| XINT (x, 1) == UNSPEC_TPOFF
|| XINT (x, 1) == UNSPEC_PLT
+ || XINT (x, 1) == UNSPEC_PCREL
|| XINT (x, 1) == UNSPEC_SYMOFF
|| XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
return false;
@@ -10714,7 +10719,8 @@ sh_delegitimize_address (rtx orig_x)
rtx symplt = XEXP (XVECEXP (y, 0, 0), 0);
if (GET_CODE (symplt) == UNSPEC
- && XINT (symplt, 1) == UNSPEC_PLT)
+ && (XINT (symplt, 1) == UNSPEC_PLT
+ || XINT (symplt, 1) == UNSPEC_PCREL))
return XVECEXP (symplt, 0, 0);
}
}
@@ -11702,9 +11708,24 @@ sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
|| crtl->args.info.stack_regs == 0)
&& ! sh_cfun_interrupt_handler_p ()
&& (! flag_pic
- || (decl && ! TREE_PUBLIC (decl))
+ || (decl && ! (TREE_PUBLIC (decl) || DECL_WEAK (decl)))
|| (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
}
+
+/* Expand to appropriate sym*_label2reg for SYM and SIBCALL_P. */
+void
+sh_expand_sym_label2reg (rtx reg, rtx sym, rtx lab, bool sibcall_p)
+{
+ const_tree decl = SYMBOL_REF_DECL (sym);
+ bool is_weak = (decl && DECL_P (decl) && DECL_WEAK (decl));
+
+ if (!is_weak && SYMBOL_REF_LOCAL_P (sym))
+ emit_insn (gen_sym_label2reg (reg, sym, lab));
+ else if (sibcall_p)
+ emit_insn (gen_symPCREL_label2reg (reg, sym, lab));
+ else
+ emit_insn (gen_symPLT_label2reg (reg, sym, lab));
+}
/* Machine specific built-in functions. */
--- a/gcc/config/sh/sh.md
+++ a/gcc/config/sh/sh.md
@@ -135,6 +135,7 @@
UNSPEC_PLT
UNSPEC_CALLER
UNSPEC_GOTPLT
+ UNSPEC_PCREL
UNSPEC_ICACHE
UNSPEC_INIT_TRAMP
UNSPEC_FCOSA
@@ -9470,11 +9471,8 @@ label:
[(const_int 0)]
{
rtx lab = PATTERN (gen_call_site ());
-
- if (SYMBOL_REF_LOCAL_P (operands[0]))
- emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
- else
- emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
+
+ sh_expand_sym_label2reg (operands[2], operands[0], lab, false);
emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab)));
DONE;
}
@@ -9605,10 +9603,7 @@ label:
{
rtx lab = PATTERN (gen_call_site ());
- if (SYMBOL_REF_LOCAL_P (operands[1]))
- emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
- else
- emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
+ sh_expand_sym_label2reg (operands[3], operands[1], lab, false);
emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
operands[2], copy_rtx (lab)));
DONE;
@@ -10008,7 +10003,7 @@ label:
rtx lab = PATTERN (gen_call_site ());
rtx call_insn;
- emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
+ sh_expand_sym_label2reg (operands[2], operands[0], lab, true);
call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
copy_rtx (lab)));
SIBLING_CALL_P (call_insn) = 1;
@@ -10200,7 +10195,7 @@ label:
rtx lab = PATTERN (gen_call_site ());
rtx call_insn;
- emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
+ sh_expand_sym_label2reg (operands[3], operands[1], lab, true);
call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
operands[3],
operands[2],
@@ -10748,6 +10743,16 @@ label:
UNSPEC_SYMOFF)))]
"TARGET_SH1" "")
+(define_expand "symPCREL_label2reg"
+ [(set (match_operand:SI 0 "" "")
+ (const:SI
+ (unspec:SI
+ [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PCREL))
+ (const:SI (plus:SI (match_operand:SI 2 "" "")
+ (const_int 2)))] UNSPEC_PCREL_SYMOFF)))]
+ "TARGET_SH1"
+ "")
+
(define_expand "symGOT_load"
[(set (match_dup 2) (match_operand 1 "" ""))
(set (match_dup 3) (plus (match_dup 2) (reg PIC_REG)))

33
patches/gcc-5.3.0/0003-shbitrot.diff Normal file
View File

@@ -0,0 +1,33 @@
--- gcc-5.2.0.orig/gcc/config.gcc
+++ gcc-5.2.0/gcc/config.gcc
@@ -4096,7 +4099,7 @@
esac
;;
- sh[123456ble]-*-* | sh-*-*)
+ sh[123456ble]*-*-* | sh-*-*)
supported_defaults="cpu"
case "`echo $with_cpu | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ_ abcdefghijklmnopqrstuvwxyz- | sed s/sh/m/`" in
"" | m1 | m2 | m2e | m3 | m3e | m4 | m4-single | m4-single-only | m4-nofpu )
--- gcc-5.2.0.base/gcc/configure.ac 2015-08-11 16:23:36.000000000 +0000
+++ gcc-5.2.0/gcc/configure.ac 2015-09-13 08:17:31.714972082 +0000
@@ -3300,7 +3300,7 @@
tls_first_minor=14
tls_as_opt="-m64 -Aesame --fatal-warnings"
;;
- sh-*-* | sh[34]-*-*)
+ sh-*-* | sh[123456789lbe]*-*-*)
conftest_s='
.section ".tdata","awT",@progbits
foo: .long 25
--- gcc-5.2.0.base/gcc/configure 2015-08-11 16:23:35.000000000 +0000
+++ gcc-5.2.0/gcc/configure 2015-09-13 08:17:42.608304751 +0000
@@ -23754,7 +23754,7 @@
tls_first_minor=14
tls_as_opt="-m64 -Aesame --fatal-warnings"
;;
- sh-*-* | sh[34]-*-*)
+ sh-*-* | sh[123456789lbe]*-*-*)
conftest_s='
.section ".tdata","awT",@progbits
foo: .long 25

349
patches/gcc-5.3.0/0004-j2.diff Normal file
View File

@@ -0,0 +1,349 @@
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 0f2dc32..a3d0d45 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -467,7 +467,7 @@ s390*-*-*)
extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h"
;;
# Note the 'l'; we need to be able to match e.g. "shle" or "shl".
-sh[123456789lbe]*-*-* | sh-*-*)
+sh[123456789lbej]*-*-* | sh-*-*)
cpu_type=sh
extra_options="${extra_options} fused-madd.opt"
extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o"
@@ -2601,19 +2601,19 @@ s390x-ibm-tpf*)
extra_options="${extra_options} s390/tpf.opt"
tmake_file="${tmake_file} s390/t-s390"
;;
-sh-*-elf* | sh[12346l]*-*-elf* | \
- sh-*-linux* | sh[2346lbe]*-*-linux* | \
+sh-*-elf* | sh[12346lj]*-*-elf* | \
+ sh-*-linux* | sh[2346lbej]*-*-linux* | \
sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \
sh64-*-netbsd* | sh64l*-*-netbsd*)
tmake_file="${tmake_file} sh/t-sh sh/t-elf"
if test x${with_endian} = x; then
case ${target} in
- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;;
+ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;;
shbe-*-* | sheb-*-*) with_endian=big,little ;;
sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;;
shl* | sh64l* | sh*-*-linux* | \
sh5l* | sh-superh-elf) with_endian=little,big ;;
- sh[1234]*-*-*) with_endian=big ;;
+ sh[j1234]*-*-*) with_endian=big ;;
*) with_endian=big,little ;;
esac
fi
@@ -2703,6 +2703,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;;
sh2a*) sh_cpu_target=sh2a ;;
sh2e*) sh_cpu_target=sh2e ;;
+ shj2*) sh_cpu_target=shj2;;
sh2*) sh_cpu_target=sh2 ;;
*) sh_cpu_target=sh1 ;;
esac
@@ -2727,7 +2728,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
- sh3e | sh3 | sh2e | sh2 | sh1) ;;
+ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;;
"") sh_cpu_default=${sh_cpu_target} ;;
*) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
esac
@@ -2738,9 +2739,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
sh[1234]*) sh_multilibs=${sh_cpu_target} ;;
sh64* | sh5*) sh_multilibs=m5-32media,m5-32media-nofpu,m5-compact,m5-compact-nofpu,m5-64media,m5-64media-nofpu ;;
sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;;
+ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;;
sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;;
- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
+ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;;
esac
if test x$with_fp = xno; then
sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
@@ -2758,7 +2759,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
m2a | m2a-single | m2a-single-only | m2a-nofpu | \
m5-64media | m5-64media-nofpu | \
m5-32media | m5-32media-nofpu | \
- m5-compact | m5-compact-nofpu)
+ m5-compact | m5-compact-nofpu | \
+ mj2)
# TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
# It is passed to MULTIILIB_OPTIONS verbatim.
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
@@ -2775,7 +2777,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
done
TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
if test x${enable_incomplete_targets} = xyes ; then
- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1"
+ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1 SUPPORT_SHJ2=1"
fi
tm_file="$tm_file ./sysroot-suffix.h"
tmake_file="$tmake_file t-sysroot-suffix"
@@ -4106,6 +4109,8 @@
;;
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
;;
+ mj2)
+ ;;
*)
echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2
echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
@@ -4456,7 +4458,7 @@ case ${target} in
tmake_file="rs6000/t-rs6000 ${tmake_file}"
;;
- sh[123456ble]*-*-* | sh-*-*)
+ sh[123456blej]*-*-* | sh-*-*)
c_target_objs="${c_target_objs} sh-c.o"
cxx_target_objs="${cxx_target_objs} sh-c.o"
;;
diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h
index b08120d..63b77fa 100644
--- a/gcc/config/sh/sh-protos.h
+++ b/gcc/config/sh/sh-protos.h
@@ -45,6 +45,7 @@ struct sh_atomic_model
hard_llcs,
soft_tcb,
soft_imask,
+ hard_cas,
num_models
};
@@ -88,6 +89,9 @@ extern const sh_atomic_model& selected_atomic_model (void);
#define TARGET_ATOMIC_SOFT_IMASK \
(selected_atomic_model ().type == sh_atomic_model::soft_imask)
+#define TARGET_ATOMIC_HARD_CAS \
+ (selected_atomic_model ().type == sh_atomic_model::hard_cas)
+
#ifdef RTX_CODE
extern rtx sh_fsca_sf2int (void);
extern rtx sh_fsca_int2sf (void);
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 0b18ce5..bdf96e2 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -692,6 +692,7 @@ parse_validate_atomic_model_option (const char* str)
model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
model_names[sh_atomic_model::soft_imask] = "soft-imask";
+ model_names[sh_atomic_model::hard_cas] = "hard-cas";
const char* model_cdef_names[sh_atomic_model::num_models];
model_cdef_names[sh_atomic_model::none] = "NONE";
@@ -699,6 +700,7 @@ parse_validate_atomic_model_option (const char* str)
model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
+ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS";
sh_atomic_model ret;
ret.type = sh_atomic_model::none;
@@ -780,6 +782,9 @@ got_mode_name:;
if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
err_ret ("cannot use atomic model %s in user mode", ret.name);
+ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2)
+ err_ret ("atomic model %s is only available J2 targets", ret.name);
+
return ret;
#undef err_ret
@@ -845,6 +850,8 @@ sh_option_override (void)
sh_cpu = PROCESSOR_SH2E;
if (TARGET_SH2A)
sh_cpu = PROCESSOR_SH2A;
+ if (TARGET_SHJ2)
+ sh_cpu = PROCESSOR_SHJ2;
if (TARGET_SH3)
sh_cpu = PROCESSOR_SH3;
if (TARGET_SH3E)
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index 7187c23..9d0d1d0 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -106,6 +106,7 @@ extern int code_for_indirect_jump_scratch;
#define SUPPORT_SH4_SINGLE 1
#define SUPPORT_SH2A 1
#define SUPPORT_SH2A_SINGLE 1
+#define SUPPORT_SHJ2 1
#endif
#define TARGET_DIVIDE_INV \
@@ -157,6 +158,7 @@ extern int code_for_indirect_jump_scratch;
#define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
#define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
#define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
+#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2)
#if SUPPORT_SH1
#define SUPPORT_SH2 1
@@ -164,6 +166,7 @@ extern int code_for_indirect_jump_scratch;
#if SUPPORT_SH2
#define SUPPORT_SH3 1
#define SUPPORT_SH2A_NOFPU 1
+#define SUPPORT_SHJ2 1
#endif
#if SUPPORT_SH3
#define SUPPORT_SH4_NOFPU 1
@@ -211,7 +214,7 @@ extern int code_for_indirect_jump_scratch;
#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
| MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
| MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5 \
- | MASK_FPU_SINGLE_ONLY)
+ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2)
/* This defaults us to big-endian. */
#ifndef TARGET_ENDIAN_DEFAULT
@@ -289,8 +292,8 @@ extern int code_for_indirect_jump_scratch;
%{m5-compact*:--isa=SHcompact} \
%{m5-32media*:--isa=SHmedia --abi=32} \
%{m5-64media*:--isa=SHmedia --abi=64} \
-%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
-
+%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround} \
+%{mj2:-isa=j2}"
#define ASM_SPEC SH_ASM_SPEC
#ifndef SUBTARGET_ASM_ENDIAN_SPEC
@@ -1853,7 +1856,7 @@ struct sh_args {
/* Nonzero if the target supports dynamic shift instructions
like shad and shld. */
-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
+#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2)
/* The cost of using the dynamic shift insns (shad, shld) are the same
if they are available. If they are not available a library function will
@@ -2185,6 +2188,7 @@ enum processor_type {
PROCESSOR_SH2,
PROCESSOR_SH2E,
PROCESSOR_SH2A,
+ PROCESSOR_SHJ2,
PROCESSOR_SH3,
PROCESSOR_SH3E,
PROCESSOR_SH4,
diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
index 1026c73..bac47ed 100644
--- a/gcc/config/sh/sh.opt
+++ b/gcc/config/sh/sh.opt
@@ -71,6 +71,10 @@ m2e
Target RejectNegative Condition(SUPPORT_SH2E)
Generate SH2e code.
+mj2
+Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2)
+Generate J2 code.
+
m3
Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
Generate SH3 code.
diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md
index 6f1337b..cff57b8 100644
--- a/gcc/config/sh/sync.md
+++ b/gcc/config/sh/sync.md
@@ -240,6 +240,9 @@
|| (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem,
exp_val, new_val);
+ else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode)
+ atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem,
+ exp_val, new_val);
else if (TARGET_ATOMIC_SOFT_GUSA)
atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem,
exp_val, new_val);
@@ -306,6 +309,57 @@
}
[(set_attr "length" "14")])
+(define_expand "atomic_compare_and_swapsi_cas"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "r")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{
+ rtx mem = gen_rtx_REG (SImode, 0);
+ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0)));
+ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3]));
+ DONE;
+})
+
+(define_insn "shj2_cas"
+ [(set (match_operand:SI 0 "register_operand" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "register_operand" "=r")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "0")]
+ UNSPECV_CMPXCHG_1))
+ (set (reg:SI T_REG)
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))]
+ "TARGET_ATOMIC_HARD_CAS"
+ "cas.l %2,%0,@%1"
+ [(set_attr "length" "2")]
+)
+
+(define_expand "atomic_compare_and_swapqi_cas"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "arith_operand" "rI08")
+ (match_operand:SI 3 "arith_operand" "rI08")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{FAIL;}
+)
+
+(define_expand "atomic_compare_and_swaphi_cas"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "arith_operand" "rI08")
+ (match_operand:SI 3 "arith_operand" "rI08")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{FAIL;}
+)
+
;; The QIHImode llcs patterns modify the address register of the memory
;; operand. In order to express that, we have to open code the memory
;; operand. Initially the insn is expanded like every other atomic insn
diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh
index 348cc0b..8e6bdaf 100644
--- a/gcc/config/sh/t-sh
+++ b/gcc/config/sh/t-sh
@@ -52,7 +52,7 @@ MULTILIB_MATCHES = $(shell \
m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
m4,m4-100,m4-200,m4-300,m4a \
m5-32media,m5-compact,m5-32media \
- m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu; do \
+ m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu,mj2; do \
subst= ; \
for lib in `echo $$abi|tr , ' '` ; do \
if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \
@@ -65,9 +65,9 @@ MULTILIB_MATCHES = $(shell \
# SH1 and SH2A support big endian only.
ifeq ($(DEFAULT_ENDIAN),ml)
-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
else
-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
endif
MULTILIB_OSDIRNAMES = \
@@ -96,6 +96,7 @@ MULTILIB_OSDIRNAMES = \
m5-compact-nofpu=!m5-compact-nofpu $(OTHER_ENDIAN)/m5-compact-nofpu=!$(OTHER_ENDIAN)/m5-compact-nofpu \
m5-64media=!m5-64media $(OTHER_ENDIAN)/m5-64media=!$(OTHER_ENDIAN)/m5-64media \
m5-64media-nofpu=!m5-64media-nofpu $(OTHER_ENDIAN)/m5-64media-nofpu=!$(OTHER_ENDIAN)/m5-64media-nofpu
+ mj2=!j2
$(out_object_file): gt-sh.h
gt-sh.h : s-gtype ; @true

24
patches/gcc-5.3.0/0005-staticpie.diff Normal file
View File

@@ -0,0 +1,24 @@
--- gcc-5.2.0.orig/gcc/config/gnu-user.h 2015-01-05 12:33:28.000000000 +0000
+++ gcc-5.2.0/gcc/config/gnu-user.h 2015-08-25 08:15:18.354957759 +0000
@@ -42,8 +42,8 @@
#if defined HAVE_LD_PIE
#define GNU_USER_TARGET_STARTFILE_SPEC \
- "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \
- crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \
+ "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:%{static:rcrt1.o%s;:Scrt1.o%s};:crt1.o%s}} \
+ crti.o%s %{shared|pie:crtbeginS.o%s;static:crtbeginT.o%s;:crtbegin.o%s} \
%{fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_start_preinit.o%s; \
fvtable-verify=std:vtv_start.o%s}"
--- gcc-5.2.0.orig/gcc/gcc.c 2015-03-10 09:37:41.000000000 +0000
+++ gcc-5.2.0/gcc/gcc.c 2015-09-30 00:25:33.225927941 +0000
@@ -739,7 +739,7 @@
#ifndef LINK_PIE_SPEC
#ifdef HAVE_LD_PIE
-#define LINK_PIE_SPEC "%{pie:-pie} "
+#define LINK_PIE_SPEC "%{pie:-pie %{static:--no-dynamic-linker}} "
#else
#define LINK_PIE_SPEC "%{pie:} "
#endif

40
patches/gcc-5.3.0/0006-defaultpie.diff Normal file
View File

@@ -0,0 +1,40 @@
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 3779369..a6d95ca 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -3101,6 +3101,12 @@ case ${target} in
;;
esac
+case "x${enable_default_pie}" in
+xyes)
+ tm_defines="${tm_defines} ENABLE_DEFAULT_PIE=1"
+ ;;
+esac
+
t=
all_defaults="abi cpu arch tune schedule float mode fpu divide"
for option in $all_defaults
--- gcc-5.2.0.orig/gcc/gcc.c 2015-03-10 09:37:41.000000000 +0000
+++ gcc-5.2.0/gcc/gcc.c 2015-08-25 07:47:12.895060530 +0000
@@ -1012,10 +1012,19 @@
#define CILK_SELF_SPECS "%{fcilkplus: -pthread}"
#endif
+/* Default to PIE */
+#ifndef PIE_SELF_SPECS
+#ifdef ENABLE_DEFAULT_PIE
+#define PIE_SELF_SPECS "%{shared|pie|r|nostdlib|nopie|no-pie:;:-pie} %{fpic|fPIC|fpie|fPIE|fno-pic|fno-PIC|fno-pie|fno-PIE|D__KERNEL__:;:-fPIE}"
+#else
+#define PIE_SELF_SPECS ""
+#endif
+#endif
+
static const char *const driver_self_specs[] = {
"%{fdump-final-insns:-fdump-final-insns=.} %<fdump-final-insns",
DRIVER_SELF_SPECS, CONFIGURE_SPECS, GOMP_SELF_SPECS, GTM_SELF_SPECS,
- CILK_SELF_SPECS
+ CILK_SELF_SPECS, PIE_SELF_SPECS
};
#ifndef OPTION_DEFAULT_SPECS

1878
patches/gcc-5.3.0/0007-fdpic.diff Normal file
View File

File diff suppressed because it is too large Load Diff

39
patches/gcc-5.3.0/0008-shsibcall.diff Normal file
View File

@@ -0,0 +1,39 @@
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -10476,7 +10476,7 @@
(call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
(match_operand 2 "" "")))
(use (reg:SI FPSCR_MODES_REG))
- (clobber (match_scratch:SI 3 "=&k"))
+ (clobber (reg:SI R1_REG))
(return)]
"TARGET_SH2 && !TARGET_FDPIC"
"#"
@@ -10491,6 +10495,8 @@
rtx lab = PATTERN (gen_call_site ());
rtx call_insn;
+ operands[3] = gen_rtx_REG (SImode, R1_REG);
+
sh_expand_sym_label2reg (operands[3], operands[1], lab, true);
call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
operands[3],
@@ -10511,7 +10519,7 @@
(match_operand 2)))
(use (reg:SI FPSCR_MODES_REG))
(use (reg:SI PIC_REG))
- (clobber (match_scratch:SI 3 "=k"))
+ (clobber (reg:SI R1_REG))
(return)]
"TARGET_SH2 && TARGET_FDPIC"
"#"
@@ -10520,6 +10528,8 @@
{
rtx lab = PATTERN (gen_call_site ());
+ operands[3] = gen_rtx_REG (SImode, R1_REG);
+
sh_expand_sym_label2reg (operands[3], operands[1], lab, true);
rtx i = emit_call_insn (gen_sibcall_valuei_pcrel_fdpic (operands[0],
operands[3],

11
patches/gcc-5.3.0/0009-mipsdw.diff Normal file
View File

@@ -0,0 +1,11 @@
--- a/libgcc/config/mips/linux-unwind.h 2016-04-07 23:08:58.088577977 +0000
+++ b/libgcc/config/mips/linux-unwind.h 2016-04-07 23:04:34.016523639 +0000
@@ -27,7 +27,7 @@
state data appropriately. See unwind-dw2.c for the structs. */
#include <signal.h>
-#include <asm/unistd.h>
+#include <sys/syscall.h>
/* The third parameter to the signal handler points to something with
* this structure defined in asm/ucontext.h, but the name clashes with

24
patches/gcc-5.3.0/0010-cfns-inline-fix.diff Normal file
View File

@@ -0,0 +1,24 @@
diff --git a/gcc/cp/cfns.h b/gcc/cp/cfns.h
index 1c6665d..69699c4 100644
--- a/gcc/cp/cfns.h
+++ b/gcc/cp/cfns.h
@@ -54,6 +54,7 @@ static unsigned int hash (const char *, unsigned int);
#ifdef __GNUC__
__inline
#endif
+static
const char * libc_name_p (const char *, unsigned int);
/* maximum key range = 391, duplicates = 0 */
@@ -124,10 +125,8 @@ hash (register const char *str, register unsigned int len)
#ifdef __GNUC__
__inline
-#ifdef __GNUC_STDC_INLINE__
-__attribute__ ((__gnu_inline__))
-#endif
#endif
+static
const char *
libc_name_p (register const char *str, register unsigned int len)
{

36
patches/gcc-5.3.0/0011-m68k.diff Normal file
View File

@@ -0,0 +1,36 @@
diff -ur gcc-6.4.0/gcc/config/m68k/linux.h gcc-6.4.0.new/gcc/config/m68k/linux.h
--- gcc-6.4.0/gcc/config/m68k/linux.h 2016-01-04 09:30:50.000000000 -0500
+++ gcc-6.4.0.new/gcc/config/m68k/linux.h 2018-06-12 20:03:47.047502695 -0400
@@ -73,6 +73,9 @@
#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#undef MUSL_DYNAMIC_LINKER
+#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-m68k.so.1"
+
#undef LINK_SPEC
#define LINK_SPEC "-m m68kelf %{shared} \
%{!shared: \
diff -ur gcc-6.4.0/libgcc/config/m68k/linux-atomic.c gcc-6.4.0.new/libgcc/config/m68k/linux-atomic.c
--- gcc-6.4.0/libgcc/config/m68k/linux-atomic.c 2016-01-04 09:30:50.000000000 -0500
+++ gcc-6.4.0.new/libgcc/config/m68k/linux-atomic.c 2018-06-07 16:15:11.610163418 -0400
@@ -33,7 +33,6 @@
using the kernel helper defined below. There is no support for
64-bit operations yet. */
-#include <asm/unistd.h>
#include <stdbool.h>
#ifndef __NR_atomic_cmpxchg_32
diff -ur gcc-6.4.0/libgcc/config/m68k/linux-unwind.h gcc-6.4.0.new/libgcc/config/m68k/linux-unwind.h
--- gcc-6.4.0/libgcc/config/m68k/linux-unwind.h 2016-01-04 09:30:50.000000000 -0500
+++ gcc-6.4.0.new/libgcc/config/m68k/linux-unwind.h 2018-06-07 16:17:16.964591108 -0400
@@ -37,7 +37,7 @@
stack_t uc_stack;
mcontext_t uc_mcontext;
unsigned long uc_filler[80];
- __sigset_t uc_sigmask;
+ sigset_t uc_sigmask;
};
#define MD_FALLBACK_FRAME_STATE_FOR m68k_fallback_frame_state

51
patches/gcc-5.3.0/0016-invalid_tls_model.diff Normal file
View File

@@ -0,0 +1,51 @@
--- gcc-7.3.0/libgomp/configure.tgt.orig 2018-09-25 13:44:16.654561098 -0400
+++ gcc-7.3.0/libgomp/configure.tgt 2018-09-25 13:44:50.452688100 -0400
@@ -10,23 +10,6 @@
# XCFLAGS Add extra compile flags to use.
# XLDFLAGS Add extra link flags to use.
-# Optimize TLS usage by avoiding the overhead of dynamic allocation.
-if test $gcc_cv_have_tls = yes ; then
- case "${target}" in
-
- *-*-k*bsd*-gnu*)
- ;;
-
- *-*-linux* | *-*-gnu*)
- XCFLAGS="${XCFLAGS} -ftls-model=initial-exec"
- ;;
-
- *-*-rtems*)
- XCFLAGS="${XCFLAGS} -ftls-model=local-exec"
- ;;
- esac
-fi
-
# Since we require POSIX threads, assume a POSIX system by default.
config_path="posix"
--- gcc-7.3.0/libitm/configure.tgt.orig 2018-09-25 13:47:31.019296903 -0400
+++ gcc-7.3.0/libitm/configure.tgt 2018-09-25 13:47:37.676322335 -0400
@@ -27,22 +27,6 @@
# XCFLAGS Add extra compile flags to use.
# XLDFLAGS Add extra link flags to use.
-# Optimize TLS usage by avoiding the overhead of dynamic allocation.
-if test "$gcc_cv_have_tls" = yes ; then
- case "${target}" in
-
- # For x86, we use slots in the TCB head for most of our TLS.
- # The setup of those slots in beginTransaction can afford to
- # use the global-dynamic model.
- i[456]86-*-linux* | x86_64-*-linux*)
- ;;
-
- *-*-linux*)
- XCFLAGS="${XCFLAGS} -ftls-model=initial-exec"
- ;;
- esac
-fi
-
# Map the target cpu to an ARCH sub-directory. At the same time,
# work out any special compilation flags as necessary.
case "${target_cpu}" in

51
patches/gcc-5.3.0/0017-fix-gthr-weak-refs-for-libgcc.patch Normal file
View File

@@ -0,0 +1,51 @@
From 51a354a0fb54165d505bfed9819c0440027312d9 Mon Sep 17 00:00:00 2001
From: Szabolcs Nagy <nsz@port70.net>
Date: Sun, 22 Sep 2019 23:04:48 +0000
Subject: [PATCH] fix gthr weak refs for libgcc
ideally gthr-posix.h should be fixed not to use weak refs for
single thread detection by default since that's unsafe.
currently we have to opt out explicitly from the unsafe behaviour
in the configure machinery of each target lib that uses gthr and
musl missed libgcc previously.
related bugs and discussions
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78017
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87189
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91737
https://sourceware.org/bugzilla/show_bug.cgi?id=5784
https://sourceware.org/ml/libc-alpha/2012-09/msg00192.html
https://sourceware.org/ml/libc-alpha/2019-08/msg00438.html
---
libgcc/config.host | 7 +++++++
libgcc/config/t-gthr-noweak | 2 ++
2 files changed, 9 insertions(+)
create mode 100644 libgcc/config/t-gthr-noweak
diff --git a/libgcc/config.host b/libgcc/config.host
index 122113fc519..fe1b9ab93d5 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1500,3 +1500,10 @@ aarch64*-*-*)
tm_file="${tm_file} aarch64/value-unwind.h"
;;
esac
+
+case ${host} in
+*-*-musl*)
+ # The gthr weak references are unsafe with static linking
+ tmake_file="$tmake_file t-gthr-noweak"
+ ;;
+esac
diff --git a/libgcc/config/t-gthr-noweak b/libgcc/config/t-gthr-noweak
new file mode 100644
index 00000000000..45a21e9361d
--- /dev/null
+++ b/libgcc/config/t-gthr-noweak
@@ -0,0 +1,2 @@
+# Don't use weak references for single-thread detection
+HOST_LIBGCC2_CFLAGS += -DGTHREAD_USE_WEAK=0
--
2.17.1

18
patches/gcc-5.3.0/0018-libstdc++-futex-time64.diff Normal file
View File

@@ -0,0 +1,18 @@
--- gcc-9.2.0/libstdc++-v3/src/c++11/futex.cc.orig 2020-01-20 14:55:05.507548334 -0500
+++ gcc-9.2.0/libstdc++-v3/src/c++11/futex.cc 2020-01-20 14:56:52.458268068 -0500
@@ -61,7 +61,15 @@
struct timeval tv;
gettimeofday (&tv, NULL);
// Convert the absolute timeout value to a relative timeout
+#if defined(SYS_futex_time64) && SYS_futex_time64 != SYS_futex
+ struct
+ {
+ long tv_sec;
+ long tv_nsec;
+ } rt;
+#else
struct timespec rt;
+#endif
rt.tv_sec = __s.count() - tv.tv_sec;
rt.tv_nsec = __ns.count() - tv.tv_usec * 1000;
if (rt.tv_nsec < 0)

18
patches/gcc-5.3.0/0019-m68k-sqrt.diff Normal file
View File

@@ -0,0 +1,18 @@
--- gcc-9.2.0.orig/gcc/config/m68k/m68k.md 2019-01-01 07:31:55.000000000 -0500
+++ gcc-9.2.0/gcc/config/m68k/m68k.md 2020-07-01 15:57:20.528408009 -0400
@@ -4126,13 +4126,13 @@
(define_expand "sqrt<mode>2"
[(set (match_operand:FP 0 "nonimmediate_operand" "")
(sqrt:FP (match_operand:FP 1 "general_operand" "")))]
- "TARGET_HARD_FLOAT"
+ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU"
"")
(define_insn "sqrt<mode>2_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
- "TARGET_68881"
+ "TARGET_68881 && TARGET_68040"
{
if (FP_REG_P (operands[1]))
return "f<FP:round>sqrt%.x %1,%0";

22
patches/gcc-5.3.0/0020-powerpcspe-musl-ldsoname.diff Normal file
View File

@@ -0,0 +1,22 @@
--- gcc-8.5.0/gcc/config/rs6000/sysv4.h.orig 2021-07-05 12:56:18.398813835 -0400
+++ gcc-8.5.0/gcc/config/rs6000/sysv4.h 2021-06-23 21:49:57.592408186 -0400
@@ -793,7 +793,7 @@
#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
#define MUSL_DYNAMIC_LINKER \
- "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"
+ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float|mcpu=854*|mspe:-sf}.so.1"
#if DEFAULT_LIBC == LIBC_UCLIBC
#define CHOOSE_DYNAMIC_LINKER(G, U, M) \
"%{mglibc:" G ";:%{mmusl:" M ";:" U "}}"
--- gcc-8.5.0/gcc/config/rs6000/linux64.h.orig 2021-07-05 12:54:24.704854044 -0400
+++ gcc-8.5.0/gcc/config/rs6000/linux64.h 2021-07-05 12:56:50.010806923 -0400
@@ -426,7 +426,7 @@
#endif
#define MUSL_DYNAMIC_LINKER32 \
- "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"
+ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float|mcpu=854*|mspe:-sf}.so.1"
#define MUSL_DYNAMIC_LINKER64 \
"/lib/ld-musl-powerpc64" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"

13
patches/gcc-6.5.0/0001-linux_libc_has_function.diff Normal file
View File

@@ -0,0 +1,13 @@
diff --git a/gcc/config/linux.c b/gcc/config/linux.c
index 250296b..16c3768 100644
--- a/gcc/config/linux.c
+++ b/gcc/config/linux.c
@@ -26,7 +26,7 @@ along with GCC; see the file COPYING3. If not see
bool
linux_libc_has_function (enum function_class fn_class)
{
- if (OPTION_GLIBC)
+ if (OPTION_GLIBC || OPTION_MUSL)
return true;
if (OPTION_BIONIC)
if (fn_class == function_c94

14
patches/gcc-6.5.0/0002-ssp_nonshared.diff Normal file
View File

@@ -0,0 +1,14 @@
diff --git a/gcc/gcc.c b/gcc/gcc.c
index 0f042b0..0576ea7 100644
--- a/gcc/gcc.c
+++ b/gcc/gcc.c
@@ -860,7 +860,8 @@ proper position among the other output files. */
#ifndef LINK_SSP_SPEC
#ifdef TARGET_LIBC_PROVIDES_SSP
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
- "|fstack-protector-strong|fstack-protector-explicit:}"
+ "|fstack-protector-strong|fstack-protector-explicit" \
+ ":-lssp_nonshared}"
#else
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
"|fstack-protector-strong|fstack-protector-explicit" \

13
patches/gcc-6.5.0/0003-mips-unwind.diff Normal file
View File

@@ -0,0 +1,13 @@
diff --git a/libgcc/config/mips/linux-unwind.h b/libgcc/config/mips/linux-unwind.h
index bf12de5..4035c121 100644
--- a/libgcc/config/mips/linux-unwind.h
+++ b/libgcc/config/mips/linux-unwind.h
@@ -27,7 +27,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
state data appropriately. See unwind-dw2.c for the structs. */
#include <signal.h>
-#include <asm/unistd.h>
+#include <sys/syscall.h>
/* The third parameter to the signal handler points to something with
* this structure defined in asm/ucontext.h, but the name clashes with

30
patches/gcc-6.5.0/0004-posix_memalign.diff Normal file
View File

@@ -0,0 +1,30 @@
diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h
index a9c2be4..2596a90 100644
--- a/gcc/config/i386/pmm_malloc.h
+++ b/gcc/config/i386/pmm_malloc.h
@@ -27,12 +27,13 @@
#include <stdlib.h>
/* We can't depend on <stdlib.h> since the prototype of posix_memalign
- may not be visible. */
+ may not be visible and we can't pollute the namespace either. */
#ifndef __cplusplus
-extern int posix_memalign (void **, size_t, size_t);
+extern int _mm_posix_memalign (void **, size_t, size_t)
#else
-extern "C" int posix_memalign (void **, size_t, size_t) throw ();
+extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw ()
#endif
+__asm__("posix_memalign");
static __inline void *
_mm_malloc (size_t __size, size_t __alignment)
@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment)
return malloc (__size);
if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4))
__alignment = sizeof (void *);
- if (posix_memalign (&__ptr, __alignment, __size) == 0)
+ if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0)
return __ptr;
else
return NULL;

47
patches/gcc-6.5.0/0005-cilkrts.diff Normal file
View File

@@ -0,0 +1,47 @@
diff --git a/libcilkrts/runtime/os-unix.c b/libcilkrts/runtime/os-unix.c
index cb582dd..e43d7d5 100644
--- a/libcilkrts/runtime/os-unix.c
+++ b/libcilkrts/runtime/os-unix.c
@@ -51,6 +51,7 @@
#if defined __linux__
# include <sys/sysinfo.h>
# include <sys/syscall.h>
+# include <sched.h>
#elif defined __APPLE__
# include <sys/sysctl.h>
// Uses sysconf(_SC_NPROCESSORS_ONLN) in verbose output
@@ -400,28 +401,19 @@ COMMON_SYSDEP void __cilkrts_sleep(void)
COMMON_SYSDEP void __cilkrts_yield(void)
{
-#if __APPLE__ || __FreeBSD__ || __VXWORKS__
- // On MacOS, call sched_yield to yield quantum. I'm not sure why we
- // don't do this on Linux also.
- sched_yield();
-#elif defined(__DragonFly__)
- // On DragonFly BSD, call sched_yield to yield quantum.
- sched_yield();
-#elif defined(__MIC__)
+#if defined(__MIC__)
// On MIC, pthread_yield() really trashes things. Arch's measurements
// showed that calling _mm_delay_32() (or doing nothing) was a better
// option. Delaying 1024 clock cycles is a reasonable compromise between
// giving up the processor and latency starting up when work becomes
// available
_mm_delay_32(1024);
-#elif defined(__ANDROID__) || (defined(__sun__) && defined(__svr4__))
- // On Android and Solaris, call sched_yield to yield quantum. I'm not
- // sure why we don't do this on Linux also.
- sched_yield();
-#else
- // On Linux, call pthread_yield (which in turn will call sched_yield)
- // to yield quantum.
+#elif defined(__sun__) && !defined(__svr4__)
+ // On old SunOS call pthread_yield to yield a quantum.
pthread_yield();
+#else
+ // On other platforms call sched_yield to yield a quantum.
+ sched_yield();
#endif
}

58
patches/gcc-6.5.0/0006-libatomic-test-fix.diff Normal file
View File

@@ -0,0 +1,58 @@
diff --git a/libatomic/testsuite/Makefile.am b/libatomic/testsuite/Makefile.am
index 561b7e2..2548a1b 100644
--- a/libatomic/testsuite/Makefile.am
+++ b/libatomic/testsuite/Makefile.am
@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \
_RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)"
+
+EXTRA_DEJAGNU_SITE_CONFIG = extra.exp
+
+extra.exp:
+ echo 'set BUILD_CC "$(CC)"' > $@.tmp
+ mv $@.tmp $@
diff --git a/libatomic/testsuite/Makefile.in b/libatomic/testsuite/Makefile.in
index 34f83e0..4af67ad 100644
--- a/libatomic/testsuite/Makefile.in
+++ b/libatomic/testsuite/Makefile.in
@@ -222,6 +222,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)"
+EXTRA_DEJAGNU_SITE_CONFIG = extra.exp
all: all-am
.SUFFIXES:
@@ -428,6 +429,10 @@ uninstall-am:
uninstall uninstall-am
+extra.exp:
+ echo 'set BUILD_CC "$(CC)"' > $@.tmp
+ mv $@.tmp $@
+
# Tell versions [3.59,3.63) of GNU make to not export all variables.
# Otherwise a system limit (for SysV at least) may be exceeded.
.NOEXPORT:
diff --git a/libatomic/testsuite/lib/libatomic.exp b/libatomic/testsuite/lib/libatomic.exp
index cafab54..dd2e1a4 100644
--- a/libatomic/testsuite/lib/libatomic.exp
+++ b/libatomic/testsuite/lib/libatomic.exp
@@ -74,6 +74,7 @@ proc libatomic_init { args } {
global ALWAYS_CFLAGS
global CFLAGS
global TOOL_EXECUTABLE TOOL_OPTIONS
+ global BUILD_CC
global GCC_UNDER_TEST
global TESTING_IN_BUILD_TREE
global target_triplet
@@ -89,6 +90,8 @@ proc libatomic_init { args } {
if ![info exists GCC_UNDER_TEST] then {
if [info exists TOOL_EXECUTABLE] {
set GCC_UNDER_TEST $TOOL_EXECUTABLE
+ } elseif [info exists BUILD_CC] {
+ set GCC_UNDER_TEST $BUILD_CC
} else {
set GCC_UNDER_TEST "[find_gcc]"
}

60
patches/gcc-6.5.0/0007-libgomp-test-fix.diff Normal file
View File

@@ -0,0 +1,60 @@
diff --git a/libgomp/testsuite/Makefile.am b/libgomp/testsuite/Makefile.am
index 66a9d94..83d3f67 100644
--- a/libgomp/testsuite/Makefile.am
+++ b/libgomp/testsuite/Makefile.am
@@ -12,6 +12,11 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)"
+EXTRA_DEJAGNU_SITE_CONFIG = extra.exp
+
+extra.exp:
+ echo 'set BUILD_CC "$(CC)"' > $@.tmp
+ mv $@.tmp $@
# Instead of directly in ../testsuite/libgomp-test-support.exp.in, the
# following variables have to be "routed through" this Makefile, for expansion
diff --git a/libgomp/testsuite/Makefile.in b/libgomp/testsuite/Makefile.in
index 4dbb406..001a163 100644
--- a/libgomp/testsuite/Makefile.in
+++ b/libgomp/testsuite/Makefile.in
@@ -254,6 +254,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)"
+EXTRA_DEJAGNU_SITE_CONFIG = extra.exp
all: all-am
.SUFFIXES:
@@ -462,6 +463,10 @@ uninstall-am:
ps ps-am uninstall uninstall-am
+extra.exp:
+ echo 'set BUILD_CC "$(CC)"' > $@.tmp
+ mv $@.tmp $@
+
# Instead of directly in ../testsuite/libgomp-test-support.exp.in, the
# following variables have to be "routed through" this Makefile, for expansion
# of the several (Makefile) variables used therein.
diff --git a/libgomp/testsuite/lib/libgomp.exp b/libgomp/testsuite/lib/libgomp.exp
index 1cb4991..398ba1f 100644
--- a/libgomp/testsuite/lib/libgomp.exp
+++ b/libgomp/testsuite/lib/libgomp.exp
@@ -85,6 +85,7 @@ proc libgomp_init { args } {
global ALWAYS_CFLAGS
global CFLAGS
global TOOL_EXECUTABLE TOOL_OPTIONS
+ global BUILD_CC
global GCC_UNDER_TEST
global TESTING_IN_BUILD_TREE
global target_triplet
@@ -107,6 +108,8 @@ proc libgomp_init { args } {
if ![info exists GCC_UNDER_TEST] then {
if [info exists TOOL_EXECUTABLE] {
set GCC_UNDER_TEST $TOOL_EXECUTABLE
+ } elseif [info exists BUILD_CC] {
+ set GCC_UNDER_TEST $BUILD_CC
} else {
set GCC_UNDER_TEST "[find_gcc]"
}

58
patches/gcc-6.5.0/0008-libitm-test-fix.diff Normal file
View File

@@ -0,0 +1,58 @@
diff --git a/libitm/testsuite/Makefile.am b/libitm/testsuite/Makefile.am
index 561b7e2..2548a1b 100644
--- a/libitm/testsuite/Makefile.am
+++ b/libitm/testsuite/Makefile.am
@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \
_RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)"
+
+EXTRA_DEJAGNU_SITE_CONFIG = extra.exp
+
+extra.exp:
+ echo 'set BUILD_CC "$(CC)"' > $@.tmp
+ mv $@.tmp $@
diff --git a/libitm/testsuite/Makefile.in b/libitm/testsuite/Makefile.in
index 4d79781..46cdc8b 100644
--- a/libitm/testsuite/Makefile.in
+++ b/libitm/testsuite/Makefile.in
@@ -232,6 +232,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)"
+EXTRA_DEJAGNU_SITE_CONFIG = extra.exp
all: all-am
.SUFFIXES:
@@ -438,6 +439,10 @@ uninstall-am:
uninstall uninstall-am
+extra.exp:
+ echo 'set BUILD_CC "$(CC)"' > $@.tmp
+ mv $@.tmp $@
+
# Tell versions [3.59,3.63) of GNU make to not export all variables.
# Otherwise a system limit (for SysV at least) may be exceeded.
.NOEXPORT:
diff --git a/libitm/testsuite/lib/libitm.exp b/libitm/testsuite/lib/libitm.exp
index 0416296..748f492 100644
--- a/libitm/testsuite/lib/libitm.exp
+++ b/libitm/testsuite/lib/libitm.exp
@@ -74,6 +74,7 @@ proc libitm_init { args } {
global ALWAYS_CFLAGS
global CFLAGS
global TOOL_EXECUTABLE TOOL_OPTIONS
+ global BUILD_CC
global GCC_UNDER_TEST
global TESTING_IN_BUILD_TREE
global target_triplet
@@ -89,6 +90,8 @@ proc libitm_init { args } {
if ![info exists GCC_UNDER_TEST] then {
if [info exists TOOL_EXECUTABLE] {
set GCC_UNDER_TEST $TOOL_EXECUTABLE
+ } elseif [info exists BUILD_CC] {
+ set GCC_UNDER_TEST $BUILD_CC
} else {
set GCC_UNDER_TEST "[find_gcc]"
}

58
patches/gcc-6.5.0/0009-libvtv-test-fix.diff Normal file
View File

@@ -0,0 +1,58 @@
diff --git a/libvtv/testsuite/Makefile.am b/libvtv/testsuite/Makefile.am
index 561b7e2..2548a1b 100644
--- a/libvtv/testsuite/Makefile.am
+++ b/libvtv/testsuite/Makefile.am
@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \
_RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)"
+
+EXTRA_DEJAGNU_SITE_CONFIG = extra.exp
+
+extra.exp:
+ echo 'set BUILD_CC "$(CC)"' > $@.tmp
+ mv $@.tmp $@
diff --git a/libvtv/testsuite/Makefile.in b/libvtv/testsuite/Makefile.in
index e19e13e..6528f38 100644
--- a/libvtv/testsuite/Makefile.in
+++ b/libvtv/testsuite/Makefile.in
@@ -227,6 +227,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)"
+EXTRA_DEJAGNU_SITE_CONFIG = extra.exp
all: all-am
.SUFFIXES:
@@ -433,6 +434,10 @@ uninstall-am:
uninstall uninstall-am
+extra.exp:
+ echo 'set BUILD_CC "$(CC)"' > $@.tmp
+ mv $@.tmp $@
+
# Tell versions [3.59,3.63) of GNU make to not export all variables.
# Otherwise a system limit (for SysV at least) may be exceeded.
.NOEXPORT:
diff --git a/libvtv/testsuite/lib/libvtv.exp b/libvtv/testsuite/lib/libvtv.exp
index edf5fdd..a596091 100644
--- a/libvtv/testsuite/lib/libvtv.exp
+++ b/libvtv/testsuite/lib/libvtv.exp
@@ -74,6 +74,7 @@ proc libvtv_init { args } {
global ALWAYS_CFLAGS
global CFLAGS
global TOOL_EXECUTABLE TOOL_OPTIONS
+ global BUILD_CC
global GCC_UNDER_TEST
global TESTING_IN_BUILD_TREE
global target_triplet
@@ -89,6 +90,8 @@ proc libvtv_init { args } {
if ![info exists GCC_UNDER_TEST] then {
if [info exists TOOL_EXECUTABLE] {
set GCC_UNDER_TEST $TOOL_EXECUTABLE
+ } elseif [info exists BUILD_CC] {
+ set GCC_UNDER_TEST $BUILD_CC
} else {
set GCC_UNDER_TEST "[find_gcc]"
}

349
patches/gcc-6.5.0/0011-j2.diff Normal file
View File

@@ -0,0 +1,349 @@
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 1d5b23f..ef0a6ab 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -471,7 +471,7 @@ s390*-*-*)
extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h"
;;
# Note the 'l'; we need to be able to match e.g. "shle" or "shl".
-sh[123456789lbe]*-*-* | sh-*-*)
+sh[123456789lbej]*-*-* | sh-*-*)
cpu_type=sh
extra_options="${extra_options} fused-madd.opt"
extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o"
@@ -2624,19 +2624,19 @@ s390x-ibm-tpf*)
extra_options="${extra_options} s390/tpf.opt"
tmake_file="${tmake_file} s390/t-s390"
;;
-sh-*-elf* | sh[12346l]*-*-elf* | \
- sh-*-linux* | sh[2346lbe]*-*-linux* | \
+sh-*-elf* | sh[12346lj]*-*-elf* | \
+ sh-*-linux* | sh[2346lbej]*-*-linux* | \
sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \
sh64-*-netbsd* | sh64l*-*-netbsd*)
tmake_file="${tmake_file} sh/t-sh sh/t-elf"
if test x${with_endian} = x; then
case ${target} in
- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;;
+ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;;
shbe-*-* | sheb-*-*) with_endian=big,little ;;
sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;;
shl* | sh64l* | sh*-*-linux* | \
sh5l* | sh-superh-elf) with_endian=little,big ;;
- sh[1234]*-*-*) with_endian=big ;;
+ sh[j1234]*-*-*) with_endian=big ;;
*) with_endian=big,little ;;
esac
fi
@@ -2726,6 +2726,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;;
sh2a*) sh_cpu_target=sh2a ;;
sh2e*) sh_cpu_target=sh2e ;;
+ shj2*) sh_cpu_target=shj2;;
sh2*) sh_cpu_target=sh2 ;;
*) sh_cpu_target=sh1 ;;
esac
@@ -2750,7 +2751,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
- sh3e | sh3 | sh2e | sh2 | sh1) ;;
+ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;;
"") sh_cpu_default=${sh_cpu_target} ;;
*) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
esac
@@ -2761,9 +2762,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
sh[1234]*) sh_multilibs=${sh_cpu_target} ;;
sh64* | sh5*) sh_multilibs=m5-32media,m5-32media-nofpu,m5-compact,m5-compact-nofpu,m5-64media,m5-64media-nofpu ;;
sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;;
+ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;;
sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;;
- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
+ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;;
esac
if test x$with_fp = xno; then
sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
@@ -2781,7 +2782,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
m2a | m2a-single | m2a-single-only | m2a-nofpu | \
m5-64media | m5-64media-nofpu | \
m5-32media | m5-32media-nofpu | \
- m5-compact | m5-compact-nofpu)
+ m5-compact | m5-compact-nofpu | \
+ mj2)
# TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
# It is passed to MULTIILIB_OPTIONS verbatim.
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
@@ -2798,7 +2800,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
done
TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
if test x${enable_incomplete_targets} = xyes ; then
- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1"
+ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1 SUPPORT_SHJ2=1"
fi
tm_file="$tm_file ./sysroot-suffix.h"
tmake_file="$tmake_file t-sysroot-suffix"
@@ -4269,6 +4271,8 @@ case "${target}" in
;;
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
;;
+ mj2)
+ ;;
*)
echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2
echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
@@ -4478,7 +4482,7 @@ case ${target} in
tmake_file="rs6000/t-rs6000 ${tmake_file}"
;;
- sh[123456ble]*-*-* | sh-*-*)
+ sh[123456blej]*-*-* | sh-*-*)
c_target_objs="${c_target_objs} sh-c.o"
cxx_target_objs="${cxx_target_objs} sh-c.o"
;;
diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h
index b08120d..63b77fa 100644
--- a/gcc/config/sh/sh-protos.h
+++ b/gcc/config/sh/sh-protos.h
@@ -45,6 +45,7 @@ struct sh_atomic_model
hard_llcs,
soft_tcb,
soft_imask,
+ hard_cas,
num_models
};
@@ -88,6 +89,9 @@ extern const sh_atomic_model& selected_atomic_model (void);
#define TARGET_ATOMIC_SOFT_IMASK \
(selected_atomic_model ().type == sh_atomic_model::soft_imask)
+#define TARGET_ATOMIC_HARD_CAS \
+ (selected_atomic_model ().type == sh_atomic_model::hard_cas)
+
#ifdef RTX_CODE
extern rtx sh_fsca_sf2int (void);
extern rtx sh_fsca_int2sf (void);
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index b18e59b..88520e8 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -692,6 +692,7 @@ parse_validate_atomic_model_option (const char* str)
model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
model_names[sh_atomic_model::soft_imask] = "soft-imask";
+ model_names[sh_atomic_model::hard_cas] = "hard-cas";
const char* model_cdef_names[sh_atomic_model::num_models];
model_cdef_names[sh_atomic_model::none] = "NONE";
@@ -699,6 +700,7 @@ parse_validate_atomic_model_option (const char* str)
model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
+ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS";
sh_atomic_model ret;
ret.type = sh_atomic_model::none;
@@ -780,6 +782,9 @@ got_mode_name:;
if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
err_ret ("cannot use atomic model %s in user mode", ret.name);
+ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2)
+ err_ret ("atomic model %s is only available J2 targets", ret.name);
+
return ret;
#undef err_ret
@@ -845,6 +850,8 @@ sh_option_override (void)
sh_cpu = PROCESSOR_SH2E;
if (TARGET_SH2A)
sh_cpu = PROCESSOR_SH2A;
+ if (TARGET_SHJ2)
+ sh_cpu = PROCESSOR_SHJ2;
if (TARGET_SH3)
sh_cpu = PROCESSOR_SH3;
if (TARGET_SH3E)
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index 7187c23..3bc2817 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -106,6 +106,7 @@ extern int code_for_indirect_jump_scratch;
#define SUPPORT_SH4_SINGLE 1
#define SUPPORT_SH2A 1
#define SUPPORT_SH2A_SINGLE 1
+#define SUPPORT_SHJ2 1
#endif
#define TARGET_DIVIDE_INV \
@@ -157,6 +158,7 @@ extern int code_for_indirect_jump_scratch;
#define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
#define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
#define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
+#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2)
#if SUPPORT_SH1
#define SUPPORT_SH2 1
@@ -164,6 +166,7 @@ extern int code_for_indirect_jump_scratch;
#if SUPPORT_SH2
#define SUPPORT_SH3 1
#define SUPPORT_SH2A_NOFPU 1
+#define SUPPORT_SHJ2 1
#endif
#if SUPPORT_SH3
#define SUPPORT_SH4_NOFPU 1
@@ -211,7 +214,7 @@ extern int code_for_indirect_jump_scratch;
#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
| MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
| MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5 \
- | MASK_FPU_SINGLE_ONLY)
+ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2)
/* This defaults us to big-endian. */
#ifndef TARGET_ENDIAN_DEFAULT
@@ -289,8 +292,8 @@ extern int code_for_indirect_jump_scratch;
%{m5-compact*:--isa=SHcompact} \
%{m5-32media*:--isa=SHmedia --abi=32} \
%{m5-64media*:--isa=SHmedia --abi=64} \
-%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
-
+%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround} \
+%{mj2:-isa=j2}"
#define ASM_SPEC SH_ASM_SPEC
#ifndef SUBTARGET_ASM_ENDIAN_SPEC
@@ -1853,7 +1856,7 @@ struct sh_args {
/* Nonzero if the target supports dynamic shift instructions
like shad and shld. */
-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
+#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2)
/* The cost of using the dynamic shift insns (shad, shld) are the same
if they are available. If they are not available a library function will
@@ -2185,6 +2188,7 @@ enum processor_type {
PROCESSOR_SH2,
PROCESSOR_SH2E,
PROCESSOR_SH2A,
+ PROCESSOR_SHJ2,
PROCESSOR_SH3,
PROCESSOR_SH3E,
PROCESSOR_SH4,
diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
index 1026c73..bac47ed 100644
--- a/gcc/config/sh/sh.opt
+++ b/gcc/config/sh/sh.opt
@@ -71,6 +71,10 @@ m2e
Target RejectNegative Condition(SUPPORT_SH2E)
Generate SH2e code.
+mj2
+Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2)
+Generate J2 code.
+
m3
Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
Generate SH3 code.
diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md
index 6f1337b..7cfd9ef 100644
--- a/gcc/config/sh/sync.md
+++ b/gcc/config/sh/sync.md
@@ -240,6 +240,9 @@
|| (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem,
exp_val, new_val);
+ else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode)
+ atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem,
+ exp_val, new_val);
else if (TARGET_ATOMIC_SOFT_GUSA)
atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem,
exp_val, new_val);
@@ -306,6 +309,57 @@
}
[(set_attr "length" "14")])
+(define_expand "atomic_compare_and_swapsi_cas"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "r")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{
+ rtx mem = gen_rtx_REG (SImode, 0);
+ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0)));
+ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3]));
+ DONE;
+})
+
+(define_insn "shj2_cas"
+ [(set (match_operand:SI 0 "register_operand" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "register_operand" "=r")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "0")]
+ UNSPECV_CMPXCHG_1))
+ (set (reg:SI T_REG)
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))]
+ "TARGET_ATOMIC_HARD_CAS"
+ "cas.l %2,%0,@%1"
+ [(set_attr "length" "2")]
+)
+
+(define_expand "atomic_compare_and_swapqi_cas"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "arith_operand" "rI08")
+ (match_operand:SI 3 "arith_operand" "rI08")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{FAIL;}
+)
+
+(define_expand "atomic_compare_and_swaphi_cas"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "arith_operand" "rI08")
+ (match_operand:SI 3 "arith_operand" "rI08")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{FAIL;}
+)
+
;; The QIHImode llcs patterns modify the address register of the memory
;; operand. In order to express that, we have to open code the memory
;; operand. Initially the insn is expanded like every other atomic insn
diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh
index 348cc0b..8e6bdaf 100644
--- a/gcc/config/sh/t-sh
+++ b/gcc/config/sh/t-sh
@@ -52,7 +52,7 @@ MULTILIB_MATCHES = $(shell \
m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
m4,m4-100,m4-200,m4-300,m4a \
m5-32media,m5-compact,m5-32media \
- m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu; do \
+ m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu,mj2; do \
subst= ; \
for lib in `echo $$abi|tr , ' '` ; do \
if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \
@@ -65,9 +65,9 @@ MULTILIB_MATCHES = $(shell \
# SH1 and SH2A support big endian only.
ifeq ($(DEFAULT_ENDIAN),ml)
-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
else
-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
endif
MULTILIB_OSDIRNAMES = \
@@ -96,6 +96,7 @@ MULTILIB_OSDIRNAMES = \
m5-compact-nofpu=!m5-compact-nofpu $(OTHER_ENDIAN)/m5-compact-nofpu=!$(OTHER_ENDIAN)/m5-compact-nofpu \
m5-64media=!m5-64media $(OTHER_ENDIAN)/m5-64media=!$(OTHER_ENDIAN)/m5-64media \
m5-64media-nofpu=!m5-64media-nofpu $(OTHER_ENDIAN)/m5-64media-nofpu=!$(OTHER_ENDIAN)/m5-64media-nofpu
+ mj2=!j2
$(out_object_file): gt-sh.h
gt-sh.h : s-gtype ; @true

14
patches/gcc-6.5.0/0012-s390x-muslldso.diff Normal file
View File

@@ -0,0 +1,14 @@
diff --git a/gcc/config/s390/linux.h b/gcc/config/s390/linux.h
index 9b00af7..3aacde6 100644
--- a/gcc/config/s390/linux.h
+++ b/gcc/config/s390/linux.h
@@ -63,6 +63,9 @@ along with GCC; see the file COPYING3. If not see
#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
#define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1"
+#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-s390.so.1"
+#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-s390x.so.1"
+
#undef LINK_SPEC
#define LINK_SPEC \
"%{m31:-m elf_s390}%{m64:-m elf64_s390} \

20
patches/gcc-6.5.0/0013-microblaze-pr65649.diff Normal file
View File

@@ -0,0 +1,20 @@
--- gcc-6.3.0/gcc/config/microblaze/microblaze.c.orig 2017-01-02 15:07:18.924082703 -0500
+++ gcc-6.3.0/gcc/config/microblaze/microblaze.c 2017-01-02 15:08:06.362438573 -0500
@@ -2364,7 +2364,7 @@
unsigned long value_long;
REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op),
value_long);
- fprintf (file, HOST_WIDE_INT_PRINT_HEX, value_long);
+ fprintf (file, "0x%lx", value_long);
}
else
{
@@ -2423,7 +2423,7 @@
print_operand_address (file, XEXP (op, 0));
}
else if (letter == 'm')
- fprintf (file, HOST_WIDE_INT_PRINT_DEC, (1L << INTVAL (op)));
+ fprintf (file, "%ld", (1L << INTVAL (op)));
else
output_addr_const (file, op);
}

36
patches/gcc-6.5.0/0014-m68k.diff Normal file
View File

@@ -0,0 +1,36 @@
diff -ur gcc-6.4.0/gcc/config/m68k/linux.h gcc-6.4.0.new/gcc/config/m68k/linux.h
--- gcc-6.4.0/gcc/config/m68k/linux.h 2016-01-04 09:30:50.000000000 -0500
+++ gcc-6.4.0.new/gcc/config/m68k/linux.h 2018-06-12 20:03:47.047502695 -0400
@@ -73,6 +73,9 @@
#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+#undef MUSL_DYNAMIC_LINKER
+#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-m68k.so.1"
+
#undef LINK_SPEC
#define LINK_SPEC "-m m68kelf %{shared} \
%{!shared: \
diff -ur gcc-6.4.0/libgcc/config/m68k/linux-atomic.c gcc-6.4.0.new/libgcc/config/m68k/linux-atomic.c
--- gcc-6.4.0/libgcc/config/m68k/linux-atomic.c 2016-01-04 09:30:50.000000000 -0500
+++ gcc-6.4.0.new/libgcc/config/m68k/linux-atomic.c 2018-06-07 16:15:11.610163418 -0400
@@ -33,7 +33,6 @@
using the kernel helper defined below. There is no support for
64-bit operations yet. */
-#include <asm/unistd.h>
#include <stdbool.h>
#ifndef __NR_atomic_cmpxchg_32
diff -ur gcc-6.4.0/libgcc/config/m68k/linux-unwind.h gcc-6.4.0.new/libgcc/config/m68k/linux-unwind.h
--- gcc-6.4.0/libgcc/config/m68k/linux-unwind.h 2016-01-04 09:30:50.000000000 -0500
+++ gcc-6.4.0.new/libgcc/config/m68k/linux-unwind.h 2018-06-07 16:17:16.964591108 -0400
@@ -37,7 +37,7 @@
stack_t uc_stack;
mcontext_t uc_mcontext;
unsigned long uc_filler[80];
- __sigset_t uc_sigmask;
+ sigset_t uc_sigmask;
};
#define MD_FALLBACK_FRAME_STATE_FOR m68k_fallback_frame_state

51
patches/gcc-6.5.0/0016-invalid_tls_model.diff Normal file
View File

@@ -0,0 +1,51 @@
--- gcc-7.3.0/libgomp/configure.tgt.orig 2018-09-25 13:44:16.654561098 -0400
+++ gcc-7.3.0/libgomp/configure.tgt 2018-09-25 13:44:50.452688100 -0400
@@ -10,23 +10,6 @@
# XCFLAGS Add extra compile flags to use.
# XLDFLAGS Add extra link flags to use.
-# Optimize TLS usage by avoiding the overhead of dynamic allocation.
-if test $gcc_cv_have_tls = yes ; then
- case "${target}" in
-
- *-*-k*bsd*-gnu*)
- ;;
-
- *-*-linux* | *-*-gnu*)
- XCFLAGS="${XCFLAGS} -ftls-model=initial-exec"
- ;;
-
- *-*-rtems*)
- XCFLAGS="${XCFLAGS} -ftls-model=local-exec"
- ;;
- esac
-fi
-
# Since we require POSIX threads, assume a POSIX system by default.
config_path="posix"
--- gcc-7.3.0/libitm/configure.tgt.orig 2018-09-25 13:47:31.019296903 -0400
+++ gcc-7.3.0/libitm/configure.tgt 2018-09-25 13:47:37.676322335 -0400
@@ -27,22 +27,6 @@
# XCFLAGS Add extra compile flags to use.
# XLDFLAGS Add extra link flags to use.
-# Optimize TLS usage by avoiding the overhead of dynamic allocation.
-if test "$gcc_cv_have_tls" = yes ; then
- case "${target}" in
-
- # For x86, we use slots in the TCB head for most of our TLS.
- # The setup of those slots in beginTransaction can afford to
- # use the global-dynamic model.
- i[456]86-*-linux* | x86_64-*-linux*)
- ;;
-
- *-*-linux*)
- XCFLAGS="${XCFLAGS} -ftls-model=initial-exec"
- ;;
- esac
-fi
-
# Map the target cpu to an ARCH sub-directory. At the same time,
# work out any special compilation flags as necessary.
case "${target_cpu}" in

43
patches/gcc-6.5.0/0017-c++-abi-break.diff Normal file
View File

@@ -0,0 +1,43 @@
From https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87822
Author: Jonathan Wakely <jwakely@redhat.com>
Date: Wed Oct 31 13:03:25 2018 +0000
PR libstdc++/87822 fix layout change for nested std::pair
The introduction of the empty __pair_base base class for PR 86751
changed the layout of std::pair<std::pair<...>, ...>. The outer pair and
its first member both have a base class of the same type, which cannot
exist at the same address. This causes the first member to be at a
non-zero offset.
The solution is to make the base class depend on the template
parameters, so that each pair type has a different base class type,
which allows the base classes of the outer pair and its first member to
have the same address.
PR libstdc++/87822
* include/bits/stl_pair.h (__pair_base): Change to class template.
(pair): Make base class type depend on template parameters.
diff --git a/libstdc++-v3/include/bits/stl_pair.h b/libstdc++-v3/include/bits/stl_pair.h
index a30b630b4fd..5a4823ab018 100644
--- a/libstdc++-v3/include/bits/stl_pair.h
+++ b/libstdc++-v3/include/bits/stl_pair.h
@@ -183,7 +183,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
};
#endif // C++11
- class __pair_base
+ template<typename _U1, typename _U2> class __pair_base
{
#if __cplusplus >= 201103L
template<typename _T1, typename _T2> friend struct pair;
@@ -202,7 +202,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
*/
template<typename _T1, typename _T2>
struct pair
- : private __pair_base
+ : private __pair_base<_T1, _T2>
{
typedef _T1 first_type; /// @c first_type is the first bound type
typedef _T2 second_type; /// @c second_type is the second bound type

147
patches/gcc-6.5.0/0018-Revert-PR-driver-81523-Make-static-override-pie.diff Normal file
View File

@@ -0,0 +1,147 @@
diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h
index de605b0c466..2787a3d16be 100644
--- a/gcc/config/gnu-user.h
+++ b/gcc/config/gnu-user.h
@@ -50,28 +50,19 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#if defined HAVE_LD_PIE
#define GNU_USER_TARGET_STARTFILE_SPEC \
- "%{shared:; \
- pg|p|profile:gcrt1.o%s; \
- static:crt1.o%s; \
- " PIE_SPEC ":Scrt1.o%s; \
- :crt1.o%s} \
- crti.o%s \
- %{static:crtbeginT.o%s; \
- shared|" PIE_SPEC ":crtbeginS.o%s; \
- :crtbegin.o%s} \
+ "%{!shared: %{pg|p|profile:gcrt1.o%s;: \
+ %{" PIE_SPEC ":Scrt1.o%s} %{" NO_PIE_SPEC ":crt1.o%s}}} \
+ crti.o%s %{static:crtbeginT.o%s;: %{shared:crtbeginS.o%s} \
+ %{" PIE_SPEC ":crtbeginS.o%s} \
+ %{" NO_PIE_SPEC ":crtbegin.o%s}} \
%{fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_start_preinit.o%s; \
fvtable-verify=std:vtv_start.o%s} \
" CRTOFFLOADBEGIN
#else
#define GNU_USER_TARGET_STARTFILE_SPEC \
- "%{shared:; \
- pg|p|profile:gcrt1.o%s; \
- :crt1.o%s} \
- crti.o%s \
- %{static:crtbeginT.o%s; \
- shared|pie:crtbeginS.o%s; \
- :crtbegin.o%s} \
+ "%{!shared: %{pg|p|profile:gcrt1.o%s;:crt1.o%s}} \
+ crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \
%{fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_start_preinit.o%s; \
fvtable-verify=std:vtv_start.o%s} \
@@ -91,20 +82,15 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
"%{fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_end_preinit.o%s; \
fvtable-verify=std:vtv_end.o%s} \
- %{static:crtend.o%s; \
- shared|" PIE_SPEC ":crtendS.o%s; \
- :crtend.o%s} \
- crtn.o%s \
+ %{shared:crtendS.o%s;: %{" PIE_SPEC ":crtendS.o%s} \
+ %{" NO_PIE_SPEC ":crtend.o%s}} crtn.o%s \
" CRTOFFLOADEND
#else
#define GNU_USER_TARGET_ENDFILE_SPEC \
"%{fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_end_preinit.o%s; \
fvtable-verify=std:vtv_end.o%s} \
- %{static:crtend.o%s; \
- shared|pie:crtendS.o%s; \
- :crtend.o%s} \
- crtn.o%s \
+ %{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s \
" CRTOFFLOADEND
#endif
#undef ENDFILE_SPEC
diff --git a/gcc/config/sol2.h b/gcc/config/sol2.h
index d522de03f4a..13b27873719 100644
--- a/gcc/config/sol2.h
+++ b/gcc/config/sol2.h
@@ -174,9 +174,9 @@ along with GCC; see the file COPYING3. If not see
%{!ansi:values-Xa.o%s}"
#if defined(HAVE_LD_PIE) && defined(HAVE_SOLARIS_CRTS)
-#define STARTFILE_CRTBEGIN_SPEC "%{static:crtbegin.o%s; \
- shared|" PIE_SPEC ":crtbeginS.o%s; \
- :crtbegin.o%s}"
+#define STARTFILE_CRTBEGIN_SPEC "%{shared:crtbeginS.o%s} \
+ %{" PIE_SPEC ":crtbeginS.o%s} \
+ %{" NO_PIE_SPEC ":crtbegin.o%s}"
#else
#define STARTFILE_CRTBEGIN_SPEC "crtbegin.o%s"
#endif
@@ -224,9 +224,9 @@ along with GCC; see the file COPYING3. If not see
#endif
#if defined(HAVE_LD_PIE) && defined(HAVE_SOLARIS_CRTS)
-#define ENDFILE_CRTEND_SPEC "%{static:crtend.o%s; \
- shared|" PIE_SPEC ":crtendS.o%s; \
- :crtend.o%s}"
+#define ENDFILE_CRTEND_SPEC "%{shared:crtendS.o%s;: \
+ %{" PIE_SPEC ":crtendS.o%s} \
+ %{" NO_PIE_SPEC ":crtend.o%s}}"
#else
#define ENDFILE_CRTEND_SPEC "crtend.o%s"
#endif
diff --git a/gcc/gcc.c b/gcc/gcc.c
index e2fae4ef055..91eb0534722 100644
--- a/gcc/gcc.c
+++ b/gcc/gcc.c
@@ -873,7 +873,8 @@ proper position among the other output files. */
#endif
#ifdef ENABLE_DEFAULT_PIE
-#define PIE_SPEC "!no-pie"
+#define NO_PIE_SPEC "no-pie|static"
+#define PIE_SPEC NO_PIE_SPEC "|r|shared:;"
#define NO_FPIE1_SPEC "fno-pie"
#define FPIE1_SPEC NO_FPIE1_SPEC ":;"
#define NO_FPIE2_SPEC "fno-PIE"
@@ -894,6 +895,7 @@ proper position among the other output files. */
#define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;"
#else
#define PIE_SPEC "pie"
+#define NO_PIE_SPEC PIE_SPEC "|r|shared:;"
#define FPIE1_SPEC "fpie"
#define NO_FPIE1_SPEC FPIE1_SPEC ":;"
#define FPIE2_SPEC "fPIE"
@@ -922,7 +924,7 @@ proper position among the other output files. */
#else
#define LD_PIE_SPEC ""
#endif
-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
+#define LINK_PIE_SPEC "%{no-pie:} " "%{" PIE_SPEC ":" LD_PIE_SPEC "} "
#endif
#ifndef LINK_BUILDID_SPEC
@@ -1010,10 +1012,8 @@ proper position among the other output files. */
#endif
/* -u* was put back because both BSD and SysV seem to support it. */
-/* %{static|no-pie:} simply prevents an error message:
- 1. If the target machine doesn't handle -static.
- 2. If PIE isn't enabled by default.
- */
+/* %{static:} simply prevents an error message if the target machine
+ doesn't handle -static. */
/* We want %{T*} after %{L*} and %D so that it can be used to specify linker
scripts which exist in user specified directories, or in standard
directories. */
@@ -1030,7 +1030,7 @@ proper position among the other output files. */
"%{fuse-ld=*:-fuse-ld=%*} " LINK_COMPRESS_DEBUG_SPEC \
"%X %{o*} %{e*} %{N} %{n} %{r}\
%{s} %{t} %{u*} %{z} %{Z} %{!nostdlib:%{!nostartfiles:%S}} \
- %{static|no-pie:} %{L*} %(mfwrap) %(link_libgcc) " \
+ %{static:} %{L*} %(mfwrap) %(link_libgcc) " \
VTABLE_VERIFICATION_SPEC " " SANITIZER_EARLY_SPEC " %o " CHKP_SPEC " \
%{fopenacc|fopenmp|%:gt(%{ftree-parallelize-loops=*:%*} 1):\
%:include(libgomp.spec)%(link_gomp)}\

57
patches/gcc-6.5.0/0019-Revert-RS6000-linux-startfile-endfile.diff Normal file
View File

@@ -0,0 +1,57 @@
diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
index cbee89140dd..de386291a51 100644
--- a/gcc/config/rs6000/sysv4.h
+++ b/gcc/config/rs6000/sysv4.h
@@ -757,34 +757,24 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN)
#define CRTOFFLOADEND ""
#endif
-/* STARTFILE_LINUX_SPEC should be the same as GNU_USER_TARGET_STARTFILE_SPEC
- but with the mnewlib ecrti.o%s selection substituted for crti.o%s. */
-#define STARTFILE_LINUX_SPEC \
- "%{shared:; \
- pg|p|profile:gcrt1.o%s; \
- static:crt1.o%s; \
- " PIE_SPEC ":Scrt1.o%s; \
- :crt1.o%s} \
- %{mnewlib:ecrti.o%s;:crti.o%s} \
- %{static:crtbeginT.o%s; \
- shared|" PIE_SPEC ":crtbeginS.o%s; \
- :crtbegin.o%s} \
- %{fvtable-verify=none:%s; \
- fvtable-verify=preinit:vtv_start_preinit.o%s; \
- fvtable-verify=std:vtv_start.o%s} \
- " CRTOFFLOADBEGIN
-
-/* ENDFILE_LINUX_SPEC should be the same as GNU_USER_TARGET_ENDFILE_SPEC
- but with the mnewlib ecrtn.o%s selection substituted for crtn.o%s. */
-#define ENDFILE_LINUX_SPEC \
- "%{fvtable-verify=none:%s; \
- fvtable-verify=preinit:vtv_end_preinit.o%s; \
- fvtable-verify=std:vtv_end.o%s} \
- %{static:crtend.o%s; \
- shared|" PIE_SPEC ":crtendS.o%s; \
- :crtend.o%s} \
- %{mnewlib:ecrtn.o%s;:crtn.o%s} \
- " CRTOFFLOADEND
+#ifdef HAVE_LD_PIE
+#define STARTFILE_LINUX_SPEC "\
+%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \
+%{mnewlib:ecrti.o%s;:crti.o%s} \
+%{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \
+" CRTOFFLOADBEGIN
+#else
+#define STARTFILE_LINUX_SPEC "\
+%{!shared: %{pg|p|profile:gcrt1.o%s;:crt1.o%s}} \
+%{mnewlib:ecrti.o%s;:crti.o%s} \
+%{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \
+" CRTOFFLOADBEGIN
+#endif
+
+#define ENDFILE_LINUX_SPEC "\
+%{shared|pie:crtendS.o%s;:crtend.o%s} \
+%{mnewlib:ecrtn.o%s;:crtn.o%s} \
+" CRTOFFLOADEND
#define LINK_START_LINUX_SPEC ""

40
patches/gcc-6.5.0/0020-static-pie-support.diff Normal file
View File

@@ -0,0 +1,40 @@
diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h
index b0bf40a..d4b56fe 100644
--- a/gcc/config/gnu-user.h
+++ b/gcc/config/gnu-user.h
@@ -51,10 +51,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#if defined HAVE_LD_PIE
#define GNU_USER_TARGET_STARTFILE_SPEC \
"%{!shared: %{pg|p|profile:gcrt1.o%s;: \
- %{" PIE_SPEC ":Scrt1.o%s} %{" NO_PIE_SPEC ":crt1.o%s}}} \
- crti.o%s %{static:crtbeginT.o%s;: %{shared:crtbeginS.o%s} \
+ %{" PIE_SPEC ":%{static:rcrt1.o%s;:Scrt1.o%s}} %{" NO_PIE_SPEC ":crt1.o%s}}} \
+ crti.o%s %{shared:crtbeginS.o%s;: \
%{" PIE_SPEC ":crtbeginS.o%s} \
- %{" NO_PIE_SPEC ":crtbegin.o%s}} \
+ %{" NO_PIE_SPEC ":%{static:crtbeginT.o%s;:crtbegin.o%s}}} \
%{fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_start_preinit.o%s; \
fvtable-verify=std:vtv_start.o%s} \
diff --git a/gcc/gcc.c b/gcc/gcc.c
index 0576ea7..0a280e0 100644
--- a/gcc/gcc.c
+++ b/gcc/gcc.c
@@ -870,7 +870,7 @@ proper position among the other output files. */
#endif
#ifdef ENABLE_DEFAULT_PIE
-#define NO_PIE_SPEC "no-pie|static"
+#define NO_PIE_SPEC "no-pie"
#define PIE_SPEC NO_PIE_SPEC "|r|shared:;"
#define NO_FPIE1_SPEC "fno-pie"
#define FPIE1_SPEC NO_FPIE1_SPEC ":;"
@@ -916,7 +916,7 @@ proper position among the other output files. */
#ifndef LINK_PIE_SPEC
#ifdef HAVE_LD_PIE
#ifndef LD_PIE_SPEC
-#define LD_PIE_SPEC "-pie"
+#define LD_PIE_SPEC "-pie %{static:--no-dynamic-linker -Bsymbolic}"
#endif
#else
#define LD_PIE_SPEC ""

51
patches/gcc-6.5.0/0021-fix-gthr-weak-refs-for-libgcc.patch Normal file
View File

@@ -0,0 +1,51 @@
From 51a354a0fb54165d505bfed9819c0440027312d9 Mon Sep 17 00:00:00 2001
From: Szabolcs Nagy <nsz@port70.net>
Date: Sun, 22 Sep 2019 23:04:48 +0000
Subject: [PATCH] fix gthr weak refs for libgcc
ideally gthr-posix.h should be fixed not to use weak refs for
single thread detection by default since that's unsafe.
currently we have to opt out explicitly from the unsafe behaviour
in the configure machinery of each target lib that uses gthr and
musl missed libgcc previously.
related bugs and discussions
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78017
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87189
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91737
https://sourceware.org/bugzilla/show_bug.cgi?id=5784
https://sourceware.org/ml/libc-alpha/2012-09/msg00192.html
https://sourceware.org/ml/libc-alpha/2019-08/msg00438.html
---
libgcc/config.host | 7 +++++++
libgcc/config/t-gthr-noweak | 2 ++
2 files changed, 9 insertions(+)
create mode 100644 libgcc/config/t-gthr-noweak
diff --git a/libgcc/config.host b/libgcc/config.host
index 122113fc519..fe1b9ab93d5 100644
--- a/libgcc/config.host
+++ b/libgcc/config.host
@@ -1500,3 +1500,10 @@ aarch64*-*-*)
tm_file="${tm_file} aarch64/value-unwind.h"
;;
esac
+
+case ${host} in
+*-*-musl*)
+ # The gthr weak references are unsafe with static linking
+ tmake_file="$tmake_file t-gthr-noweak"
+ ;;
+esac
diff --git a/libgcc/config/t-gthr-noweak b/libgcc/config/t-gthr-noweak
new file mode 100644
index 00000000000..45a21e9361d
--- /dev/null
+++ b/libgcc/config/t-gthr-noweak
@@ -0,0 +1,2 @@
+# Don't use weak references for single-thread detection
+HOST_LIBGCC2_CFLAGS += -DGTHREAD_USE_WEAK=0
--
2.17.1

18
patches/gcc-6.5.0/0022-libstdc++-futex-time64.diff Normal file
View File

@@ -0,0 +1,18 @@
--- gcc-9.2.0/libstdc++-v3/src/c++11/futex.cc.orig 2020-01-20 14:55:05.507548334 -0500
+++ gcc-9.2.0/libstdc++-v3/src/c++11/futex.cc 2020-01-20 14:56:52.458268068 -0500
@@ -61,7 +61,15 @@
struct timeval tv;
gettimeofday (&tv, NULL);
// Convert the absolute timeout value to a relative timeout
+#if defined(SYS_futex_time64) && SYS_futex_time64 != SYS_futex
+ struct
+ {
+ long tv_sec;
+ long tv_nsec;
+ } rt;
+#else
struct timespec rt;
+#endif
rt.tv_sec = __s.count() - tv.tv_sec;
rt.tv_nsec = __ns.count() - tv.tv_usec * 1000;
if (rt.tv_nsec < 0)

45
patches/gcc-6.5.0/0023-pr93402.diff Normal file
View File

@@ -0,0 +1,45 @@
2020-01-23 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/93402
* postreload.c (reload_combine_recognize_pattern): Don't try to adjust
USE insns.
* gcc.c-torture/execute/pr93402.c: New test.
--- a/gcc/postreload.c.jj 2020-01-12 11:54:36.000000000 +0100
+++ b/gcc/postreload.c 2020-01-23 17:23:25.359929516 +0100
@@ -1078,6 +1078,10 @@ reload_combine_recognize_pattern (rtx_in
struct reg_use *use = reg_state[regno].reg_use + i;
if (GET_MODE (*use->usep) != mode)
return false;
+ /* Don't try to adjust (use (REGX)). */
+ if (GET_CODE (PATTERN (use->insn)) == USE
+ && &XEXP (PATTERN (use->insn), 0) == use->usep)
+ return false;
}
/* Look for (set (REGX) (CONST_INT))
--- a/gcc/testsuite/gcc.c-torture/execute/pr93402.c.jj 2020-01-23 17:25:46.496803852 +0100
+++ b/gcc/testsuite/gcc.c-torture/execute/pr93402.c 2020-01-23 17:25:05.221425501 +0100
@@ -0,0 +1,21 @@
+/* PR rtl-optimization/93402 */
+
+struct S { unsigned int a; unsigned long long b; };
+
+__attribute__((noipa)) struct S
+foo (unsigned long long x)
+{
+ struct S ret;
+ ret.a = 0;
+ ret.b = x * 11111111111ULL + 111111111111ULL;
+ return ret;
+}
+
+int
+main ()
+{
+ struct S a = foo (1);
+ if (a.a != 0 || a.b != 122222222222ULL)
+ __builtin_abort ();
+ return 0;
+}

18
patches/gcc-6.5.0/0024-m68k-sqrt.diff Normal file
View File

@@ -0,0 +1,18 @@
--- gcc-9.2.0.orig/gcc/config/m68k/m68k.md 2019-01-01 07:31:55.000000000 -0500
+++ gcc-9.2.0/gcc/config/m68k/m68k.md 2020-07-01 15:57:20.528408009 -0400
@@ -4126,13 +4126,13 @@
(define_expand "sqrt<mode>2"
[(set (match_operand:FP 0 "nonimmediate_operand" "")
(sqrt:FP (match_operand:FP 1 "general_operand" "")))]
- "TARGET_HARD_FLOAT"
+ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU"
"")
(define_insn "sqrt<mode>2_68881"
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
(sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
- "TARGET_68881"
+ "TARGET_68881 && TARGET_68040"
{
if (FP_REG_P (operands[1]))
return "f<FP:round>sqrt%.x %1,%0";

22
patches/gcc-6.5.0/0025-powerpcspe-musl-ldsoname.diff Normal file
View File

@@ -0,0 +1,22 @@
--- gcc-8.5.0/gcc/config/rs6000/sysv4.h.orig 2021-07-05 12:56:18.398813835 -0400
+++ gcc-8.5.0/gcc/config/rs6000/sysv4.h 2021-06-23 21:49:57.592408186 -0400
@@ -793,7 +793,7 @@
#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
#define MUSL_DYNAMIC_LINKER \
- "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"
+ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float|mcpu=854*|mspe:-sf}.so.1"
#if DEFAULT_LIBC == LIBC_UCLIBC
#define CHOOSE_DYNAMIC_LINKER(G, U, M) \
"%{mglibc:" G ";:%{mmusl:" M ";:" U "}}"
--- gcc-8.5.0/gcc/config/rs6000/linux64.h.orig 2021-07-05 12:54:24.704854044 -0400
+++ gcc-8.5.0/gcc/config/rs6000/linux64.h 2021-07-05 12:56:50.010806923 -0400
@@ -426,7 +426,7 @@
#endif
#define MUSL_DYNAMIC_LINKER32 \
- "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"
+ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float|mcpu=854*|mspe:-sf}.so.1"
#define MUSL_DYNAMIC_LINKER64 \
"/lib/ld-musl-powerpc64" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"

14
patches/gcc-7.5.0/0001-ssp_nonshared.diff Normal file
View File

@@ -0,0 +1,14 @@
diff --git a/gcc/gcc.c b/gcc/gcc.c
index c48178f1aa3..e2fae4ef055 100644
--- a/gcc/gcc.c
+++ b/gcc/gcc.c
@@ -863,7 +863,8 @@ proper position among the other output files. */
#ifndef LINK_SSP_SPEC
#ifdef TARGET_LIBC_PROVIDES_SSP
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
- "|fstack-protector-strong|fstack-protector-explicit:}"
+ "|fstack-protector-strong|fstack-protector-explicit" \
+ ":-lssp_nonshared}"
#else
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
"|fstack-protector-strong|fstack-protector-explicit" \

30
patches/gcc-7.5.0/0002-posix_memalign.diff Normal file
View File

@@ -0,0 +1,30 @@
diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h
index 73d9e887b4b..33f998702fa 100644
--- a/gcc/config/i386/pmm_malloc.h
+++ b/gcc/config/i386/pmm_malloc.h
@@ -27,12 +27,13 @@
#include <stdlib.h>
/* We can't depend on <stdlib.h> since the prototype of posix_memalign
- may not be visible. */
+ may not be visible and we can't pollute the namespace either. */
#ifndef __cplusplus
-extern int posix_memalign (void **, size_t, size_t);
+extern int _mm_posix_memalign (void **, size_t, size_t)
#else
-extern "C" int posix_memalign (void **, size_t, size_t) throw ();
+extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw ()
#endif
+__asm__("posix_memalign");
static __inline void *
_mm_malloc (size_t __size, size_t __alignment)
@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment)
return malloc (__size);
if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4))
__alignment = sizeof (void *);
- if (posix_memalign (&__ptr, __alignment, __size) == 0)
+ if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0)
return __ptr;
else
return NULL;

46
patches/gcc-7.5.0/0003-cilkrts.diff Normal file
View File

@@ -0,0 +1,46 @@
diff --git a/libcilkrts/runtime/os-unix.c b/libcilkrts/runtime/os-unix.c
index c419fb68abf..155d8669e91 100644
--- a/libcilkrts/runtime/os-unix.c
+++ b/libcilkrts/runtime/os-unix.c
@@ -55,6 +55,7 @@
#if defined __linux__
# include <sys/sysinfo.h>
# include <sys/syscall.h>
+# include <sched.h>
#elif defined __APPLE__
# include <sys/sysctl.h>
@@ -452,28 +453,19 @@ COMMON_SYSDEP void __cilkrts_sleep(void)
COMMON_SYSDEP void __cilkrts_yield(void)
{
-#if defined(__ANDROID__) || \
- defined(__APPLE__) || \
- defined(__CYGWIN__) || \
- defined(__FreeBSD__) || \
- defined(__VXWORKS__) || \
- (defined(__sun__) && defined(__svr4__))
- // Call sched_yield to yield quantum. I'm not sure why we
- // don't do this on Linux also.
- sched_yield();
-#elif defined(__MIC__)
+#if defined(__MIC__)
// On MIC, pthread_yield() really trashes things. Arch's measurements
// showed that calling _mm_delay_32() (or doing nothing) was a better
// option. Delaying 1024 clock cycles is a reasonable compromise between
// giving up the processor and latency starting up when work becomes
// available
_mm_delay_32(1024);
-#elif defined(__linux__)
- // On Linux, call pthread_yield (which in turn will call sched_yield)
- // to yield quantum.
+#elif defined(__sun__) && !defined(__svr4__)
+ // On old SunOS call pthread_yield to yield a quantum.
pthread_yield();
#else
-# error "Unsupported architecture"
+ // On other platforms call sched_yield to yield a quantum.
+ sched_yield();
#endif
}

58
patches/gcc-7.5.0/0004-libatomic-test-fix.diff Normal file
View File

@@ -0,0 +1,58 @@
diff --git a/libatomic/testsuite/Makefile.am b/libatomic/testsuite/Makefile.am
index a9a0144185a..a19101aac54 100644
--- a/libatomic/testsuite/Makefile.am
+++ b/libatomic/testsuite/Makefile.am
@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \
_RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)"
+
+EXTRA_DEJAGNU_SITE_CONFIG = extra.exp
+
+extra.exp:
+ echo 'set BUILD_CC "$(CC)"' > $@.tmp
+ mv $@.tmp $@
diff --git a/libatomic/testsuite/Makefile.in b/libatomic/testsuite/Makefile.in
index adfc231484a..5400ac3ce11 100644
--- a/libatomic/testsuite/Makefile.in
+++ b/libatomic/testsuite/Makefile.in
@@ -223,6 +223,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)"
+EXTRA_DEJAGNU_SITE_CONFIG = extra.exp
all: all-am
.SUFFIXES:
@@ -429,6 +430,10 @@ uninstall-am:
uninstall uninstall-am
+extra.exp:
+ echo 'set BUILD_CC "$(CC)"' > $@.tmp
+ mv $@.tmp $@
+
# Tell versions [3.59,3.63) of GNU make to not export all variables.
# Otherwise a system limit (for SysV at least) may be exceeded.
.NOEXPORT:
diff --git a/libatomic/testsuite/lib/libatomic.exp b/libatomic/testsuite/lib/libatomic.exp
index cafab5432b7..dd2e1a4de49 100644
--- a/libatomic/testsuite/lib/libatomic.exp
+++ b/libatomic/testsuite/lib/libatomic.exp
@@ -74,6 +74,7 @@ proc libatomic_init { args } {
global ALWAYS_CFLAGS
global CFLAGS
global TOOL_EXECUTABLE TOOL_OPTIONS
+ global BUILD_CC
global GCC_UNDER_TEST
global TESTING_IN_BUILD_TREE
global target_triplet
@@ -89,6 +90,8 @@ proc libatomic_init { args } {
if ![info exists GCC_UNDER_TEST] then {
if [info exists TOOL_EXECUTABLE] {
set GCC_UNDER_TEST $TOOL_EXECUTABLE
+ } elseif [info exists BUILD_CC] {
+ set GCC_UNDER_TEST $BUILD_CC
} else {
set GCC_UNDER_TEST "[find_gcc]"
}

60
patches/gcc-7.5.0/0005-libgomp-test-fix.diff Normal file
View File

@@ -0,0 +1,60 @@
diff --git a/libgomp/testsuite/Makefile.am b/libgomp/testsuite/Makefile.am
index e2a3f460eb0..3309f71e02e 100644
--- a/libgomp/testsuite/Makefile.am
+++ b/libgomp/testsuite/Makefile.am
@@ -12,6 +12,11 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)"
+EXTRA_DEJAGNU_SITE_CONFIG = extra.exp
+
+extra.exp:
+ echo 'set BUILD_CC "$(CC)"' > $@.tmp
+ mv $@.tmp $@
# Instead of directly in ../testsuite/libgomp-test-support.exp.in, the
# following variables have to be "routed through" this Makefile, for expansion
diff --git a/libgomp/testsuite/Makefile.in b/libgomp/testsuite/Makefile.in
index 6edb7ae7ade..b3eddbc3e62 100644
--- a/libgomp/testsuite/Makefile.in
+++ b/libgomp/testsuite/Makefile.in
@@ -254,6 +254,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)"
+EXTRA_DEJAGNU_SITE_CONFIG = extra.exp
all: all-am
.SUFFIXES:
@@ -462,6 +463,10 @@ uninstall-am:
ps ps-am uninstall uninstall-am
+extra.exp:
+ echo 'set BUILD_CC "$(CC)"' > $@.tmp
+ mv $@.tmp $@
+
# Instead of directly in ../testsuite/libgomp-test-support.exp.in, the
# following variables have to be "routed through" this Makefile, for expansion
# of the several (Makefile) variables used therein.
diff --git a/libgomp/testsuite/lib/libgomp.exp b/libgomp/testsuite/lib/libgomp.exp
index 5e47872c5c4..b277c93047d 100644
--- a/libgomp/testsuite/lib/libgomp.exp
+++ b/libgomp/testsuite/lib/libgomp.exp
@@ -85,6 +85,7 @@ proc libgomp_init { args } {
global ALWAYS_CFLAGS
global CFLAGS
global TOOL_EXECUTABLE TOOL_OPTIONS
+ global BUILD_CC
global GCC_UNDER_TEST
global TESTING_IN_BUILD_TREE
global target_triplet
@@ -107,6 +108,8 @@ proc libgomp_init { args } {
if ![info exists GCC_UNDER_TEST] then {
if [info exists TOOL_EXECUTABLE] {
set GCC_UNDER_TEST $TOOL_EXECUTABLE
+ } elseif [info exists BUILD_CC] {
+ set GCC_UNDER_TEST $BUILD_CC
} else {
set GCC_UNDER_TEST "[find_gcc]"
}

58
patches/gcc-7.5.0/0006-libitm-test-fix.diff Normal file
View File

@@ -0,0 +1,58 @@
diff --git a/libitm/testsuite/Makefile.am b/libitm/testsuite/Makefile.am
index a9a0144185a..a19101aac54 100644
--- a/libitm/testsuite/Makefile.am
+++ b/libitm/testsuite/Makefile.am
@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \
_RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)"
+
+EXTRA_DEJAGNU_SITE_CONFIG = extra.exp
+
+extra.exp:
+ echo 'set BUILD_CC "$(CC)"' > $@.tmp
+ mv $@.tmp $@
diff --git a/libitm/testsuite/Makefile.in b/libitm/testsuite/Makefile.in
index eb9e992279d..1250e7f9a5a 100644
--- a/libitm/testsuite/Makefile.in
+++ b/libitm/testsuite/Makefile.in
@@ -234,6 +234,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)"
+EXTRA_DEJAGNU_SITE_CONFIG = extra.exp
all: all-am
.SUFFIXES:
@@ -440,6 +441,10 @@ uninstall-am:
uninstall uninstall-am
+extra.exp:
+ echo 'set BUILD_CC "$(CC)"' > $@.tmp
+ mv $@.tmp $@
+
# Tell versions [3.59,3.63) of GNU make to not export all variables.
# Otherwise a system limit (for SysV at least) may be exceeded.
.NOEXPORT:
diff --git a/libitm/testsuite/lib/libitm.exp b/libitm/testsuite/lib/libitm.exp
index 041629687f6..748f492c03d 100644
--- a/libitm/testsuite/lib/libitm.exp
+++ b/libitm/testsuite/lib/libitm.exp
@@ -74,6 +74,7 @@ proc libitm_init { args } {
global ALWAYS_CFLAGS
global CFLAGS
global TOOL_EXECUTABLE TOOL_OPTIONS
+ global BUILD_CC
global GCC_UNDER_TEST
global TESTING_IN_BUILD_TREE
global target_triplet
@@ -89,6 +90,8 @@ proc libitm_init { args } {
if ![info exists GCC_UNDER_TEST] then {
if [info exists TOOL_EXECUTABLE] {
set GCC_UNDER_TEST $TOOL_EXECUTABLE
+ } elseif [info exists BUILD_CC] {
+ set GCC_UNDER_TEST $BUILD_CC
} else {
set GCC_UNDER_TEST "[find_gcc]"
}

58
patches/gcc-7.5.0/0007-libvtv-test-fix.diff Normal file
View File

@@ -0,0 +1,58 @@
diff --git a/libvtv/testsuite/Makefile.am b/libvtv/testsuite/Makefile.am
index a9a0144185a..a19101aac54 100644
--- a/libvtv/testsuite/Makefile.am
+++ b/libvtv/testsuite/Makefile.am
@@ -11,3 +11,9 @@ EXPECT = $(shell if test -f $(top_builddir)/../expect/expect; then \
_RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)"
+
+EXTRA_DEJAGNU_SITE_CONFIG = extra.exp
+
+extra.exp:
+ echo 'set BUILD_CC "$(CC)"' > $@.tmp
+ mv $@.tmp $@
diff --git a/libvtv/testsuite/Makefile.in b/libvtv/testsuite/Makefile.in
index b5dfd29973c..9f672e9ae98 100644
--- a/libvtv/testsuite/Makefile.in
+++ b/libvtv/testsuite/Makefile.in
@@ -228,6 +228,7 @@ _RUNTEST = $(shell if test -f $(top_srcdir)/../dejagnu/runtest; then \
echo $(top_srcdir)/../dejagnu/runtest; else echo runtest; fi)
RUNTEST = "$(_RUNTEST) $(AM_RUNTESTFLAGS)"
+EXTRA_DEJAGNU_SITE_CONFIG = extra.exp
all: all-am
.SUFFIXES:
@@ -434,6 +435,10 @@ uninstall-am:
uninstall uninstall-am
+extra.exp:
+ echo 'set BUILD_CC "$(CC)"' > $@.tmp
+ mv $@.tmp $@
+
# Tell versions [3.59,3.63) of GNU make to not export all variables.
# Otherwise a system limit (for SysV at least) may be exceeded.
.NOEXPORT:
diff --git a/libvtv/testsuite/lib/libvtv.exp b/libvtv/testsuite/lib/libvtv.exp
index edf5fddbad2..a596091573b 100644
--- a/libvtv/testsuite/lib/libvtv.exp
+++ b/libvtv/testsuite/lib/libvtv.exp
@@ -74,6 +74,7 @@ proc libvtv_init { args } {
global ALWAYS_CFLAGS
global CFLAGS
global TOOL_EXECUTABLE TOOL_OPTIONS
+ global BUILD_CC
global GCC_UNDER_TEST
global TESTING_IN_BUILD_TREE
global target_triplet
@@ -89,6 +90,8 @@ proc libvtv_init { args } {
if ![info exists GCC_UNDER_TEST] then {
if [info exists TOOL_EXECUTABLE] {
set GCC_UNDER_TEST $TOOL_EXECUTABLE
+ } elseif [info exists BUILD_CC] {
+ set GCC_UNDER_TEST $BUILD_CC
} else {
set GCC_UNDER_TEST "[find_gcc]"
}

147
patches/gcc-7.5.0/0008-Revert-PR-driver-81523-Make-static-override-pie.diff Normal file
View File

@@ -0,0 +1,147 @@
diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h
index de605b0c466..2787a3d16be 100644
--- a/gcc/config/gnu-user.h
+++ b/gcc/config/gnu-user.h
@@ -50,28 +50,19 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#if defined HAVE_LD_PIE
#define GNU_USER_TARGET_STARTFILE_SPEC \
- "%{shared:; \
- pg|p|profile:gcrt1.o%s; \
- static:crt1.o%s; \
- " PIE_SPEC ":Scrt1.o%s; \
- :crt1.o%s} \
- crti.o%s \
- %{static:crtbeginT.o%s; \
- shared|" PIE_SPEC ":crtbeginS.o%s; \
- :crtbegin.o%s} \
+ "%{!shared: %{pg|p|profile:gcrt1.o%s;: \
+ %{" PIE_SPEC ":Scrt1.o%s} %{" NO_PIE_SPEC ":crt1.o%s}}} \
+ crti.o%s %{static:crtbeginT.o%s;: %{shared:crtbeginS.o%s} \
+ %{" PIE_SPEC ":crtbeginS.o%s} \
+ %{" NO_PIE_SPEC ":crtbegin.o%s}} \
%{fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_start_preinit.o%s; \
fvtable-verify=std:vtv_start.o%s} \
" CRTOFFLOADBEGIN
#else
#define GNU_USER_TARGET_STARTFILE_SPEC \
- "%{shared:; \
- pg|p|profile:gcrt1.o%s; \
- :crt1.o%s} \
- crti.o%s \
- %{static:crtbeginT.o%s; \
- shared|pie:crtbeginS.o%s; \
- :crtbegin.o%s} \
+ "%{!shared: %{pg|p|profile:gcrt1.o%s;:crt1.o%s}} \
+ crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \
%{fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_start_preinit.o%s; \
fvtable-verify=std:vtv_start.o%s} \
@@ -91,20 +82,15 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
"%{fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_end_preinit.o%s; \
fvtable-verify=std:vtv_end.o%s} \
- %{static:crtend.o%s; \
- shared|" PIE_SPEC ":crtendS.o%s; \
- :crtend.o%s} \
- crtn.o%s \
+ %{shared:crtendS.o%s;: %{" PIE_SPEC ":crtendS.o%s} \
+ %{" NO_PIE_SPEC ":crtend.o%s}} crtn.o%s \
" CRTOFFLOADEND
#else
#define GNU_USER_TARGET_ENDFILE_SPEC \
"%{fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_end_preinit.o%s; \
fvtable-verify=std:vtv_end.o%s} \
- %{static:crtend.o%s; \
- shared|pie:crtendS.o%s; \
- :crtend.o%s} \
- crtn.o%s \
+ %{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s \
" CRTOFFLOADEND
#endif
#undef ENDFILE_SPEC
diff --git a/gcc/config/sol2.h b/gcc/config/sol2.h
index d522de03f4a..13b27873719 100644
--- a/gcc/config/sol2.h
+++ b/gcc/config/sol2.h
@@ -174,9 +174,9 @@ along with GCC; see the file COPYING3. If not see
%{!ansi:values-Xa.o%s}"
#if defined(HAVE_LD_PIE) && defined(HAVE_SOLARIS_CRTS)
-#define STARTFILE_CRTBEGIN_SPEC "%{static:crtbegin.o%s; \
- shared|" PIE_SPEC ":crtbeginS.o%s; \
- :crtbegin.o%s}"
+#define STARTFILE_CRTBEGIN_SPEC "%{shared:crtbeginS.o%s} \
+ %{" PIE_SPEC ":crtbeginS.o%s} \
+ %{" NO_PIE_SPEC ":crtbegin.o%s}"
#else
#define STARTFILE_CRTBEGIN_SPEC "crtbegin.o%s"
#endif
@@ -224,9 +224,9 @@ along with GCC; see the file COPYING3. If not see
#endif
#if defined(HAVE_LD_PIE) && defined(HAVE_SOLARIS_CRTS)
-#define ENDFILE_CRTEND_SPEC "%{static:crtend.o%s; \
- shared|" PIE_SPEC ":crtendS.o%s; \
- :crtend.o%s}"
+#define ENDFILE_CRTEND_SPEC "%{shared:crtendS.o%s;: \
+ %{" PIE_SPEC ":crtendS.o%s} \
+ %{" NO_PIE_SPEC ":crtend.o%s}}"
#else
#define ENDFILE_CRTEND_SPEC "crtend.o%s"
#endif
diff --git a/gcc/gcc.c b/gcc/gcc.c
index e2fae4ef055..91eb0534722 100644
--- a/gcc/gcc.c
+++ b/gcc/gcc.c
@@ -873,7 +873,8 @@ proper position among the other output files. */
#endif
#ifdef ENABLE_DEFAULT_PIE
-#define PIE_SPEC "!no-pie"
+#define NO_PIE_SPEC "no-pie|static"
+#define PIE_SPEC NO_PIE_SPEC "|r|shared:;"
#define NO_FPIE1_SPEC "fno-pie"
#define FPIE1_SPEC NO_FPIE1_SPEC ":;"
#define NO_FPIE2_SPEC "fno-PIE"
@@ -894,6 +895,7 @@ proper position among the other output files. */
#define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;"
#else
#define PIE_SPEC "pie"
+#define NO_PIE_SPEC PIE_SPEC "|r|shared:;"
#define FPIE1_SPEC "fpie"
#define NO_FPIE1_SPEC FPIE1_SPEC ":;"
#define FPIE2_SPEC "fPIE"
@@ -922,7 +924,7 @@ proper position among the other output files. */
#else
#define LD_PIE_SPEC ""
#endif
-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
+#define LINK_PIE_SPEC "%{no-pie:} " "%{" PIE_SPEC ":" LD_PIE_SPEC "} "
#endif
#ifndef LINK_BUILDID_SPEC
@@ -1010,10 +1012,8 @@ proper position among the other output files. */
#endif
/* -u* was put back because both BSD and SysV seem to support it. */
-/* %{static|no-pie:} simply prevents an error message:
- 1. If the target machine doesn't handle -static.
- 2. If PIE isn't enabled by default.
- */
+/* %{static:} simply prevents an error message if the target machine
+ doesn't handle -static. */
/* We want %{T*} after %{L*} and %D so that it can be used to specify linker
scripts which exist in user specified directories, or in standard
directories. */
@@ -1030,7 +1030,7 @@ proper position among the other output files. */
"%{fuse-ld=*:-fuse-ld=%*} " LINK_COMPRESS_DEBUG_SPEC \
"%X %{o*} %{e*} %{N} %{n} %{r}\
%{s} %{t} %{u*} %{z} %{Z} %{!nostdlib:%{!nostartfiles:%S}} \
- %{static|no-pie:} %{L*} %(mfwrap) %(link_libgcc) " \
+ %{static:} %{L*} %(mfwrap) %(link_libgcc) " \
VTABLE_VERIFICATION_SPEC " " SANITIZER_EARLY_SPEC " %o " CHKP_SPEC " \
%{fopenacc|fopenmp|%:gt(%{ftree-parallelize-loops=*:%*} 1):\
%:include(libgomp.spec)%(link_gomp)}\

57
patches/gcc-7.5.0/0009-Revert-RS6000-linux-startfile-endfile.diff Normal file
View File

@@ -0,0 +1,57 @@
diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
index cbee89140dd..de386291a51 100644
--- a/gcc/config/rs6000/sysv4.h
+++ b/gcc/config/rs6000/sysv4.h
@@ -757,34 +757,24 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN)
#define CRTOFFLOADEND ""
#endif
-/* STARTFILE_LINUX_SPEC should be the same as GNU_USER_TARGET_STARTFILE_SPEC
- but with the mnewlib ecrti.o%s selection substituted for crti.o%s. */
-#define STARTFILE_LINUX_SPEC \
- "%{shared:; \
- pg|p|profile:gcrt1.o%s; \
- static:crt1.o%s; \
- " PIE_SPEC ":Scrt1.o%s; \
- :crt1.o%s} \
- %{mnewlib:ecrti.o%s;:crti.o%s} \
- %{static:crtbeginT.o%s; \
- shared|" PIE_SPEC ":crtbeginS.o%s; \
- :crtbegin.o%s} \
- %{fvtable-verify=none:%s; \
- fvtable-verify=preinit:vtv_start_preinit.o%s; \
- fvtable-verify=std:vtv_start.o%s} \
- " CRTOFFLOADBEGIN
-
-/* ENDFILE_LINUX_SPEC should be the same as GNU_USER_TARGET_ENDFILE_SPEC
- but with the mnewlib ecrtn.o%s selection substituted for crtn.o%s. */
-#define ENDFILE_LINUX_SPEC \
- "%{fvtable-verify=none:%s; \
- fvtable-verify=preinit:vtv_end_preinit.o%s; \
- fvtable-verify=std:vtv_end.o%s} \
- %{static:crtend.o%s; \
- shared|" PIE_SPEC ":crtendS.o%s; \
- :crtend.o%s} \
- %{mnewlib:ecrtn.o%s;:crtn.o%s} \
- " CRTOFFLOADEND
+#ifdef HAVE_LD_PIE
+#define STARTFILE_LINUX_SPEC "\
+%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \
+%{mnewlib:ecrti.o%s;:crti.o%s} \
+%{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \
+" CRTOFFLOADBEGIN
+#else
+#define STARTFILE_LINUX_SPEC "\
+%{!shared: %{pg|p|profile:gcrt1.o%s;:crt1.o%s}} \
+%{mnewlib:ecrti.o%s;:crti.o%s} \
+%{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \
+" CRTOFFLOADBEGIN
+#endif
+
+#define ENDFILE_LINUX_SPEC "\
+%{shared|pie:crtendS.o%s;:crtend.o%s} \
+%{mnewlib:ecrtn.o%s;:crtn.o%s} \
+" CRTOFFLOADEND
#define LINK_START_LINUX_SPEC ""

59
patches/gcc-7.5.0/0010-static-pie-support.diff Normal file
View File

@@ -0,0 +1,59 @@
diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h
index 2787a3d16be..ee7b781319e 100644
--- a/gcc/config/gnu-user.h
+++ b/gcc/config/gnu-user.h
@@ -51,10 +51,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
#if defined HAVE_LD_PIE
#define GNU_USER_TARGET_STARTFILE_SPEC \
"%{!shared: %{pg|p|profile:gcrt1.o%s;: \
- %{" PIE_SPEC ":Scrt1.o%s} %{" NO_PIE_SPEC ":crt1.o%s}}} \
- crti.o%s %{static:crtbeginT.o%s;: %{shared:crtbeginS.o%s} \
+ %{" PIE_SPEC ":%{static:rcrt1.o%s;:Scrt1.o%s}} %{" NO_PIE_SPEC ":crt1.o%s}}} \
+ crti.o%s %{shared:crtbeginS.o%s;: \
%{" PIE_SPEC ":crtbeginS.o%s} \
- %{" NO_PIE_SPEC ":crtbegin.o%s}} \
+ %{" NO_PIE_SPEC ":%{static:crtbeginT.o%s;:crtbegin.o%s}}} \
%{fvtable-verify=none:%s; \
fvtable-verify=preinit:vtv_start_preinit.o%s; \
fvtable-verify=std:vtv_start.o%s} \
diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
index de386291a51..577fddc8a7c 100644
--- a/gcc/config/rs6000/sysv4.h
+++ b/gcc/config/rs6000/sysv4.h
@@ -759,9 +759,12 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN)
#ifdef HAVE_LD_PIE
#define STARTFILE_LINUX_SPEC "\
-%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \
+%{!shared: %{pg|p|profile:gcrt1.o%s;: \
+ %{" PIE_SPEC ":%{static:rcrt1.o%s;:Scrt1.o%s}} %{" NO_PIE_SPEC ":crt1.o%s}}} \
%{mnewlib:ecrti.o%s;:crti.o%s} \
-%{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \
+%{shared:crtbeginS.o%s;: \
+ %{" PIE_SPEC ":crtbeginS.o%s} \
+ %{" NO_PIE_SPEC ":%{static:crtbeginT.o%s;:crtbegin.o%s}}} \
" CRTOFFLOADBEGIN
#else
#define STARTFILE_LINUX_SPEC "\
diff --git a/gcc/gcc.c b/gcc/gcc.c
index 91eb0534722..74a390e6005 100644
--- a/gcc/gcc.c
+++ b/gcc/gcc.c
@@ -873,7 +873,7 @@ proper position among the other output files. */
#endif
#ifdef ENABLE_DEFAULT_PIE
-#define NO_PIE_SPEC "no-pie|static"
+#define NO_PIE_SPEC "no-pie"
#define PIE_SPEC NO_PIE_SPEC "|r|shared:;"
#define NO_FPIE1_SPEC "fno-pie"
#define FPIE1_SPEC NO_FPIE1_SPEC ":;"
@@ -919,7 +919,7 @@ proper position among the other output files. */
#ifndef LINK_PIE_SPEC
#ifdef HAVE_LD_PIE
#ifndef LD_PIE_SPEC
-#define LD_PIE_SPEC "-pie"
+#define LD_PIE_SPEC "-pie %{static:--no-dynamic-linker -Bsymbolic}"
#endif
#else
#define LD_PIE_SPEC ""

346
patches/gcc-7.5.0/0011-j2.diff Normal file
View File

@@ -0,0 +1,346 @@
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 6e75bd45fb9..8ab5f15ea8e 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -474,7 +474,7 @@ s390*-*-*)
extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h"
;;
# Note the 'l'; we need to be able to match e.g. "shle" or "shl".
-sh[123456789lbe]*-*-* | sh-*-*)
+sh[123456789lbej]*-*-* | sh-*-*)
cpu_type=sh
extra_options="${extra_options} fused-madd.opt"
extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o"
@@ -2664,18 +2664,18 @@ s390x-ibm-tpf*)
extra_options="${extra_options} s390/tpf.opt"
tmake_file="${tmake_file} s390/t-s390"
;;
-sh-*-elf* | sh[12346l]*-*-elf* | \
- sh-*-linux* | sh[2346lbe]*-*-linux* | \
+sh-*-elf* | sh[12346lj]*-*-elf* | \
+ sh-*-linux* | sh[2346lbej]*-*-linux* | \
sh-*-netbsdelf* | shl*-*-netbsdelf*)
tmake_file="${tmake_file} sh/t-sh sh/t-elf"
if test x${with_endian} = x; then
case ${target} in
- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;;
+ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;;
shbe-*-* | sheb-*-*) with_endian=big,little ;;
sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;;
shl* | sh*-*-linux* | \
sh-superh-elf) with_endian=little,big ;;
- sh[1234]*-*-*) with_endian=big ;;
+ sh[j1234]*-*-*) with_endian=big ;;
*) with_endian=big,little ;;
esac
fi
@@ -2742,6 +2742,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;;
sh2a*) sh_cpu_target=sh2a ;;
sh2e*) sh_cpu_target=sh2e ;;
+ shj2*) sh_cpu_target=shj2;;
sh2*) sh_cpu_target=sh2 ;;
*) sh_cpu_target=sh1 ;;
esac
@@ -2763,7 +2764,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
- sh3e | sh3 | sh2e | sh2 | sh1) ;;
+ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;;
"") sh_cpu_default=${sh_cpu_target} ;;
*) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
esac
@@ -2772,9 +2773,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
case ${target} in
sh[1234]*) sh_multilibs=${sh_cpu_target} ;;
sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;;
+ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;;
sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;;
- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
+ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;;
esac
if test x$with_fp = xno; then
sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
@@ -2789,7 +2790,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
m1 | m2 | m2e | m3 | m3e | \
m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \
- m2a | m2a-single | m2a-single-only | m2a-nofpu)
+ m2a | m2a-single | m2a-single-only | m2a-nofpu | \
+ mj2)
# TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
# It is passed to MULTIILIB_OPTIONS verbatim.
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
@@ -2806,7 +2808,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
done
TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
if test x${enable_incomplete_targets} = xyes ; then
- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1"
+ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1"
fi
tm_file="$tm_file ./sysroot-suffix.h"
tmake_file="$tmake_file t-sysroot-suffix"
@@ -4380,6 +4382,8 @@ case "${target}" in
;;
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
;;
+ mj2)
+ ;;
*)
echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2
echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
@@ -4589,7 +4593,7 @@ case ${target} in
tmake_file="rs6000/t-rs6000 ${tmake_file}"
;;
- sh[123456ble]*-*-* | sh-*-*)
+ sh[123456blej]*-*-* | sh-*-*)
c_target_objs="${c_target_objs} sh-c.o"
cxx_target_objs="${cxx_target_objs} sh-c.o"
;;
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index ff79b93adc2..5fe3f3bfe69 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -662,6 +662,7 @@ parse_validate_atomic_model_option (const char* str)
model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
model_names[sh_atomic_model::soft_imask] = "soft-imask";
+ model_names[sh_atomic_model::hard_cas] = "hard-cas";
const char* model_cdef_names[sh_atomic_model::num_models];
model_cdef_names[sh_atomic_model::none] = "NONE";
@@ -669,6 +670,7 @@ parse_validate_atomic_model_option (const char* str)
model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
+ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS";
sh_atomic_model ret;
ret.type = sh_atomic_model::none;
@@ -747,6 +749,9 @@ got_mode_name:;
if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
err_ret ("cannot use atomic model %s in user mode", ret.name);
+ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2)
+ err_ret ("atomic model %s is only available J2 targets", ret.name);
+
return ret;
#undef err_ret
@@ -803,6 +808,8 @@ sh_option_override (void)
sh_cpu = PROCESSOR_SH2E;
if (TARGET_SH2A)
sh_cpu = PROCESSOR_SH2A;
+ if (TARGET_SHJ2)
+ sh_cpu = PROCESSOR_SHJ2;
if (TARGET_SH3)
sh_cpu = PROCESSOR_SH3;
if (TARGET_SH3E)
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index b13d1b3c943..9e24649d189 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -83,6 +83,7 @@ extern int code_for_indirect_jump_scratch;
#define SUPPORT_SH4_SINGLE 1
#define SUPPORT_SH2A 1
#define SUPPORT_SH2A_SINGLE 1
+#define SUPPORT_SHJ2 1
#endif
#define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
@@ -115,6 +116,7 @@ extern int code_for_indirect_jump_scratch;
#define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
#define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
#define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
+#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2)
#if SUPPORT_SH1
#define SUPPORT_SH2 1
@@ -122,6 +124,7 @@ extern int code_for_indirect_jump_scratch;
#if SUPPORT_SH2
#define SUPPORT_SH3 1
#define SUPPORT_SH2A_NOFPU 1
+#define SUPPORT_SHJ2 1
#endif
#if SUPPORT_SH3
#define SUPPORT_SH4_NOFPU 1
@@ -154,7 +157,7 @@ extern int code_for_indirect_jump_scratch;
#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
| MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
| MASK_HARD_SH4 | MASK_FPU_SINGLE \
- | MASK_FPU_SINGLE_ONLY)
+ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2)
/* This defaults us to big-endian. */
#ifndef TARGET_ENDIAN_DEFAULT
@@ -229,7 +232,8 @@ extern int code_for_indirect_jump_scratch;
%{m2a-single:--isa=sh2a} \
%{m2a-single-only:--isa=sh2a} \
%{m2a-nofpu:--isa=sh2a-nofpu} \
-%{m4al:-dsp}"
+%{m4al:-dsp} \
+%{mj2:-isa=j2}"
#define ASM_SPEC SH_ASM_SPEC
@@ -345,6 +349,7 @@ struct sh_atomic_model
hard_llcs,
soft_tcb,
soft_imask,
+ hard_cas,
num_models
};
@@ -388,6 +393,9 @@ extern const sh_atomic_model& selected_atomic_model (void);
#define TARGET_ATOMIC_SOFT_IMASK \
(selected_atomic_model ().type == sh_atomic_model::soft_imask)
+#define TARGET_ATOMIC_HARD_CAS \
+ (selected_atomic_model ().type == sh_atomic_model::hard_cas)
+
#endif // __cplusplus
#define SUBTARGET_OVERRIDE_OPTIONS (void) 0
@@ -1568,7 +1576,7 @@ extern bool current_function_interrupt;
/* Nonzero if the target supports dynamic shift instructions
like shad and shld. */
-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
+#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2)
/* The cost of using the dynamic shift insns (shad, shld) are the same
if they are available. If they are not available a library function will
@@ -1833,6 +1841,7 @@ enum processor_type {
PROCESSOR_SH2,
PROCESSOR_SH2E,
PROCESSOR_SH2A,
+ PROCESSOR_SHJ2,
PROCESSOR_SH3,
PROCESSOR_SH3E,
PROCESSOR_SH4,
diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
index c4f0d964d00..792af395b5d 100644
--- a/gcc/config/sh/sh.opt
+++ b/gcc/config/sh/sh.opt
@@ -65,6 +65,10 @@ m2e
Target RejectNegative Condition(SUPPORT_SH2E)
Generate SH2e code.
+mj2
+Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2)
+Generate J2 code.
+
m3
Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
Generate SH3 code.
diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md
index b46ac3131a8..72705583f84 100644
--- a/gcc/config/sh/sync.md
+++ b/gcc/config/sh/sync.md
@@ -240,6 +240,9 @@
|| (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem,
exp_val, new_val);
+ else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode)
+ atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem,
+ exp_val, new_val);
else if (TARGET_ATOMIC_SOFT_GUSA)
atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem,
exp_val, new_val);
@@ -306,6 +309,57 @@
}
[(set_attr "length" "14")])
+(define_expand "atomic_compare_and_swapsi_cas"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "r")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{
+ rtx mem = gen_rtx_REG (SImode, 0);
+ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0)));
+ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3]));
+ DONE;
+})
+
+(define_insn "shj2_cas"
+ [(set (match_operand:SI 0 "register_operand" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "register_operand" "=r")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "0")]
+ UNSPECV_CMPXCHG_1))
+ (set (reg:SI T_REG)
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))]
+ "TARGET_ATOMIC_HARD_CAS"
+ "cas.l %2,%0,@%1"
+ [(set_attr "length" "2")]
+)
+
+(define_expand "atomic_compare_and_swapqi_cas"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "arith_operand" "rI08")
+ (match_operand:SI 3 "arith_operand" "rI08")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{FAIL;}
+)
+
+(define_expand "atomic_compare_and_swaphi_cas"
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
+ (unspec_volatile:SI
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
+ (match_operand:SI 2 "arith_operand" "rI08")
+ (match_operand:SI 3 "arith_operand" "rI08")]
+ UNSPECV_CMPXCHG_1))]
+ "TARGET_ATOMIC_HARD_CAS"
+{FAIL;}
+)
+
;; The QIHImode llcs patterns modify the address register of the memory
;; operand. In order to express that, we have to open code the memory
;; operand. Initially the insn is expanded like every other atomic insn
diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh
index 409554a8c8d..d354c11c8f2 100644
--- a/gcc/config/sh/t-sh
+++ b/gcc/config/sh/t-sh
@@ -50,7 +50,8 @@ MULTILIB_MATCHES = $(shell \
m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \
m2a-single,m2a-single-only \
m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
- m4,m4-100,m4-200,m4-300,m4a; do \
+ m4,m4-100,m4-200,m4-300,m4a \
+ mj2; do \
subst= ; \
for lib in `echo $$abi|tr , ' '` ; do \
if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \
@@ -63,9 +64,9 @@ MULTILIB_MATCHES = $(shell \
# SH1 and SH2A support big endian only.
ifeq ($(DEFAULT_ENDIAN),ml)
-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
else
-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
endif
MULTILIB_OSDIRNAMES = \
@@ -87,7 +88,8 @@ MULTILIB_OSDIRNAMES = \
m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \
m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \
m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \
- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al
+ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \
+ mj2=!j2
$(out_object_file): gt-sh.h
gt-sh.h : s-gtype ; @true

14
patches/gcc-7.5.0/0012-s390x-muslldso.diff Normal file
View File

@@ -0,0 +1,14 @@
diff --git a/gcc/config/s390/linux.h b/gcc/config/s390/linux.h
index 739df00f62d..ccd48ee7b84 100644
--- a/gcc/config/s390/linux.h
+++ b/gcc/config/s390/linux.h
@@ -76,6 +76,9 @@ along with GCC; see the file COPYING3. If not see
#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
#define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1"
+#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-s390.so.1"
+#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-s390x.so.1"
+
#undef LINK_SPEC
#define LINK_SPEC \
"%{m31:-m elf_s390}%{m64:-m elf64_s390} \

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